Technical Brief High-Speed Board Design Advisor Power Distribution Network

Transcription

1 Introduction Technical Brie High-Speed Board Design Advisor Power Distribution Network This document contains a step-by-step tutorial and checklist o best-practice guidelines to design and review a power distribution network (PDN). Altera provides the Decoupling Design Tool to acilitate the process o selection o the decoupling capacitors or a PDN design. The method described here uses the Frequency Domain Target Impedance Method. Additional PDN-related papers and online lectures can be ound in Further Inormation. This document assumes amiliarity with the ollowing tools and support collateral: Stratix II GX Handbook: Stratix II GX Pinouts: PowerPlay Early Power Estimator (EPE) Spreadsheet and User Guide: Decoupling Design Tool and User Guide: Available rom an Altera sales representative: Quartus II Development Sotware Handbook: Altera Stratix II GX FPGA-based development kits deliver quality-proven implementations and comprise board schematics, layout iles, and board-speciic guidelines documents which can be used as a starting point or user designs: Transceiver Signal Integrity Development Kit, Stratix II GX Edition: PCI Express Development Kit, Stratix II GX Edition: Audio Video Development Kit, Stratix II GX Edition: Calculate the Target Impedance or Each Voltage Rail Reer to the Stratix II GX Transceiver User Guide section o the Stratix II GX Handbook or urther inormation about transceivers modes and eatures. Determine the settings or each transceiver quad (number o channels, data rate, mode, pre-emphasis settings, V OD ). Choose the maximum expected values or conservative estimations. Use the PowerPlay EPE spreadsheet and enter the transceiver settings in the XCVR tab. Design separate power supply rails and decoupling networks or the power supplies o the ollowing groups. Power supply voltage may vary and urther separation o power supplies may be needed depending on the requirements o the application. V CCT, V CCL, and V CCR (1.2V analog transceiver power supply) V CCH (1.2/1.5V transceiver buer) V CCA (3.3V analog transceiver power supply) V CCP (1.2V digital transceiver power supply) V CCINT (1.2V core power supply) V CCPD (3.3V I/O pre-driver supply) V CCIO (1.2V, 1.5V, 1.8V, 2.5V, 3.3V I/O power supply) TB November 2007, ver

2 High-Speed Board Design Advisor Altera Corporation Reer to High-Speed Board Design Advisor: Pinout Deinition or a detailed pin description: Use a contiguous ground (VSS) plane without splits or all transceiver unctions. Derive maximum current (A) values rom the PowerPlay EPE Spreadsheet and enter the values in Table 1. Reer to the EPE User Guide and the Quartus II Handbook, Volume 3, Section III or a detailed description o the tools used with Quartus II development sotware. Calculate the maximum transient currents. A best practice guideline is to use 50 percent o the maximum current as estimation or the transient current. The maximum transient current is calculated rom maximum current used minus minimum current used or a given design or by measurement or simulations. Since none o these methods are routinely available, Altera recommends the 50 percent rule or the PDN design. Speciy the maximum tolerable ripple. A good design practice is to allow ±2 percent or less ripple or all analog transceiver supplies V CCT, V CCL, V CCR, V CCA, V CCH and V CCP, ±5 percent total power supply tolerance or V CCIO and V CCPD, and ±50mV or V CCINT. VoltageRail %Ripple Use Table 1 to calculate the target impedance or a PDN using the equation Z Target = MaxTransientCurrent Enter target impedance values into Decoupling Design Tool. Table 1. Calculation o the Target Impedance Voltage Rail Voltage (V) % Ripple Max Current (A) Maximum Transient Current (A) Target Impedance Z Target V CCT 1.2V 2% V CCL 1.2V 2% V CCR 1.2V 2% V CCH 1.2/1.5V 2% V CCA 3.3V 2% V CCP 1.2V 2% V CCINT 1.2V ±50mV V CCPD 3.3V 5% V CCIO 1.5V 1.8V 2.5V 3.3V 5% The Decoupling Design Tool requires choosing three capacitor values per decade (n). The irst tab in the spreadsheet contains the capacitor library. Enter the capacitor values, ESL, and ESR or all capacitors used. Select the Voltage Regulator Module and Determine the Decoupling Capacitance Values at the Lowest Frequency Set the Voltage Regulator Modules (VRM) as either switching regulators or linear regulators. For VRM design examples, reer to the Stratix II GX development kit documentation. The ollowing voltage regulator vendors provide recommendations about Altera device power supply options: Obtain the ESR and ESL values rom the VRM vendor. Alternatively, take measurements using a low requency network analyzer or get the impedance proile rom the VRM vendor and extract ESR and ESL values. Enter the ESR and ESL values in the Decoupling Design Tool. 2

3 Altera Corporation High-Speed Board Design Advisor Determine the eective requency range o the VRM (target requency = VRM impedance, typical ~10 khz). Above this minimum requency the board-level PDN must be designed to keep the impedance below the target impedance. Choose enough low C or low requency decoupling (bulk capacitors). Use the Decoupling Design Tool to adjust the composite requency response to stay below the target impedance in the low-requency range by changing the lower requency decoupling capacitance value or number o capacitors or each voltage rail. Allow a comortable margin, but take into account the trade-o between perormance and cost. Determine Decoupling Capacitance Values at the Highest Frequency The highest requency o interest determines the maximum requency at which the board decoupling can be eective. Beyond this requency, the FPGA device and package impedance dominates the PDN. For Stratix II GX FPGAs, use 50 MHz or V CCINT and 200 MHz or all other power rails. Those values are preconigured in the Decoupling Design Tool or each voltage rail. The PCB power and ground planes are used or high-requency decoupling. Model the impedance o the planes as an ideal transmission line using the ormulas in the Decoupling Design Tool User Guide, Section 3.2.3, and calculate the equivalent ESR and ESL values. Enter the results in the Decoupling Design Tool or each voltage rail. The capacitance is insigniicant compared to the capacitance o the chip and can be neglected. Ideally, the lowest impedance requency o the planes matches the range o the highest requency o interest. Select the Decoupling Capacitor Network or Each Power Rail In the mid- to high-requency range, a single capacitor cannot provide a low enough ESL to meet the target impedance. Thereore, use multiple capacitors in parallel. Get the ESR and ESL value rom the capacitor vendor. ESL rom the vendor does not relect the total mounted inductance (ESL Total ) since this is dependant on how and where the capacitor is mounted on the planes. Get the lowest, practical total mounted inductance o the capacitors by using the ollowing guidelines: Use short, wide capacitors, such as 0402, 0508, IDC, or X2Y Use short surace traces to connect capacitor pads to the vias connected to the planes below (minimum size solder dams, vias as close to device as possible) Use wide surace traces Use multiple via pairs Place capacitors on the back side o the package within the power and ground ring (eliminates spreading inductance) Place power and ground planes close to the surace where the capacitors are attached Use a thin dielectric between power and ground planes Use multiple power and ground plane pairs Don't use a surace trace to route to a package pad (cost is ~13 ph/mil) Don't share vias o adjacent capacitors Use large diameter vias Place capacitors close to package Bring opposite current vias close together Place same current vias ar apart Place capacitor in the middle o the board rather than at edges and corners Use V CC planes or high requency and transient currents at the surace o the FPGA side o the PCB stackup Estimate or calculate the total ESL (ESL Total = intrinsic ESL + mounting inductance) o the decoupling capacitors using the ormulas in the Decoupling Design Tool User Guide, Section Alternatively, use the deault ESR, ESL, and mounting inductance values in the Decoupling Design Tool or 0402 or 0603 capacitor ootprints. Enter the values in the Decoupling Design Tool spreadsheet. The capacitor values selected in the tool use three dierent capacitance values per decade. 3

4 High-Speed Board Design Advisor Altera Corporation Adjust the composite requency response to stay below the target impedance in the target requency range with the least amount o capacitors, while continuously evaluating the trade-o between extra margin and cost. An example result is shown in Figure 2. Eective Decoupling Radius The eectiveness o the decoupling capacitor is directly proportional to its distance to the associated load. Decoupling capacitors are most eective when they are located at the point o load or using the wavelength over 40 rule: D EFF = eective distance = 1/10 o 1/4 wavelength at the resonant requency o the decoupling capacitor λ D EFF = with λ =, 40 velocity R = R 2π ESL Total C Use the ollowing equation to calculate the eective decoupling radius/distance: 2π ESL Total C D EFF = , velocity = 180 ps/in (e.g., or FR-4) velocity 40 Examples using ESL Total = 1.9 nh = 0.4 nh (ESL) nh (mounting inductance), are shown in Table 2. Table 2. ESL Total Examples Cap Value (uf) 1.0 uf 0.1 uf 0.01 uf uf Eective Decoupling Radius (in) Highest requency response capacitors would ideally be mounted close to the power supply pins. Use low mounting inductance placement guidelines or low ESL Total. Optimize the Board Stackup or Low Impedance Power and Ground Planes Under Consideration o Manuacturability and Cost Choose the thinnest possible dielectric between power and ground planes. Place power and ground planes as close to the suraces as possible. Use as many power and ground plane pairs as practical: One plane place close to the surace with capacitors and package on the same side Two planes place close to the top and bottom surace Three planes place one close to top surace, one close to bottom surace, and one in the middle Use the highest dissipation actor laminate as possible Validate the PDN perormance with measurements or simulations rom DC to the highest requency o interest. The ollowing igures are screen shots taken rom the Decoupling Design Tool. Figure 1 illustrates the use o the capacitor spreadsheets. Figure 2 shows the adjustment o the composite requency response in order to match the target requency. 4

5 Altera Corporation High-Speed Board Design Advisor Figure 1. Capacitor Spreadsheet Mounting Inductance (nh) Total Inductance (nh) Number ESR ESL Cap Value Units Footprint o Caps (ohm) (nh) uf 2.00E E uf 2.00E E uf 2.00E E uf 2.00E E uf 2.00E E uf 2.00E E uf 2.00E E uf 2.00E E uf 2.00E E uf 2.00E E uf 2.00E E uf 2.00E E uf 2.00E E uf 2.00E+00 PCB uf 2.00E+00 VRM High Frequency Target (Fh) Target Impedance (ohm) (MHz) Figure 2. Composite Frequency Response Adjustment VCCIO Impedance uf uf uf 0.01 uf uf uf 0.1 uf 0.22 uf 0.47 uf 1uF 2.2 uf 4.7 uf 330 uf PCB VRM Ze Target Fh E E E E E E+09 Frequency Further Inormation Frequency Domain Target Impedance Method or Bypass Capacitor Selection or Power Distribution Systems, Larry D. Smith o Altera Corporation, DesignCon Dr. Eric Bogatin s online lecture, OLL Best Board Design Practices or Power Distribution Network : Power Distribution system Design Methodology and Capacitor selection or Modern CMOS Technology, Manuscript o paper published in IEEE Transaction on Advanced Packaging, August, 1999, pp by Larry Smith, Raymond Anderson, Doug Forehand, Tom Pelc, and Tanmoy Roy, all o Sun Microsystems Inc. 5

6 High-Speed Board Design Advisor Altera Corporation Power Plane SPICE Models and Simulated Perormance or Materials and Geometries, Manuscript o paper published in IEEE Transactions on Advanced Packaging, August 2001 edition by Larry Smith, Raymond Anderson, and Tanmoy Roy. Distributed SPICE Circuit Model or Ceramic Capacitors, Presented at IEEE ECTC Conerence, Lake Buena Vista, Florida May 29-June 1, 2001 by Larry Smith and David Hockanson o Sun Microsystems. A Transmission-Line Model or Ceramic Capacitors or CAD Tools Based on Measured Parameters, Published in the Conerence Record, Electrical Components Technology Conerence (ECTC) May 2002, San Diego, CA by Larry D. Smith, David Hockanson, Krina Kothari, all o Sun Microsystems Inc. Model to Hardware Correlation or Power Distribution Induced I/O Noise in a Functioning Computer System, Published in the Conerence Record o ECTC 2002 at San Diego, Cali. by Sungjun Chun (GaTech), Larry Smith, Ray Anderson (both o Sun Microsystems), and Madhavan Swaminathan (GaTech). ESR and ESL o Ceramic Capacitors Applied to Decoupling Applications, presented at the IEEE Electrical Perormance o Electronic Packaging Conerence (EPEP) Oct by Larry Smith o Sun Microsystems and John Prymak o Kemet Electronic Corporation. Chip-Package Resonance in Core Power Supply Structures or a High Power Microprocessor, Published in the Proceedings o IPACK'01, the Paciic Rim/ASME International Electronics Packaging Technical Conerence and Exhibition, July 8-13, 2001, Kauai, Hawaii USA by Larry Smith, Raymond Anderson, Tanmoy Roy, all o Sun Microsystems. Simultaneous Switch Noise and Power Plane Bounce or CMOS Technology, presented at the IEEE electrical Perormance o Electrical Packaging (EPEP) Conerence, San Diego, CA October 17-25, 1999 by Larry Smith o Sun Microsystems. Power Plane Spice Models or Frequency and Time Domains, presented at the IEEE Perormance o Electrical Packaging (EPEP) Conerence 2000 (EPEP 2000), October 2000 at Scottsdale, Arizona by Larry Smith, Raymond Anderson, and Tanmoy Roy, all o Sun Microsystems. Power Distribution System or JEDEC DDR2 Memory DIMM, published in Conerence Record, IEEE Electrical Perormance o Electronic Packages 2003 (EPEP 2003), Princeton, NJ, pp October 2003 by Larry D. Smith and Jerey Lee o Sun Microsystems Inc. High-Speed Board Design Advisor: Thermal Management: High-Speed Board Design Advisor: Pinout Deinition: High-Speed Board Design Advisor: High-Speed Channel Design and Layout: High-Speed Board Design Advisor: Hardware Integration, Test, and Debug: Innovation Drive San Jose, CA Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, speciic device designations, and all other words and logos that are identiied as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks o Altera Corporation in the U.S. and other countries. All other product or service names are the property o their respective holders. Altera products are protected under numerous U.S. and oreign patents and pending applications, maskwork rights, and copyrights. Altera warrants perormance o its semiconductor products to current speciications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out o the application or use o any inormation, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version o device speciications beore relying on any published inormation and beore placing orders or products or services. 6