MAX 10 Analog to Digital Converter User Guide

Transcription

1 MAX 10 Analog to Digital Converter User Guide Subscribe UG-M10ADC 101 Innovation Drive San Jose, CA

2 TOC-2 Contents MAX 10 ADC Overview ADC Block Counts in MAX 10 Devices ADC Channel Counts in MAX 10 Devices MAX 10 ADC Vertical Migration Support MAX 10 Single or Dual Supply Devices MAX 10 ADC Conversion MAX 10 ADC Architecture and Features MAX 10 ADC Hard IP Block ADC Block Locations Single or Dual ADC Devices ADC Analog Input Pins ADC Prescaler ADC Clock Sources ADC Voltage Reference ADC Temperature Sensing Diode ADC Sequencer ADC Timing Altera Modular ADC and Altera Modular Dual ADC IP Cores Altera Modular ADC IP Core Configuration Variants Altera Modular ADC and Altera Modular Dual ADC IP Cores Architecture Altera ADC HAL Driver MAX 10 ADC Design Considerations Guidelines: ADC Ground Plane Connection Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) Guidelines: Board Design for Analog Input Guidelines: Board Design for ADC Reference Voltage Pin MAX 10 ADC Implementation Guides Creating MAX 10 ADC Design Customizing and Generating Altera Modular ADC IP Core Parameters Settings for Generating ALTPLL IP Core Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core Completing ADC Design Altera Modular ADC IP Core References Altera Modular ADC Parameters Settings

3 TOC-3 Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping Altera Modular Dual ADC Parameters Settings Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping Altera Modular ADC and Altera Modular Dual ADC Interface Signals Command Interface of Altera Modular ADC and Altera Modular Dual ADC Response Interface of Altera Modular ADC and Altera Modular Dual ADC Threshold Interface of Altera Modular ADC and Altera Modular Dual ADC CSR Interface of Altera Modular ADC and Altera Modular Dual ADC IRQ Interface of Altera Modular ADC and Altera Modular Dual ADC Peripheral Clock Interface of Altera Modular ADC and Altera Modular Dual ADC Peripheral Reset Interface of Altera Modular ADC and Altera Modular Dual ADC ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual ADC ADC PLL Locked Interface of Altera Modular ADC and Altera Modular Dual ADC Altera Modular ADC Register Definitions Sequencer Core Registers Sample Storage Core Registers ADC HAL Device Driver for Nios II Gen Additional Information for MAX 10 Analog to Digital Converter User Guide... A-1 Document Revision History for MAX 10 Analog to Digital Converter User Guide...A-1

4 MAX 10 ADC Overview 1 UG-M10ADC Subscribe MAX 10 devices feature up to two analog-to-digital converters (ADC). The ADCs provide the MAX 10 devices with built-in capability for on-die temperature monitoring and external analog signal conversion. The ADC solution consists of hard IP blocks in the MAX 10 device periphery and soft logic through the Altera Modular ADC IP core. The ADC solution provides you with built-in capability to translate analog quantities to digital data for information processing, computing, data transmission, and control systems. The basic function is to provide a 12 bit digital representation of the analog signal being observed. The ADC solution works in two modes: Normal mode monitors single-ended external inputs with a cumulative sampling rate of 1 million samples per second (MSPS): Single ADC devices up to 17 single-ended external inputs (one dedicated analog and 16 dual function input pins) Dual ADC devices up to 18 single-ended external inputs (one dedicated analog and eight dual function input pins in each ADC block) Temperature sensing mode monitors external temperature data input with a sampling rate of up to 50 kilosamples per second. In dual ADC devices, only the first ADC block supports this mode. MAX 10 ADC Architecture and Features on page 2-1 MAX 10 ADC Design Considerations on page 3-1 MAX 10 ADC Implementation Guides on page 4-1 Altera Modular ADC IP Core References on page 5-1 ADC Block Counts in MAX 10 Devices The ADC block is available in single and dual supply MAX 10 devices All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Innovation Drive, San Jose, CA 95134

5 1-2 ADC Channel Counts in MAX 10 Devices Table 1-1: Number of ADC Blocks in MAX 10 Devices and Packages UG-M10ADC For more information about the device part numbers that feature ADC blocks, refer to the device overview. Package Power Supply Device 10M04 10M08 10M16 10M25 10M40 10M50 M153 Single 1 1 U169 Single U324 Dual F256 Dual E144 Single F484 Dual F672 Dual 2 2 MAX 10 FPGA Device Overview ADC Channel Counts in MAX 10 Devices Different MAX 10 devices support different number of ADC channels. Table 1-2: ADC Channel Counts in MAX 10 Devices Devices with two ADC blocks have two dedicated analog inputs and each ADC block has 8 dual function pins. You can use the dual function pins in an ADC block as general purpose I/O (GPIO) pins if you do not use the ADC. For more information about the device part numbers that feature ADC blocks, refer to the device overview. Package Pin Type ADC Channel Counts Per Device 10M04 10M08 10M16 10M25 10M40 10M50 M153 U169 U324 F256 Dedicated 1 1 Dual function 8 8 Dedicated Dual function Dedicated Dual function Dedicated Dual function MAX 10 ADC Overview

6 UG-M10ADC MAX 10 ADC Vertical Migration Support 1-3 Package E144 F484 F672 Pin Type ADC Channel Counts Per Device 10M04 10M08 10M16 10M25 10M40 10M50 Dedicated Dual function Dedicated Dual function Dedicated 2 2 Dual function MAX 10 FPGA Device Overview MAX 10 ADC Vertical Migration Support on page 1-3 MAX 10 ADC Vertical Migration Support Figure 1-1: ADC Vertical Migration Across MAX 10 Devices Preliminary The arrows indicate the ADC migration paths. The devices included in each vertical migration path are shaded. Device Package M153 U169 U324 F256 E144 F484 F672 10M04 10M08 10M16 10M25 10M40 10M50 Dual ADC Device: Each ADC (ADC1 and ADC2) supports 1 dedicated analog input pin and 8 dual function pins. Single ADC Device: Single ADC that supports 1 dedicated analog input pin and 16 dual function pins. Single ADC Device: Single ADC that supports 1 dedicated analog input pin and 8 dual function pins. MAX 10 ADC Overview

7 1-4 MAX 10 Single or Dual Supply Devices Table 1-3: Pin Migration Conditions for ADC Migration UG-M10ADC Source Target Migratable Pins Single ADC device Dual ADC device Single ADC device Dual ADC device You can migrate all ADC input pins Single ADC device Dual ADC device One dedicated analog input pin. Dual ADC device Single ADC device Eight dual function pins from the ADC1 block of the source device to the ADC1 block of the target device. ADC Channel Counts in MAX 10 Devices on page 1-2 MAX 10 Single or Dual Supply Devices MAX 10 devices are available in single or dual supply packages. For devices with single power supply: Use on chip regulator to power up the digital supply. Use V CCA to power up the ADC analog. For dual power supply devices, you must provide external power supplies of 1.2 V and 2.5 V to power up the ADC. To choose the correct device, refer to the MAX 10 device overview. For more information about the ADC parameter, refer to the device datasheet. MAX 10 Device Datasheet MAX 10 FPGA Device Overview MAX 10 ADC Conversion The ADC in dual supply MAX 10 devices can measure from 0 V to 2.5 V. In single supply MAX 10 devices, it can measure up to 3.0 V or 3.3 V, depending on your power supply voltage. In prescaler mode, the analog input can measure up to 3.0 V in dual supply MAX 10 devices and up to 3.6 V in single supply MAX 10 devices. The analog input scale has full scale code from 000h to FFFh. However, the measurement can only display up to full scale 1 LSB. For the 12 bits corresponding value calculation, use unipolar straight binary coding scheme. MAX 10 ADC Overview

8 UG-M10ADC MAX 10 ADC Conversion 1-5 Figure 1-2: ADC Measurement Display for 2.5 V Output Code FFF Full Scale Transition 12 bit Output Code (Hex) FFE FFD Full scale input = 2.5 V Resolution = 2 12 = LSB = 2.5V / 4096 = µ V µ µ Input Voltage (V) The MAX 10 ADC is a 1 MHz successive approximation register (SAR) ADC. If you set up the PLL and Altera Modular ADC IP core correctly, the ADC operates at 1 MHz during normal sampling and 50 khz during temperature sensing. Note: The analog value represented by the all-ones code is not full scale but full scale 1 LSB. This is a common convention in data conversion notation and applies to ADCs. Creating MAX 10 ADC Design on page 4-2 Altera Modular ADC Parameters Settings on page 5-1 Altera Modular Dual ADC Parameters Settings on page 5-6 MAX 10 ADC Overview

9 MAX 10 ADC Architecture and Features 2 UG-M10ADC Subscribe In MAX 10 devices, the ADC is a 12 bits SAR ADC that provides the following features: Sampling rate of up to 1 MSPS Up to 18 channels for analog measurement: 16 dual function channels and two dedicated analog input channels in dual ADC devices Single-ended measurement capability Simultaneous measurement capability at the dedicated analog input pins for dual ADC devices Soft logic sequencer On-chip temperature sensor with sampling rate of 50 kilosamples per second Internal or external voltage references usage. The source of the internal voltage reference is the ADC analog supply; the ADC conversion result is ratiometric. MAX 10 ADC Overview on page 1-1 MAX 10 ADC Hard IP Block The MAX 10 ADC is a successive approximation register (SAR) ADC that converts one analog sample in one clock cycle. Each ADC block supports one dedicated analog input pin and up to 16 channels of dual function pins. You can use the built-in temperature sensing diode (TSD) to perform on-chip temperature measurement All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Innovation Drive, San Jose, CA 95134

10 2-2 ADC Block Locations Figure 2-1: ADC Hard IP Block in MAX 10 Devices UG-M10ADC Note: In dual ADC devices, the temperature sensor is available only in ADC1. Dedicated Analog Input ADC Hard IP Block PLL Clock In Sequencer [4:0] ADC Analog Input (Dual Function) [16:1] Mux Sampling and Hold 12 bit 1 Mbps ADC DOUT [11:0] Control/Status ADC V REF Temperature Sensor Altera Modular ADC IP Core Internal V REF ADC Block Locations The ADC blocks are located at the top left corner of the MAX 10 device periphery. Figure 2-2: ADC Block Location in MAX and 08 Devices ADC A 6 1B 2 5 I/O Bank 3 4 ADC Block MAX 10 ADC Architecture and Features

11 UG-M10ADC ADC Block Locations 2-3 Figure 2-3: ADC Block Location in MAX Devices ADC A 6 1B 2 5 OCT I/O Bank 3 4 ADC Block MAX 10 ADC Architecture and Features

12 2-4 Single or Dual ADC Devices Figure 2-4: ADC Block Location in MAX 10 25, 40, and 50 Devices UG-M10ADC Package E144 of these devices have only one ADC block. ADC1 ADC A 6 1B 2 5 OCT I/O Bank 3 4 ADC Block Single or Dual ADC Devices MAX 10 devices are available with single or dual ADC blocks. For devices with one ADC block, you can use up to 17 ADC channels: These channels include one dedicated analog input and up to 16 dual function pins. You can use the dual function pins as GPIO pins when you do not use the ADC. Note: MAX 10 devices in the E144 package have only 8 dual function ADC pins. For devices with two ADC blocks, you can use up to 18 ADC channels: For dual ADC devices, each ADC block can support one dedicated analog input pin and up to 8 dual function pins. If you use both ADC blocks in dual ADC devices, you can use up to two dedicated analog input pins and 16 dual function pins. For simultaneous measurement, you can use only dedicated analog input pins in both ADC blocks because the package routing of both dedicated analog pins are matched. For dual function pins, the routing latency between two ADC blocks may cause data mismatch in simultaneous measurement. For simultaneous measurement, use the Altera Modular Dual ADC IP core. To choose the correct device, refer to the MAX 10 device overview. MAX 10 FPGA Device Overview MAX 10 ADC Architecture and Features

13 UG-M10ADC ADC Analog Input Pins 2-5 ADC Channel Counts in MAX 10 Devices on page 1-2 ADC Analog Input Pins The analog input pins support single-ended and unipolar measurements. The ADC block in MAX 10 devices contains two types of ADC analog input pins: Dedicated ADC analog input pin pins with dedicated routing that ensures both dedicated analog input pins in a dual ADC device has the same trace length. Dual function ADC analog input pin pins that share the pad with GPIO pins. If you use bank 1A for ADC, you cannot use the bank for GPIO. Each analog input pin in the ADC block is protected by electrostatic discharge (ESD) cell. For more information, refer to the device datasheet. MAX 10 Device Datasheet ADC Prescaler The ADC block in MAX 10 devices contains a prescaler function. The prescaler function divides the analog input voltage by half. Using this function, you can measure analog input greater than 2.5 V. In prescaler mode, the analog input can handle up to 3 V input for the dual supply MAX 10 devices and 3.6 V for the single supply MAX 10 devices. Figure 2-5: ADC Prescaler Block Diagram ADC Analog Input 3.6 kω 3.6 kω Mux REFGND The prescaler feature is available on these channels in each ADC block: Single ADC device channels 8 and 16 (if available) Dual ADC device: Using Altera Modular ADC IP core channel 8 of first or second ADC Using Altera Modular Dual ADC IP core channel 8 of ADC1 and channel 17 of ADC2 ADC Clock Sources The ADC block uses the device PLL as the clock source. The ADC clock path is a dedicated clock path. You cannot change this clock path. MAX 10 ADC Architecture and Features

14 2-6 ADC Voltage Reference Depending on the device package, the MAX 10 devices support one or two PLLs PLL1 only, or PLL1 and PLL3. For devices that support two PLLs, you can select which PLL to connect to the ADC. You can configure the ADC blocks with one of the following schemes: Both ADC blocks share the same clock source for synchronization. Both ADC blocks use different PLLs for redundancy. If each ADC block in your design uses its own PLL, the Quartus II Fitter automatically selects the clock source scheme based on the PLL clock input source: If each PLL that clocks its respective ADC block uses different PLL input clock source, the Quartus II Fitter follows your design (two PLLs). If both PLLs that clock their respective ADC block uses the same PLL input clock source, the Quartus II Fitter merges both PLLs as one. In dual ADC mode, both ADC instance must share the same ADC clock setting. ADC Voltage Reference Each ADC block in MAX 10 devices can independently use an internal or external voltage reference. In dual ADC devices, you can assign an internal voltage reference to one ADC block and an external voltage reference to the other ADC block. There is only one external VREF pin in each MAX 10 device. Therefore, if you want to assign external voltage reference for both ADC blocks in dual ADC devices, share the same external voltage reference for both ADC blocks. Altera recommends that you use external voltage reference for the ADC blocks. If the ADC block uses an internal voltage reference, the ADC block is tied to its analog voltage and the conversion result is ratiometric. ADC Temperature Sensing Diode The ADC block in MAX 10 devices has built-in TSD. You can use the built-in TSD to monitor the internal temperature of the MAX 10 device. While using the temperature sensing mode, the ADC sampling rate is 50 kilosamples per second during temperature measurement. After the temperature measurement completes, if the next conversion in the sequence is normal sampling mode, the Altera Modular ADC IP core automatically switches the ADC back to normal sampling mode. The cumulative sampling rate in normal sampling mode is 1 MSPS. When the ADC switches from normal sensing mode to temperature sensing mode, and vice versa, calibration is run automatically for the changed clock frequency. The calibration incurs at least six clock calibration cycles from the new sampling rate. The ADC TSD measurement uses a 64-samples running average method. For example: The first measured temperature value is the average of samples 1 to 64. The second measured temperature value is the average of samples 2 to 65. The third measured temperature value is the average of samples 3 to 66. The subsequent temperature measurements follow the same method. For dual ADC devices, the temperature sensor is available in ADC1 only. UG-M10ADC MAX 10 ADC Architecture and Features

15 UG-M10ADC Temperature Measurement Code Conversion 2-7 Temperature Measurement Code Conversion Use the temperature measurement code conversion table to convert the values measured by the ADC TSD to actual temperature. Table 2-1: Temperature Code Conversion Table Preliminary Temp (C) Code Temp (C) Code Temp (C) Code Temp (C) Code Temp (C) Code MAX 10 ADC Architecture and Features

16 2-8 ADC Sequencer UG-M10ADC Temp (C) Code Temp (C) Code Temp (C) Code Temp (C) Code Temp (C) Code ADC Sequencer The Altera Modular ADC and Altera Modular Dual ADC IP cores implement the sequencer. Use the Altera Modular ADC or Altera Modular Dual ADC parameter editor to define the ADC channel acquisition sequence and generate the HDL code. The sequencer can support sequences of up to 64 ADC measurement slots. While configuring the Altera Modular ADC or Altera Modular Dual ADC IP core, you can select which channel, including the TSD channel, to sample in each sequencer slot. During runtime, you cannot change the channel sequence but you can configure the conversion mode using the Nios II HAL driver API. You can specify up to 64 slots and assign the channel for each slot. You can repeat the same channel number several times if required. Guidelines: ADC Sequencer in Altera Modular Dual ADC IP Core on page 2-8 Guidelines: ADC Sequencer in Altera Modular Dual ADC IP Core Follow these sequencer guidelines if you use dual ADC blocks with the Altera Modular Dual ADC IP core. The conversion sequence length of both ADC blocks must be the same. You can configure independent patterns for the conversion sequence of each ADC blocks. You can set a sequencer slot in ADC2 to NULL. If you set the slot to NULL, ADC2 will perform a dummy conversion for the slot with output of "0". The NULL option is available only for ADC2. The temperature sensor is available only in ADC1. If you configure a sequencer slot in ADC1 for temperature sensing, you must set the same sequencer slot number in ADC2 to NULL. ADC Sequencer on page 2-8 MAX 10 ADC Architecture and Features

17 UG-M10ADC ADC Timing 2-9 ADC Timing Figure 2-6: MAX 10 ADC Timing Diagram This figure shows the timing diagram for the command and response interface of the Altera Modular ADC control core. The timing diagram shows the latency of the first valid response data, and the latency between the first acknowledgment of the first command request and the back-to-back response data. clock reset_n command_valid commandd_channel[4:0] command_starofpacket command_endofpacket command_ready response_valid response_channel[4:0] response_data[11:0] response_startofpacket response_endofpacket 0x00 0x10 0x01 0x02 0x00 0x10 0x00 0x01 0x000 0x008 0x000 0x001 3 ADC soft IP clock + 2 μs 1 μs 3 ADC soft IP clock + 3 μs The timing diagram shows an example where: The conversion sequence is channel 16 channel 1 channel 2 The response data for channel 16 is 8 The response data for channel 1 is 1 Altera Modular ADC and Altera Modular Dual ADC IP Cores You can use the Altera Modular ADC and Altera Modular Dual ADC IP cores to generate soft IP controllers for the ADC hard IP blocks in MAX 10 devices. There are two ADC IP cores: Altera Modular ADC IP core each instance can control one ADC hard IP block. In a dual ADC device, you can instantiate one Altera Modular ADC IP core instance for each ADC block. However, both instances will be asynchronous to each other. Altera Modular Dual ADC IP core you can control both ADC hard IP block with a single IP instance. For the analog input pins (ANAIN1 and ANAIN2) in both ADC hard IP blocks, the measurement is synchronous. For the dual function input pins, there are some measurement timing differences caused by the routing latency. MAX 10 ADC Architecture and Features

18 2-10 Altera Modular ADC IP Core Configuration Variants You can perform the following functions with the Altera Modular ADC or Altera Modular Dual ADC IP core parameter editor: Configure the ADC clock and reference voltage. Select which analog input channels that the ADC block samples. Configure the threshold value to trigger a threshold violation notification. Set up a conversion sequence to determine which channel requires more frequent attention. Altera Modular ADC IP Core References on page 5-1 Altera Modular ADC IP Core Configuration Variants The Altera Modular ADC IP core provides four configuration variants that target different ADC use cases. These configuration variants support usages from basic system monitoring to high performance ADC data streaming. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage on page 2-10 In this configuration variant, you can use the standard sequencer micro core with internal on-chip RAM for storing ADC samples. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection on page 2-11 In this configuration variant, you can use the standard sequencer micro core with internal on-chip RAM for storing ADC samples with the additional capability of detecting threshold violation. Configuration 3: Standard Sequencer with External Sample Storage on page 2-13 In this configuration variant, you can use the standard sequencer micro core and store the ADC samples in external storage. Configuration 4: ADC Control Core Only on page 2-13 In this configuration variant, the Altera Modular ADC generates only the ADC control core. Altera Modular ADC IP Core References on page 5-1 UG-M10ADC Configuration 1: Standard Sequencer with Avalon-MM Sample Storage In this configuration variant, you can use the standard sequencer micro core with internal on-chip RAM for storing ADC samples. This configuration is useful for basic system monitoring application. In a system monitoring application, the ADC captures a block of samples data and stores them in the onchip RAM. The host processor retrieves the data before triggering another block of ADC data sample request. The speed of the host processor in servicing the interrupt determines the interval between each block sample request. MAX 10 ADC Architecture and Features

19 UG-M10ADC Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Figure 2-7: Standard Sequencer with Avalon-MM Sample Storage (Altera Modular ADC IP Core) peripheral clock peripheral reset CSR altera_adc altera_adc_sequencer S command altera_adc_control adc_pll_clock (clock from dedicated PLL) adc_pll_locked (locked signal from dedicated PLL) CSR IRQ altera_adc_sample_store S response Figure 2-8: Standard Sequencer with Avalon-MM Sample Storage (Altera Modular Dual ADC IP Core) altera_dual_adc peripheral clock peripheral reset altera_adc_sequencer command altera_adc_control response sync handshake adc_pll_clock (clock from dedicated PLL) adc_pll_locked (locked signal from dedicated PLL) CSR S altera_dual_adc_synchronizer altera_adc_response_merge altera_adc_sample_store response S CSR IRQ sync handshake command altera_adc_control response Customizing and Generating Altera Modular ADC IP Core on page 4-2 Completing ADC Design on page 4-7 Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection In this configuration variant, you can use the standard sequencer micro core with internal on-chip RAM for storing ADC samples with the additional capability of detecting threshold violation. This configuration is useful for system monitoring application where you want to know whether the ADC samples value fall outside the maximum or minimum threshold value. When the threshold value is violated, the Altera Modular ADC or Altera Modular Dual ADC IP core notifies the discrete logic component. The discrete component then triggers system recovery action. For example, the system can increase the fan speed in a temperature control system. MAX 10 ADC Architecture and Features

20 2-12 Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and... UG-M10ADC Figure 2-9: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection (Altera Modular ADC IP Core) peripheral clock peripheral reset CSR altera_adc altera_adc_sequencer S command altera_adc_control adc_pll_clock (clock from dedicated PLL) adc_pll_locked (locked signal from dedicated PLL) CSR IRQ altera_adc_sample_store S response Avalon ST Splitter Core response threshold altera_adc_threshold_detect response In dual ADC mode, you can configure the threshold detection of each ADC instance independently of each other. This capability is available because each ADC instance measures different analog metrics. Figure 2-10: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection (Altera Modular Dual ADC IP Core) threshold altera_dual_adc altera_adc_threshold_detect peripheral clock peripheral reset CSR altera_adc_sequencer S altera_adc_control command response sync handshake altera_dual_adc_synchronizer sync handshake command response altera_adc_control altera_adc_threshold_detect response response Avalon ST Splitter altera_adc_response_merge Core Avalon ST Splitter Core response response response altera_adc_sample_store S adc_pll_clock (clock from dedicated PLL) adc_pll_locked (locked signal from dedicated PLL) CSR IRQ threshold Customizing and Generating Altera Modular ADC IP Core on page 4-2 Completing ADC Design on page 4-7 MAX 10 ADC Architecture and Features

21 UG-M10ADC Configuration 3: Standard Sequencer with External Sample Storage 2-13 Configuration 3: Standard Sequencer with External Sample Storage In this configuration variant, you can use the standard sequencer micro core and store the ADC samples in external storage. You need to design your own logic to interface with the external storage. Figure 2-11: Standard Sequencer with External Sample Storage (Altera Modular ADC IP Core) peripheral clock peripheral reset CSR altera_adc altera_adc_sequencer S command altera_adc_control adc_pll_clock (clock from dedicated PLL) adc_pll_locked (locked signal from dedicated PLL) response Figure 2-12: Standard Sequencer with External Sample Storage (Altera Modular Dual ADC IP Core) altera_dual_adc peripheral clock peripheral reset CSR altera_adc_sequencer S altera_adc_control command sync handshake altera_dual_adc_synchronizer response adc_pll_clock (clock from dedicated PLL) adc_pll_locked (locked signal from dedicated PLL) sync handshake command response altera_adc_control Customizing and Generating Altera Modular ADC IP Core on page 4-2 Completing ADC Design on page 4-7 Configuration 4: ADC Control Core Only In this configuration variant, the Altera Modular ADC generates only the ADC control core. You have full flexibility to design your own application-specific sequencer and use your own way to manage the ADC samples. MAX 10 ADC Architecture and Features

22 2-14 Altera Modular ADC and Altera Modular Dual ADC IP Cores Architecture Figure 2-13: ADC Control Core Only (Altera Modular ADC IP Core) UG-M10ADC peripheral clock peripheral reset command altera_adc altera_adc_control adc_pll_clock (clock from dedicated PLL) adc_pll_locked (locked signal from dedicated PLL) response Figure 2-14: ADC Control Core Only (Altera Modular Dual ADC IP Core) command peripheral clock peripheral reset altera_dual_adc altera_adc_control sync handshake altera_dual_adc_synchronizer sync handshake response adc_pll_clock (clock from dedicated PLL) adc_pll_locked (locked signal from dedicated PLL) command response altera_adc_control Customizing and Generating Altera Modular ADC IP Core on page 4-2 Completing ADC Design on page 4-7 Altera Modular ADC and Altera Modular Dual ADC IP Cores Architecture The Altera Modular ADC IP core consists of six micro cores. MAX 10 ADC Architecture and Features

23 UG-M10ADC Altera Modular ADC and Altera Modular Dual ADC IP Cores Architecture 2-15 Table 2-2: Altera Modular ADC Micro Cores Micro Core ADC control Sequencer Sample storage Response merge Dual ADC synchronizer core Description This core interacts with the ADC hard IP block. The ADC control core uses Avalon ST interface to receive commands from upstream cores, decodes, and drives the ADC hard IP block accordingly. This core contains command register and static conversion sequence data. The sequencer core issues commands for downstream cores to execute. You can use the command register to configure the intended conversion mode. You can configure the length and content of the conversion sequence data only when generating the IP core. You can access the register of the sequencer core through the Avalon-MM slave interface. The command information to the downstream core goes through the Avalon ST interface. This core stores the ADC samples that are received through the Avalon ST interface. The samples are stored in the on-chip RAM. You can retrieve the samples through the Avalon-MM slave interface. With this core, you have the option to generate interrupt when the ADC receives a block of ADC samples (one full round of conversion sequence). This core merges simultaneous responses from two ADC control cores into a single response packet to send to the sample storage core. This core is available only if you use the Altera Modular Dual ADC IP core in the following configurations: Standard Sequencer with Avalon-MM Sample Storage Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection This core performs synchronization handshakes between two ADC control cores. This core is available only if you use the Altera Modular Dual ADC IP core. MAX 10 ADC Architecture and Features

24 2-16 ADC Control Core UG-M10ADC Micro Core Description Threshold detection This core supports fault detection. The threshold detection core receives ADC samples through the Avalon ST interface and checks whether the samples value exceeds the maximum or falls below the minimum threshold value. The threshold detection core conveys threshold value violation information through the Avalon ST interface. You can configure which channel to enable for maximum and minimum threshold detection and the threshold values only during IP core generation. ADC Control Core The ADC control core drives the ADC hard IP according to the command it receives. The control core also maps the channels from the Altera Modular ADC IP core to the channels in the ADC hard IP block. The ADC control core of the Altera Modular ADC IP core implements only the functions that are related to ADC hard IP block operations. For example: Power up Power down Analog to digital conversion on analog pins Analog to digital conversion on on-chip temperature sensor The ADC control core has two clock domains: One clock domain for clocking the ADC control core soft logic Another clock domain for the ADC hard IP block The ADC control core does not have run-time configurable options. Figure 2-15: ADC Control Core High-Level Block Diagram peripheral clock peripheral reset command altera_adc_control ADC Controller FSM ADC Hard IP Wrapper adc_pll_clock (clock from dedicated PLL) adc_pll_locked (locked signal from dedicated PLL) response sync handshake (dual ADC only) MAX 10 ADC Architecture and Features

25 UG-M10ADC Sequencer Core 2-17 Table 2-3: ADC Control Core Backpressure Behavior Interface Command Response Backpressure Behavior The ADC control core asserts ready when it is ready to perform a sample conversion. The ADC control core only accepts one command at a time. The control core releases ready when it completes processing current command and prepares to perform the next command. Once the ADC control core asserts "cmd_ready=1" to acknowledge the current command, the Sequencer core provides the next valid request within two clock cycles. If the next valid request comes after two clock cycles, the ADC control core perform non-continuous sampling. The ADC control core does not support backpressure in the response interface. The fastest back-to-back assertion of valid request is 1 µs. Sequencer Core The sequencer core controls the type of conversion sequence performed by the ADC hard IP. You can configure the conversion mode during run time using the sequencer core registers. During Altera Modular ADC or Altera Modular Dual ADC IP core configuration, the sequencer core provides up to 64 configurable slots. You can define the sequence that the ADC channels are sampled by selecting the ADC channel for each sequencer slot. The sequencer core has a single clock domain. Figure 2-16: Sequencer Core High-Level Block Diagram peripheral clock peripheral reset CSR altera_adc_sequencer S Command Register Static Conversion Sequence Data Array (up to 64 slots) Sequencer Controller Sequencer Controller command command (dual ADC only) Table 2-4: Sequencer Core Conversion Modes Conversion Mode Single cycle ADC conversion Description In this mode, when the run bit is set, ADC conversion starts from the channel that you specify in the first slot. The conversion continues onwards with the channel that you specify in each sequencer slot. Once the conversion finishes with the last sequencer slot, the conversion cycle stops and the ADC hard IP block clears the run bit. MAX 10 ADC Architecture and Features

26 2-18 Sample Storage Core UG-M10ADC Conversion Mode Continuous ADC conversion Description In this mode, when the run bit is set, ADC conversion starts from the channel that you specify in the first slot. The conversion continues onwards with the channel that you specify in each sequencer slot. Once the conversion finishes with the last sequencer slot, the conversion begins again from the first slot of the sequence. To stop the continuous conversion, clear the run bit. The sequencer core continues the conversion sequence until it reaches the last slot and then stops the conversion cycle. Altera Modular ADC Parameters Settings on page 5-1 Lists the parameters available during Altera Modular ADC IP core configuration. Altera Modular Dual ADC Parameters Settings on page 5-6 Lists the parameters available during Altera Modular Dual ADC IP core configuration. Sequencer Core Registers on page 5-16 Lists the registers for run-time control of the sequencer core. Sample Storage Core The sample storage core stores the ADC sampling data in the on-chip RAM. The sample storage core stores the ADC samples data based on conversion sequence slots instead of ADC channels. For example, if you sample a sequence of CH1, CH2, CH1, CH3, CH1, and then CH4, the ADC sample storage core stores the channel sample data in the same RAM entry sequence. This means that CH1 sample data will be in the first, third, and fifth RAM entries; one for each sequence slot. The sample storage core asserts IRQ when it completes receipt of a sample block. You can disable the IRQ assertion during run time using the interrupt enable register (IER) of the sample storage core. If you disable IRQ assertion, you must create polling methods in your design to determine the complete receipt of a sample block. The sample storage core has a single clock domain. Figure 2-17: Sample Storage Core High-Level Block Diagram peripheral clock peripheral reset CSR IRQ altera_adc_sample_store S 64 RAM Entries for ADC Sample Storage IER Register ISR Register RAM Control Interrupt Control response MAX 10 ADC Architecture and Features

27 UG-M10ADC Response Merge Core 2-19 Sample Storage Core Registers on page 5-16 Response Merge Core The response merge core merges simultaneous responses from two ADC control cores in the Altera Modular Dual ADC IP core. The Altera Modular Dual ADC IP core uses the response merge core if you use the following configurations: Standard Sequencer with Avalon-MM Sample Storage Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection Figure 2-18: Response Merge Core High-Level Block Diagram peripheral clock peripheral reset response response altera_adc_response_merge Response merge logic response Dual ADC Synchronizer Core The dual ADC synchronizer core performs synchronization handshakes between two ADC control cores in the Altera Modular Dual ADC IP core. The peripheral clock domain is asynchronous to the ADC PLL clock domain in the ADC control core. Control event from the ADC hard IP block can appear at the peripheral clock domain at the same time, or by a difference of one peripheral clock between ADC1 and ADC2 control cores. Both ADC hard IP cores communicate with the dual ADC synchronizer core through the Avalon-ST interface. For example, although a new command valid event from the sequencer arrives at both ADC control cores at the same peripheral clock cycle, the end of conversion signals arrive at one peripheral clock cycle difference between ADC1 and ADC2. To avoid the condition where ADC1 begins conversion earlier or later than ADC2, the ADC control core performs synchronization handshake using the dual ADC synchronizer core. An ADC control core asserts a sync_valid signal when it detects an ADC PLL clock domain event. The dual ADC synchronizer core asserts the sync_ready signal after it receives sync_valid signals from both ADC control cores. After the sync_ready signal is asserted, both ADC control cores proceed to their next internal state. MAX 10 ADC Architecture and Features

28 2-20 Threshold Detection Core Figure 2-19: Dual ADC Synchronizer Core High-Level Block Diagram UG-M10ADC peripheral clock peripheral reset sync handshake sync handshake altera_dual_adc_synchronizer Synchronizer logic Threshold Detection Core The threshold detection core compares the sample value that the ADC block receives to the threshold value that you define during Altera Modular ADC IP core configuration. This core does not have runtime configurable options. If the ADC sample value is beyond the maximum or minimum threshold limit, the threshold detection core issues a violation notification through the Avalon-ST interface. The threshold detection core has a single clock domain. Figure 2-20: Threshold Detection Core High-Level Block Diagram peripheral clock peripheral reset threshold altera_adc_threshold_detect Comparator Logic response Altera ADC HAL Driver The Altera ADC HAL driver supports the following features: Read ADC channel data. Enable maximum or minimum threshold and return a user callback when the interrupt is triggered. Command the control of the ADC (run, stop, and recalibrate). MAX 10 ADC Architecture and Features

29 MAX 10 ADC Design Considerations 3 UG-M10ADC Subscribe There are several considerations that require your attention to ensure the success of your designs. Unless noted otherwise, these design guidelines apply to all variants of this device family. MAX 10 ADC Overview on page 1-1 Guidelines: ADC Ground Plane Connection For power pins, use the GND pin. For the ADC and V REF pins, use the REFGND pin. MAX 10 FPGA Device Family Pin Connection Guidelines Provides more information about pin connections including pin names and connection guidelines. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) The crosstalk requirement for analog to digital signal is -100 db up to 2 GHz. There must be no parallel routing between power, ground, and I/O traces. If a power plane is not possible, route the power and ground traces as wide as possible. To reduce IR drop and switching noise, keep the impedance as low as possible for the ADC power and ground. The maximum DC resistance for power is 1.5 Ω. The power supplies connected to the ADC should have ferrite beads in series followed by a 10 µf capacitor to the ground. This setup ensures that no external noise goes into the device power supply pins. Decouple each of the device power supply pin with a 0.1 µf capacitor. Place the capacitor as close as possible to the device pin All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Innovation Drive, San Jose, CA 95134

30 3-2 Guidelines: Board Design for Analog Input Figure 3-1: Recommended RC Filter for Power Traces UG-M10ADC Power Supply Ferrite Beads 10 µf 0.1 µf VCCADC_2P5 Place this cap close to the pin Power Supply Ferrite Beads GND 10 µf GND 0.1 µf VCCADC_1P2 GND Place this cap close to the pin GND There is no impedance requirement for the REFGND. Altera recommends that you use the lowest impedance with the most minimum DC resistance possible. Typical resistance is less than 1 Ω. Altera recommends that you set a REFGND plane that extends as close as possible to the corresponding decoupling capacitor and FPGA: If possible, define a complete REFGND plane in the layout. Otherwise, route the REFGND using a trace that is as wide as possible from the island to the FPGA pins and decoupling capacitor. The REFGND ground is the reference ground plane for the ADC V REF and analog input. Connect REFGND ground to the system digital ground through ferrite beads. You can also evaluate the ferrite bead option by comparing the impedance with the frequency specifications. Guidelines: Board Design for Analog Input The crosstalk requirement for analog to digital signal is -100 db up to 2 GHz. There must be no parallel routing between analog input signals and I/O traces, and between analog input signals and FPGA I/O signal traces. The total RC constant, including package, trace, and parasitic driver must be less than 42.4 ns. This consideration is to ensure that the input signal is fully settled during the sampling phase. If you reduce the total sampling rate, you can calculate the required settling time as 0.45 F S > RC constant. To gain more total RC margin, Altera recommends that you set the driver source impedance as low as possible: For prescaler-disabled channel less than 1 kω For prescaler-enabled channel less than 11 Ω MAX 10 ADC Design Considerations

31 UG-M10ADC Guidelines: Board Design for Analog Input 3-3 Trace Routing If possible, route the switching I/O traces on different layer. There is no specific requirement for input signal trace impedance. However, the DC resistance for the input trace must be as low as possible. Route the analog input signal traces as adjacent as possible to REFGND if there is no REFGND plane. Use REFGND as ground reference for the ADC input signal. For prescaler-enabled input signal, set the ground reference to REFGND. Performance degrades if the ground reference of prescaler-enabled input signal is set to common ground (GND). Input Low Pass Filter Selection A low pass RC filter can reduce the trace spacing between analog input signal and digital I/O signal to meet -100 db crosstalk requirement. Altera recommends that you place active low pass filter to help in meeting the required settling time. Place the low pass filter as close as possible to the analog input signals. The cut off frequency depends on the analog input frequency. Altera recommends that the F -3dB is five times the input frequency. You can download the ADC input SPICE model for ADC front end board design simulation from the Altera website. Table 3-1: RC Constant and Filter Value This table is an example of the method to quantify the RC constant and identify the RC filter value. Total RC Constant = (R DRIVER + R BOARD + R PACKAGE + R FILTER ) (C DRIVER + C BOARD + C PACKAGE + C FILTER + C PIN ) R (Ω) Driver Board Package Pin C (pf) R (Ω) C (pf) R (Ω) C (pf) Capacitance (pf) RC Filter R (Ω) C (pf) F -3dB (MHz) Total RC Constant (ns) Settling Time (ns) Figure 3-2: Passive Low Pass Filter Example Driver RC Board RC R FILTER ADC Analog Input Place this cap close to the pin C FILTER Altera Device REFGND MAX 10 ADC Design Considerations

32 3-4 Guidelines: Board Design for ADC Reference Voltage Pin Figure 3-3: First Order Active Low Pass Filter Example UG-M10ADC This figure is an example. You can design nth order active low pass filter. Driver RC Board RC R ƒ c = 1 2πRC C + - ADC Analog Input REFGND Altera Device How can I change the sampling rate of the ADC in MAX 10 devices? Provides more information about reducing the total sampling rate. SPICE Models for Altera Devices Provides the MAX 10 ADC spice model download. Guidelines: Board Design for ADC Reference Voltage Pin The crosstalk requirement for analog to digital signal is -100 db up to 2 GHz. There is no parallel routing between analog input signals and I/O traces. Route the V REF traces as adjacent as possible to REFGND. If a REFGND plane is not possible, route the analog input signal as adjacent as possible to REFGND. There is one ADC reference voltage pin in each MAX 10 device. This pin uses REFGND as ground reference. Keep the trace resistance less than 0.8 Ω. Figure 3-4: RC Filter Design Example for Reference Voltage Pin Place the RC filter as close as possible to the analog input pin. V REF 1.0 Ω 10.0 µf 1 µf Altera device REFGND REFGND MAX 10 ADC Design Considerations