4. Embedded Multipliers in the Cyclone III Device Family
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1 ecember 2011 CIII Embedded Multipliers in the Cyclone III evice Family CIII The Cyclone III device family (Cyclone III and Cyclone III LS devices) includes a combination of on-chip resources and external interfaces that help to increase performance, reduce system cost, and lower the power consumption of digital signal processing (SP) systems. The Cyclone III device family, either alone or as SP device co-processors, are used to improve price-to-performance ratios of SP systems. Particular focus is placed on optimizing Cyclone III and Cyclone III LS devices for applications that benefit from an abundance of parallel processing resources, which include video and image processing, intermediate frequency (IF) modems used in wireless communications systems, and multi-channel communications and video systems. This chapter contains the following sections: Embedded Multiplier Block Overview on page 4 2 Architecture on page 4 3 Operational Modes on page Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARCOPY, MAX, MEGACORE, NIOS, UARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Cyclone III evice Handbook ecember 2011 Subscribe
2 4 2 Chapter 4: Embedded Multipliers in the Cyclone III evice Family Embedded Multiplier Block Overview Embedded Multiplier Block Overview Figure 4 1 shows one of the embedded multiplier columns with the surrounding logic array blocks (LABs). The embedded multiplier is configured as either one multiplier or two 9 9 multipliers. For multiplications greater than 18 18, the uartus II software cascades multiple embedded multiplier blocks together. There are no restrictions on the data width of the multiplier, but the greater the data width, the slower the multiplication process. Figure 4 1. Embedded Multipliers Arranged in Columns with Adjacent LABs Embedded Multiplier Column 1 LAB Row Embedded Multiplier Table 4 1 lists the number of embedded multipliers and the multiplier modes that can be implemented in the Cyclone III device family. Table 4 1. Number of Embedded Multipliers in the Cyclone III evice Family evice Family evice Embedded Multipliers 9 9 Multipliers (1) Multipliers (1) Cyclone III Cyclone III LS EP3C EP3C EP3C EP3C EP3C EP3C EP3C EP3C EP3CLS EP3CLS EP3CLS EP3CLS Note to Table 4 1: (1) These columns show the number of 9 9 or multipliers for each device. The total number of multipliers for each device is not the sum of all the multipliers. Cyclone III evice Handbook ecember 2011 Altera Corporation
3 Chapter 4: Embedded Multipliers in the Cyclone III evice Family 4 3 Architecture In addition to the embedded multipliers in the Cyclone III device family, you can implement soft multipliers by using the M9K memory blocks as look-up tables (LUTs). The LUTs contain partial results from the multiplication of input data with coefficients that implement variable depth and width high-performance soft multipliers for low-cost, high-volume SP applications. The availability of soft multipliers increases the number of available multipliers in the device. Table 4 2 lists the total number of multipliers available in the Cyclone III device family using embedded multipliers and soft multipliers. Table 4 2. Number of Multipliers in the Cyclone III evice Family evice Family evice Embedded Multipliers Cyclone III Cyclone III LS Soft Multipliers (16 16) (1) Total Multipliers (2) EP3C EP3C EP3C EP3C EP3C EP3C EP3C EP3C EP3CLS EP3CLS EP3CLS EP3CLS Notes to Table 4 2: (1) Soft multipliers are implemented in sum of multiplication mode. M9K memory blocks are configured with 18-bit data widths to support 16-bit coefficients. The sum of the coefficients requires 18-bits of resolution to account for overflow. (2) The total number of multipliers may vary, depending on the multiplier mode you use. f f For more information about M9K memory blocks of the Cyclone III device family, refer to the Memory Blocks in the Cyclone III evice Family chapter. For more information about soft multipliers, refer to the Implementing Multipliers in FPGA evices application note. Architecture Each embedded multiplier consists of the following elements: Multiplier stage Input and output registers Input and output interfaces ecember 2011 Altera Corporation Cyclone III evice Handbook
4 4 4 Chapter 4: Embedded Multipliers in the Cyclone III evice Family Architecture Figure 4 2 shows the multiplier block architecture. Figure 4 2. Multiplier Block Architecture signa signb aclr clock ena ata A ata Out ata B Input Register Output Register Embedded Multiplier Block Input Registers You can send each multiplier input signal into an input register or directly into the multiplier in 9- or 18-bit sections, depending on the operational mode of the multiplier. Each multiplier input signal can be sent through a register independently of other input signals. For example, you can send the multiplier ata A signal through a register and send the ata B signal directly to the multiplier. The following control signals are available to each input register in the embedded multiplier: clock clock enable Multiplier Stage asynchronous clear All input and output registers in a single embedded multiplier are fed by the same clock, clock enable, and asynchronous clear signals. The multiplier stage of an embedded multiplier block supports 9 9 or multipliers as well as other multipliers in between these configurations. epending on the data width or operational mode of the multiplier, a single embedded multiplier can perform one or two multiplications in parallel. For multiplier information, refer to Operational Modes on page 4 5. Each multiplier operand is a unique signed or unsigned number. Two signals, signa and signb, control an input of a multiplier and determine if the value is signed or unsigned. If the signa signal is high, the ata A operand is a signed number. If the signa signal is low, the ata A operand is an unsigned number. Cyclone III evice Handbook ecember 2011 Altera Corporation
5 Chapter 4: Embedded Multipliers in the Cyclone III evice Family 4 5 Operational Modes Table 4 3 lists the sign of the multiplication results for the various operand sign representations. The results of the multiplication are signed if any one of the operands is a signed value. Each embedded multiplier block has only one signa and one signb signal to control the sign representation of the input data to the block. If the embedded multiplier block has two 9 9 multipliers, the ata A input of both multipliers share the same signa signal, and the ata B input of both multipliers share the same signb signal. You can dynamically change the signa and signb signals to modify the sign representation of the input operands at run time. You can send the signa and signb signals through a dedicated input register. The multiplier offers full precision, regardless of the sign representation. 1 When the signa and signb signals are unused, the uartus II software sets the multiplier to perform unsigned multiplication by default. Output Registers You can register the embedded multiplier output using output registers in either 18- or 36-bit sections, depending on the operational mode of the multiplier. The following control signals are available for each output register in the embedded multiplier: clock Operational Modes Table 4 3. Multiplier Sign Representation clock enable ata A asynchronous clear All input and output registers in a single embedded multiplier are fed by the same clock, clock enable, and asynchronous clear signals. You can use an embedded multiplier block in one of two operational modes, depending on the application needs: One 18-bit 18-bit multiplier Up to two 9-bit 9-bit independent multipliers ata B signa Value Logic Level signb Value Logic Level Result Unsigned Low Unsigned Low Unsigned Unsigned Low Signed High Signed Signed High Unsigned Low Signed Signed High Signed High Signed ecember 2011 Altera Corporation Cyclone III evice Handbook
6 4 6 Chapter 4: Embedded Multipliers in the Cyclone III evice Family Operational Modes 1 You can also use embedded multipliers of the Cyclone III device family to implement multiplier adder and multiplier accumulator functions, in which the multiplier portion of the function is implemented using embedded multipliers, and the adder or accumulator function is implemented in logic elements (LEs). 18-Bit Multipliers Figure Bit Multiplier Mode You can configure each embedded multiplier to support a single multiplier for input widths of 10 to 18 bits. Figure 4 3 shows the embedded multiplier configured to support an 18-bit multiplier. signa signb aclr clock ena ata A [17..0] ata Out [35..0] ata B [17..0] Multiplier Embedded Multiplier 9-Bit Multipliers All 18-bit multiplier inputs and results are independently sent through registers. The multiplier inputs can accept signed integers, unsigned integers, or a combination of both. Also, you can dynamically change the signa and signb signals and send these signals through dedicated input registers. You can configure each embedded multiplier to support two 9 9 independent multipliers for input widths of up to 9 bits. Cyclone III evice Handbook ecember 2011 Altera Corporation
7 Chapter 4: Embedded Multipliers in the Cyclone III evice Family 4 7 Operational Modes Figure Bit Multiplier Mode Figure 4 4 shows the embedded multiplier configured to support two 9-bit multipliers. signa signb aclr clock ena ata A 0 [8..0] ata Out 0 [17..0] ata B 0 [8..0] 9 9 Multiplier ata A 1 [8..0] ata Out 1 [17..0] ata B 1 [8..0] 9 9 Multiplier Embedded Multiplier All 9-bit multiplier inputs and results are independently sent through registers. The multiplier inputs can accept signed integers, unsigned integers, or a combination of both. Two 9 9 multipliers in the same embedded multiplier block share the same signa and signb signal. Therefore, all the ata A inputs feeding the same embedded multiplier must have the same sign representation. Similarly, all the ata B inputs feeding the same embedded multiplier must have the same sign representation. ecember 2011 Altera Corporation Cyclone III evice Handbook
8 4 8 Chapter 4: Embedded Multipliers in the Cyclone III evice Family ocument Revision History ocument Revision History Table 4 4 lists the revision history for this document. Table 4 4. ocument Revision History ate Version Changes ecember Minor text edits. ecember Minor changes to the text. July Made minor correction to the part number. June Updated to include Cyclone III LS information Updated chapter part number. Updated Introduction on page 4 1. Updated Embedded Multiplier Block Overview on page 4 1. Updated Table 4 1 on page 4 2 and Table 4 2 on page 4 2. Updated Input Registers on page 4 4. October Updated chapter to new template. July Added EP3C120 information. Updated Introduction section. Updated Table 4 1 and Table 4 2. Added chapter TOC and Referenced ocuments section. March Initial release. Cyclone III evice Handbook ecember 2011 Altera Corporation
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