Technical Brief High-Speed Board Design Advisor Thermal Management

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1 Introduction TB Technical Brie High-Speed Board Design Advisor Thermal Management This document contains a step-by-step tutorial and checklist with a best-practice set o step-by-step guidelines to support users to design and review their thermal design with Stratix II GX FPGAs. This document assumes amiliarity with the ollowing sites, tools, and support collateral: Stratix II GX Handbook: Stratix II GX PowerPlay Early Power Estimator (EPE) Spreadsheet and User Guide: Quartus II Handbook: Power Management Resource Center: Package Inormation or Stratix II GX Devices: Altera Device Package Inormation: Stratix Series Device Thermal Resistance: AN 358: Thermal Management or FPGAs: Altera's Stratix II GX FPGA-based development kits deliver quality-proven implementations and comprise board schematics, layout iles, and board-speciic guidelines documents that can be used as a starting point or user designs: Transceiver Signal Integrity Development Kit, Stratix II GX Edition: PCI Express Development Kit, Stratix II GX Edition: Audio Video Development Kit, Stratix II GX Edition: As process technologies shrink and FPGA densities increase, thermal management becomes an important design task. The process involves: Speciying the operating conditions Estimating the total power consumption Determining the necessity o a cooling solution Selecting a cooling solution using a heatsink and thermal interace material and/or airlow Validating the cooling solution Additional topics: Power optimization methods with Quartus II development sotware Temperature-sensing diode or power management Thermal analysis simulations Use the EPE Spreadsheet to speciy the operating conditions, estimate the power and calculate the junction temperature or a given device, package, or design. The spreadsheet will determine the need o a cooling solution November 2007, ver

2 High-Speed Board Design Advisor Altera Corporation based on meeting or exceeding the maximum junction temperature. Once selected, use the EPE to validate the cooling solution. Speciying the Operating Conditions Get the latest version o the PowerPlay EPE Spreadsheet. At the main tab, select the Stratix II GX device and package combination. Select the temperature grade (T JMAX ): industrial or commercial (see Junction Temperature TJ and TJMAX ). Select maximum power characteristics to get worst-case total power. Enter the ambient temperature T A rom the system speciication. Thermal resistance values are provided by the EPE (see Thermal Resistance Values or Stratix II GX FPGAs ). Estimate the Total Power Consumption Enter or import the design details to get the total power consumption (or guidance, see Power Analysis Beore Starting the FPGA Design ). Determine the Necessity o a Cooling Solution With no heatsink and still air, the tool will tell i the maximum junction temperature is exceeded and i a cooling solution is required. The calculated T J will turn red when exceeding 85 C or commercial and 100 C or industrial temperature grade. Select Cooling Solution Heatsink and Thermal Interace Material and/or Airlow Select a cooling solution. AN 358: Thermal Management or FPGAs gives more inormation about evaluations o heatsinks and thermal interace materials: Select a heatsink and thermal interace material vendor (see Guidance to Select a Cooling Solution ). Note that the EPE assumes a deault case-to-heatsink thermal resistance θ CS = 0.1 C/W (or manual calculation, see Manual Calculation o Junction Temperature TJ ). Validate the Cooling Solution Use the EPE to validate the cooling solution. Option 1: Using standard values or heatsink and airlow Heatsink: low (15 mm), medium (23 mm), high (33 mm) proile Airlow: 100 lm (0.5 m/s), 200 lm (1.0 m/s), 400 lm (2.0 m/s) Board thermal model: none (conservative) or typical board Analyze the results under Thermal Analysis in the EPE Option 2: Using custom values or heatsink and airlow Heatsink: custom solution Airlow: not applicable, included in θ SA Enter the custom rom the cooling solution Board thermal model: custom Enter the custom rom the board θ JB θ SA Analyze the results under Thermal Analysis in the EPE 2

3 Altera Corporation High-Speed Board Design Advisor Reerences Junction Temperature T J and T JMAX Get the maximum junction temperatures T JMAX, T J rom the Stratix II GX DC and Switching Characteristics chapter o the handbook: Stratix II GX device absolute maximum ratings: -55 C < T J < 125 C Stratix II GX device recommended operating conditions: T J For commercial use: 0 C < T J < 85 C (T JMAX ) For industrial use: -40 C < T J < 100 C (T JMAX ) When selecting the cooling solution, the calculated T J should not exceed T JMAX or the device's recommended operating condition. Thermal Resistance Values or Stratix II GX FPGAs Get the thermal resistance or the FPGA device and package rom the Stratix Series Device Thermal Resistance Data Sheet: Junction-to-ambient thermal resistance ( θ JA ) at still air, 100 lm (0.5 m/s), 200 lm (1.0 m/s), 400 lm (2.0 m/s) without a heatsink Junction-to-case thermal resistance ( θ JC ) Junction-to-board thermal resistance ( ) Guidance to Select a Cooling Solution Select the cooling solution and get the thermal resistance including heatsink and airlow (n). Heatsink-to-ambient thermal resistance ( ) Thermal resistance or thermal interace material rom the vendors data sheet (n): Case-to heatsink thermal resistance ( ) θ JB θ CS θ SA Manual Calculation o Junction Temperature T J Estimate the board temperature T B (T A < T B < T J ) Worst-case estimation: T B = T J Best-case estimation: T B = T A Calculate T J using the ollowing ormula: P θ JA θ JB + T A θ JB + T B θ JA( Total) T J = , θ θ JA + θ JA( Total) = θ JC + θ CS + θ SA JB θ JA Total reers to the total thermal resistance including the heatsink solution. resistance (junction-to-ambient) rom the device package data sheet. Power Analysis Beore Starting the FPGA Design ( ) θ JA Select Stratix II GX FPGAs as the target amily, device, and package. usually reers to the thermal The Stratix II GX EPE User Guide provides more inormation on how to enter the inormation in the EPE: Select the operating conditions, environment conditions, and junction temperature. Speciy the device resources, operating requency, and toggle rates o the design. The PowerPlay EPE displays the estimated power usage in the Total section. 3

4 High-Speed Board Design Advisor Altera Corporation Power Analysis While Creating the FPGA Design Compile the partial FPGA design in the Quartus II sotware. Generate the PowerPlay EPE ile (<revisionname>_early_pwr.csv) in the Quartus II sotware by clicking Generate PowerPlay Early Power Estimator File in the Project menu. Import the PowerPlay EPE ile (click on Import Quartus II File) into the PowerPlay EPE spreadsheet to populate the spreadsheet entries automatically. Ater importing the ile to populate the PowerPlay EPE, manually edit the cells to relect inal device resource estimates. The PowerPlay EPE will display the estimated power usage in the Total section. PowerPlay Power Analyzer in Quartus II Sotware Compile the FPGA design with realistic timing constraints in the Quartus II sotware. The Power Analysis chapter o the Quartus II Handbook provides more inormation on using the power analyzer tool: Simulate the design (preerably with gate-level simulation) and create a signal activity ile (.sa) or value change dump (.vcd) ile containing the toggle rate data inormation o the design, using Quartus II simulator or any supported third-party simulator. Speciy the operating conditions o the design in Quartus II sotware rom the Assignment menu. Choose the PowerPlay Power Analyzer tool rom the Processing menu. To use the Signal Activity File(s), Value Change Dump File(s), or both as an input to the PowerPlay Power Analyzer, turn on Use Input File(s) to utilize toggle rates and static probabilities during power analysis. I the simulation output iles are not available, then enter the deault toggle rate or use vectorless estimation. The PowerPlay Power Analyzer estimates the total thermal power consumption o the design based on input data entered and generates comprehensive power estimation reports. Use these power analyzer reports or power planning and power optimization purposes. PowerPlay Power Optimization Use a smaller device that its the design as it will have less static power consumption. Use a better cooling solution, such as a heatsink or airlow, or reduce dynamic or I/O power to reduce the junction temperature. This will result in lower device static power. Set the PowerPlay power optimization option value as Extra eort or Analysis and Synthesis Settings in Quartus II sotware. This optimization option allows the synthesis netlist to ully optimize the design or power. Set the PowerPlay power optimization option value as Extra eort or Fitter Settings in Quartus II sotware. This setting can be applied only on a project-wide basis and perorms place-and-route optimization during itting to ully optimize the design or power. Use area optimization rather than timing or delay optimization to save power. Use gate-level register retiming to reduce circuit switching activity. Use clock control blocks to dynamically enable or disable the clock networks. Use clock enable signals or the memory blocks. Use pipelining and retiming or designs with many glitches. The Power Optimization chapter in the Quartus II Handbook provides more inormation on dierent techniques to urther optimize the design or power: 4

5 Altera Corporation High-Speed Board Design Advisor Temperature-Sensing Diode or Power Management Reer to the Coniguration and Testing chapter o the Stratix II GX Handbook (Keyword: Temperature Sensing Diode): Thermal Analysis Simulation Perorm thermal analysis and test design modiications in the early stages o the design process to Solve thermal problems beore the hardware is built Reduce design respins and product unit costs Improve reliability and overall engineering design Altera provides compact thermal models (CTM) deined by JEDEC, please contact an Altera sales representative or uther inormation: Two-resistor (2-R) model DELPHI model: Thermal simulation tools Flomerics: Icepak: Further Inormation Heatsink vendors: Alpha Novatech: Malico Inc.: Aavid Thermalloy: Wakeield Thermal Solutions: Radian Heatsinks: Cool Innovations: Heat Technology, Inc.: Thermal interace material vendors: Shin-Etsu MicroSi: LORD Corporation: Laird Technologies: Chomerics: The Bergquist Company: 5

6 High-Speed Board Design Advisor Altera Corporation High-Speed Board Design Advisor: Power Distribution Network: High-Speed Board Design Advisor: Pinout Deinition: High-Speed Board Design Advisor: High-Speed Channel Design and Layout: High-Speed Board Design Advisor: Hardware Integration, Test, and Debug: Innovation Drive San Jose, CA Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, speciic device designations, and all other words and logos that are identiied as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks o Altera Corporation in the U.S. and other countries. All other product or service names are the property o their respective holders. Altera products are protected under numerous U.S. and oreign patents and pending applications, maskwork rights, and copyrights. Altera warrants perormance o its semiconductor products to current speciications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out o the application or use o any inormation, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version o device speciications beore relying on any published inormation and beore placing orders or products or services. 6

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