DKAN0008A PIC18 Software UART Timing Requirements

Transcription

1 DKAN0008A PIC18 Sotware UART Timing Requirements 11 June 2009 Introduction Design conditions oten limit the hardware peripherals available or an embedded system. Perhaps the available hardware UARTs are already allocated, or the system requires alternate unctionality (creating a conlict when the UART shares a common pin). Implementing the UART in sotware is one common solution. The Microchip MPLAB C18 C Compiler Libraries include sotware UART unctions. Implementing this UART requires the user to calculate and meet the speciic timing requirements or the desired baud rate. This application note provides inormation on the time delays required in the serial data sampling routines and the relationship between the sampling rate and the serial data. Background The MPLAB C18 compiler eatures both hardware and sotware libraries or each communications peripheral ound in Microchip s PIC18 amily o microcontroller products. The hardware libraries take ull advantage o port registers and assigned port pins, while the sotware libraries allow the user to speciy and conigure GPIO pins as a communications port. amiliarity with the MPLAB IDE environment, the MPLAB C18 C Compiler, and RS232 is assumed. The deault library unctions expect a host serial port conigured or 8 data s, 1 stop, no parity, and no low control. Microchip provides all o the assembly iles or the library, so the developer can modiy the coniguration and/or port pins. Application The C18 library provides unctions or initializing ports and transmitting/receiving serial data. However, the embedded developer must provide the delay routines used by the library unctions, namely DelayTXBitUART, DelayRXHalBitUART, and DelayRXBitUART. These routines set delays that correspond to the periods during communication. This provides a means to synchronize data transer and received data. Incoming data is identiied by continuously polling the receive pin. A high-to-low transition indicates the start o the serial data rame. A hal- delay sets the point at the start s midpoint. Ater the initial hal- delay, ull- delays are used to the remaining data. This is repeated or each rame o received data. igure 1 illustrates this technique or one rame. Page 1 o 6

2 PIC18 Sotware UART Timing Requirements start transition hal- delay ull- delay ull- delay ull- delay ull- delay ull- delay ull- delay ull- delay ull- delay Logic 1 Idle Start Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Stop Idle Logic 0 igure 1. RS-232 Logic Level Signal Sample and Delay Contributing actors to sampling error include the initial response delay to the start, the hal- and ull- delay inaccuracies, and the transmitter and receiver clock tolerances. Each actor contributes a small t rom the ideal point o each. These deviations accumulate over the entire data rame and can shit the point beore or ater a data position, resulting in data recovery errors. Some analysis is required to assure reliable communication. Initial Response Delay The initial response delay t ird is the maximum time between the start s transition and its detection. It is determined by how oten the receive pin is polled. Thereore, the number o instructions executed by the microcontroller between polling s inluences the size o the initial response delay. t ird contributes a one-time oset to each data rame. igure 2 illustrates the timing errors. Use equation (1) to calculate the time delay provided by the polling routine. Start transition Start transition + initial response delay Ideal point Sample point delay (hal- + polling) Ideal point Nominal window Sample point delay (hal- + ull- + polling) Tcte Ideal point Tcte Sample window shit rom eect o polling, hal, and ull- delays Logic 1 Target Receive Idle Start Bit 1 Bit 8 Stop Logic 0 igure 2. Sample Point Change (1) t ird Polling _ routineinstruction _ cycles Digi-Key Corporation Page 2 o 6

3 PIC18 Sotware UART Timing Requirements or example, a inal clock requency o 4MHz and 3 instruction cycles in the polling routine results in a t ird o 3us. Receive Hal-Bit and ull-bit Delays The receive hal- and ull- delays determine the number o instruction cycles required or any illator and rate combination (see also the C18 library documentation, Chapter 3.6). Equations (2) and (3) deine these relationships, respectively baud (2) RXhaldelay 9( ) baud (3) RXdelay 14( ) 2 or example, a inal clock requency o 4MHz and a baud rate o 9600bps require a hal- delay o 44 instruction cycles and a ull- delay o 91 instruction cycles. Use equations (4) and (5) to calculate the time delay provided by the hal- and ull- instruction cycle delays, respectively. or the example above, the hal- time delay is 53us, and the ull- time delay is 105us. (4) (5) Thal T ( RXhaldelay + 9) ( RXdelay + 14) or received data at 9600bps, the total time period (1 start, 8 data s) is 937.5us, with the last data s center point at 885.4us. Sampling the incoming data requires 1 Thal and 8 T delays, totaling 893us. The point o the last data is oset by approximately 7.6us rom the center o the period. Clock Tolerance Error The clock variation between the transmitter and receiver also contribute to the sampling error. Clock error Tcte is the time between the point and the n th data o the transmitted data rame. The window bounded by Tcte and Tcte varies, since microcontroller internal illators can vary by ±2% at ambient and ±10% over the operational temperature range. max and min are the worst case clock requencies in the application s environment. Equations (6) and (7) determine i the inal occurs beore the end o the n th o the data rame. (6) Tcte ns 0.5 min tx,max tx, ns Digi-Key Corporation Page 3 o 6

4 PIC18 Sotware UART Timing Requirements (7) Tcte < 0 ns is the number o s in the packet (including start and data s). Equations (8) and (9) ensure that the takes place ater the n th begins. (8) Tcte ns 0.5 max t tx,min tx, ns 1 (9) Tcte > 0 Assume a host transmit rate o 9600bps, 9 s to recover (1 start, 8 data s), and a 4MHz clock with an accuracy o ±2%. The receiving microcontroller s clock o 4MHz also has an accuracy o ±2%. Using equation (6) and (8) results in Tcte -15.6us and Tcte 17.7us, meeting the timing boundary conditions in equation (7) and (9). With the transmit clock accuracy decreased to ±4 %, Tcte 2.0us and Tcte 0us, ailing the boundary requirements, resulting in communication errors at the worst case clock requencies. Total Receive Error Total receiver error Ttre is the sum o the initial response delay, the hal- and ull- delays, and the clock tolerance error. In eect, the window, bounded by the clock variation, is shited in time due to the accumulation o timing errors. This shit can cause the window to all outside the data boundaries, resulting in communication errors. Equations (10) and (11) determine i the inal occurs beore the end o the n th o the data rame. Equations (12) and (13) ensure that the takes place ater the n th begins. ( ( ) (10) Ttre Tcte + t + Thal + T ( ns 1) min ird (11) Ttre < ns 0.5 baud ( ( ) (12) Ttre Tcte + t + Thal + T ( ns 1) max ird (13) Ttre > ns 0.5 baud Expanding on the prior example, assume a host transmit rate o 9600bps, 9 s to recover (1 start, 8 data s), and a 4MHz clock with an accuracy o ±2%. The receiving microcontroller s 4MHz clock has an accuracy o ±2%. Applying the results rom equations (1), (4), (5), (6) and (8), in equations (10) and (12) results in Ttre -15.6us and Ttre 17.7us, meeting the timing boundary conditions in equation (11) and (13). Digi-Key Corporation Page 4 o 6

5 PIC18 Sotware UART Timing Requirements Accumulated timing eects can move the point to the edge o the period. Noise on the line or capacitive eects altering the signal edge rate can urther reduce the margin until data is not reliably recovered. Transmission ull-bit Delay Error Data transmission rom the target also introduces timing errors rom the ull- delay inaccuracy and clock tolerance. The transmit ull- delay, equation (14), determines the number o instruction cycles required or any illator and rate combination. Equation (15) calculates the time delay provided by the ull- instruction cycle delay baud (14) TXdelay 12( ) 2 (15) T tx _ delay ( TXdelay + 12) or a microcontroller clock requency o 4MHz and a baud rate o 9600bps, a ull- delay o 93 instruction cycles is required. The ull- time delay is 105us. Transmission timing errors accumulate as the start, 8 data s, and stop are transmitted and may impact the ability o the host receiver to recover the data. Conclusion A conservative timing margin must be maintained to ensure reliable data transer. I high rates are required, a tight clock tolerance enhances the timing margin. Increasing the clock requency reduces the sotware hal- and ull- delay inaccuracies. Reducing the serial data rate provides longer periods, increasing the timing margin. Using sotware UART is not without pitalls. But, once the contributing error actors are understood and ameliorated, a reliable serial communication port can be implemented using any pair o GPIO pins. Additional Inormation MPLAB C18 C Compiler Libraries, Chapter 3.6; Microchip Technology, Inc. Digi-Key Corporation Page 5 o 6

6 PIC18 Sotware UART Timing Requirements Disclaimer This document is or inormational use only and is subject to change without prior notice. Digi-Key makes no commitment to update or keep current the inormation contained herein. Digi-Key does not guarantee or warrant that any inormation provided is accurate, complete, or correct and disclaims any and all liability associated with the use o the inormation contained herein. The use o this inormation and Digi-Key s liability is subject to Digi-Key s standard Terms & Conditions which can be ound at by clicking on the Terms & Conditions link at the bottom o the web page. No license, whether express, implied, arising by estoppel or otherwise is granted under any intellectual property or other rights o Digi-Key or others. Trademarks DIGI-KEY is a registered trademark o Digi-Key Corporation. All other trademarks, service marks and product names contained herein are the sole property o their respective owner and their use is or inormational purposes only and does not imply any endorsement, recommendation, sponsorship or approval by the trademark owner o the contents. Copyright Use o this document is limited to customer s internal business use or the evaluation and purchase o products. No permission is granted to the user to copy, print, store, distribute, transmit, display in public or modiy the content o this document in any way or any other purpose. Copyright 2009 Digi-Key Corporation. All rights reserved. Digi-Key Corporation Page 6 o 6