UHF ASK/FSK. Transmitter T5754

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1 Features Integrated PLL Loop Filter ESD Protection (4 kv HBM/200 V MM; Except Pin 2: 4 kv HBM/100 V MM) also at / High Output Power (. dbm) with Low Supply Current (9.0 ma) Modulation Scheme ASK/ FSK FSK Modulation is Achieved by Connecting an Additional Capacitor Between the Load Capacitor and the Open Drain Output o the Modulating Microcontroller Easy to Design-in Due to Excellent Isolation o the PLL rom the PA and Power Supply Single Li-cell or Power Supply Supply Voltage 2.0 V to 4.0 V in the Temperature Range o -40 C to 8 C/12 C Package TSSOP8L Single-ended Antenna Output with High Eicient Power Ampliier CLK Output or Clocking the Microcontroller One-chip Solution with Minimum External Circuitry 12 C Operation or Tire Pressure Systems UHF ASK/FSK Transmitter T4 Description The T4 is a PLL transmitter IC which has been developed or the demands o RF low-cost transmission systems at data rates up to 2 kbaud. The transmitting requency range is 429 MHz to 49 MHz. It can be used in both FSK and ASK systems. Figure 1. System Block Diagram 1 Li cell Keys Encoder ATARx9x UHF ASK/FSK Remote control transmitter T4 XTO PLL VCO Antenna Antenna U41B/ U4B/ T4/ T44 UHF ASK/FSK Remote control receiver Demod. IF Amp PLL Control XTO 1... Microcontroller Power amp. LNA VCO Rev.

2 Pin Coniguration Figure 2. Pinning TSSOP8L CLK 1 8 PA_ 2 GND T4 6 VS 4 Pin Description Pin Symbol Function Coniguration VS 1 CLK Clock output signal or microconroller The clock output requency is set by the crystal to / CLK 2 PA_ Switches on power ampliier, used or ASK modulation PA_ 0k U re = 1.1 V 20 µa Emitter o antenna output stage 4 Open collector antenna output 1.k 1.2k Connection or crystal 182 µa 6 VS Supply voltage See ESD protection circuitry (see Figure 8 on page 8) GND Ground See ESD protection circuitry (see Figure 8 on page 8) 8 Enable input 200k 2 T4

3 T4 Figure. Block Diagram T4 Power up/down CLK PA_ 2 PFD GND CP VS 6 LF 4 PA VCO XTO PLL General Description This ully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmitters to be assembled. The VCO is locked to 2 hence a 1.6 MHz crystal is needed or a 4.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are needed as external elements. The crystal oscillator together with the PLL needs typically <1 ms until the PLL is locked and the CLK output is stable. There is a wait time o 1 ms until the CLK is used or the microcontroller and the PA is switched on. The power ampliier is an open-collector output delivering a current pulse which is nearly independent rom the load impedance. The delivered output power is hence controllable via the connected load impedance. This output coniguration enables a simple matching to any kind o antenna or to 0. A high power eiciency o =P out /(I S,PA ) o 6% or the power ampliier results when an optimized load impedance o Z Load = (166 + j22) is used at V supply voltage.

4 Functional Description I = L and the PA_ = L, the circuit is in standby mode consuming only a very small amount o current so that a lithium cell used as power supply can work or several years. With = H the XTO, PLL and the CLK driver are switched on. I PA_ remains L only the PLL and the XTO is running and the CLK signal is delivered to the microcontroller. The VCO locks to 2 times the XTO requency. With = H and PA_ = H the PLL, XTO, CLK driver and the power ampliier are on. With PA_ the power ampliier can be switched on and o, which is used to perorm the ASK modulation. ASK Transmission FSK Transmission The T4 is activated by = H. PA_ must remain L or t 1 ms, then the CLK signal can be taken to clock the microcontroller and the output power can be modulated by means o Pin PA_. Ater transmission PA_ is switched to L and the microcontroller switches back to internal clocking. The T4 is switched back to standby mode with = L. The T4 is activated by = H. PA_ must remain L or t 1 ms, then the CLK signal can be taken to clock the microcontroller and the power ampliier is switched on with PA_ = H. The chip is then ready or FSK modulation. The microcontroller starts to switch on and o the capacitor between the load capacitor and GND with an open-drain output port, thus changing the reerence requency o the PLL. I the switch is closed, the output requency is lower than i the switch is open. Ater transmission PA_ is switched to L and the microcontroller switches back to internal clocking. The T4 is switched back to standby mode with = L. The accuracy o the requency deviation with pulling method is about ±2% when the ollowing tolerances are considered. Figure 4. Tolerances o Frequency Modulation ~ C Stray1 C Stray2 ~ C M L M R S C 4 C 0 Crystal equivalent circuit C C Switch Using C 4 = 9.2 pf ± 2%, C = 6.8 pf ± %, a switch port with C Switch = pf ± 10%, stray capacitances on each side o the crystal o C Stray1 =C Stray2 = 1 pf ± 10%, a parallel capacitance o the crystal o C 0 =.2 pf ± 10% and a crystal with C M = 1 F ± 10%, an FSK deviation o ±21 khz typical with worst case tolerances o ±16. khz to ±28.8 khz results. CLK Output Clock Pulse Take-over An output CLK signal is provided or a connected microcontroller, the delivered signal is CMOS compatible i the load capacitance is lower than 10 pf. The clock o the crystal oscillator can be used or clocking the microcontroller. Atmel s ATARx9x has the special eature o starting with an integrated RC-oscillator to switch on the T4 with = H, and ater 1 ms to assume the clock signal o the transmission IC, so that the message can be sent with crystal accuracy. 4 T4

5 ~ T4 Output Matching and Power Setting The output power is set by the load impedance o the antenna. The maximum output power is achieved with a load impedance o Z Load,opt = (166 + j22). There must be a low resistive path to to deliver the DC current. The delivered current pulse o the power ampliier is 9 ma and the maximum output power is delivered to a resistive load o 46 i the 1.0 pf output capacitance o the power ampliier is compensated by the load impedance. An optimum load impedance o: Z Load = 46 j/(2 1.0 pf) = (166 + j22) thus results or the maximum output power o. dbm. The load impedance is deined as the impedance seen rom the T4 s, into the matching network. Do not conuse this large signal load impedance with a small signal input impedance delivered as input characteristic o RF ampliiers and measured rom the application into the IC instead o rom the IC into the application or a power ampliier. Less output power is achieved by lowering the real parallel part o 46 where the parallel imaginary part should be kept constant. Output power measurement can be done with the circuit o Figure. Note that the component values must be changed to compensate the individual board parasitics until the T4 has the right load impedance Z Load,opt = (166 + j22). Also the damping o the cable used to measure the output power must be calibrated out. Figure. Output Power Measurement C 1 = 1n L 1 = n Z = 0 Ω Power meter Z Lopt C 2 = 2.2p R in 0 Ω ~ Application Circuit For the supply-voltage blocking capacitor C a value o 68 nf/xr is recommended (see Figure 6 on page 6 and Figure on page ). C 1 and C 2 are used to match the loop antenna to the power ampliier where C 1 typically is 8.2 pf/np0 and C 2 is 6 pf/np0 (10 pf + 1 pf in series); or C 2 two capacitors in series should be used to achieve a better tolerance value and to have the possibility to realize the Z Load,opt by using standard valued capacitors. C 1 orms together with the pins o T4 and the PCB board wires a series resonance loop that suppresses the 1 st harmonic, hence the position o C 1 on the PCB is important. Normally the best supression is achieved when C 1 is placed as close as possible to the Pins and. The loop antenna should not exceed a width o 1. mm, otherwise the Q-actor o the loop antenna is too high. L 1 ([0 nh to 100 nh) can be printed on PCB. C 4 should be selected that the XTO runs on the load resonance requency o the crystal. Normally, a value o 12 pf results or a 1 pf load-capacitance crystal.

6 Figure 6. ASK Application Circuit S 1 ATARx9x V DD 1 S 2 S 20 OSC1 T4 Power up/down CLK PA_ 2 PFD GND C C 2 CP 6 Loop Antenna C1 LF 4 PA VCO XTO L 1 PLL C 4 6 T4

7 T4 Figure. FSK Application Circuit ATARx9x S 1 V DD 1 S 2 S 20 BP42/T2O 18 OSC1 T4 Power up/down CLK PA_ 2 PFD GND C C 2 CP 6 Loop Antenna C1 LF 4 PA VCO XTO C C 4 L 1 PLL

8 Figure 8. ESD Protection Circuit VS CLK PA_ GND Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and unctional operation o the device at these or any other conditions beyond those indicated in the operational sections o this speciication is not implied. Exposure to absolute maximum rating conditions or extended periods may aect device reliability. Parameters Symbol Minimum Maximum Unit Supply voltage V Power dissipation P tot 100 mw Junction temperature T j 10 C Storage temperature T stg - 12 C Ambient temperature T amb - 12 C Thermal Resistance Parameters Symbol Value Unit Junction ambient R thja 10 K/W Electrical Characteristics = 2.0 V to 4.0 V, T amb = -40 C to 12 C unless otherwise speciied. Typical values are given at =.0 V and T amb = 2 C. All parameters are reered to GND (pin ). Parameters Test Conditions Symbol Min. Typ. Max. Unit Supply current Supply current Supply current Power down V < 0.2 V, -40 C to 8 C V PA- < 0.2 V, -40 C to +12 C V PA- < 0.2 V, 2 C (100% correlation tested) Power up, PA o, = V, V >1.V, V PA- <0.2V Power up, =.0 V, V >1.V, V PA- >1.V I S_O <10 0 na µa na I S. 4.8 ma I S_Transmit ma 8 T4

9 T4 Electrical Characteristics (Continued) = 2.0 V to 4.0 V, T amb = -40 C to 12 C unless otherwise speciied. Typical values are given at =.0 V and T amb = 2 C. All parameters are reered to GND (pin ). Parameters Test Conditions Symbol Min. Typ. Max. Unit Output power Output power variation or the ull temperature range Output power variation or the ull temperature range =.0 V, T amb =2 C, = 4.92 MHz, Z Load = (166 + j2) T amb = -40 C to +8 C, =.0 V = 2.0 V T amb = -40 C to +12 C, =.0 V = 2.0 V, P Out = P Re + P Re P Re.. 10 dbm P Re -1. P Re -4.0 P Re -2.0 P Re -4. Achievable output-power range Selectable by load impedance P Out_typ 0. dbm Spurious emission Oscillator requency XTO (= phase comparator requency) CLK = 0 /128 Load capacitance at Pin CLK = 10 pf O ± 1 CLK O ± 4 CLK other spurious are lower XTO = 0 /2 = resonant requency o the, C M 10 F, load capacitance selected accordingly T amb = -40 C to +8 C, T amb = -40 C to +12 C XTO PLL loop bandwidth 20 khz Phase noise o phase comparator Reerred to PC = XT0, 2 khz distance to carrier dbc/hz In loop phase noise PLL 2 khz distance to carrier dbc/hz Phase noise VCO at 1 MHz at 6 MHz db db db db dbc dbc ppm ppm dbc/hz dbc/hz Frequency range o VCO VCO MHz Clock output requency (CMOS microcontroller compatible) 0 /128 MHz Voltage swing at Pin CLK C Load 10 pf V 0h 0.8 V V 0l 0.2 V Series resonance R o the crystal Rs 110 Capacitive load at Pin XT0 pf FSK modulation requency rate ASK modulation requency rate input PA_ input Duty cycle o the modulation signal = 0% Duty cycle o the modulation signal = 0% Low level input voltage High level input voltage Input current high Low level input voltage High level input voltage Input current high V Il V Ih I In 1. V Il V Ih I In khz 0 2 khz V V µa V V µa 9

10 Ordering Inormation Extended Type Number Package Remarks T4-6AQ TSSOP8L Taped and reeled Package Inormation 10 T4

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T5753C. UHF ASK/FSK Transmitter DATASHEET. Features

T5753C. UHF ASK/FSK Transmitter DATASHEET. Features T553C UHF ASK/FSK Transmitter DATASHEET Features Integrated PLL loop ilter ESD protection also at / (3kV HBM/150V MM; Except pin 2: 3kV HBM/100V MM) High output power (8.0dBm) with low supply current (9.0mA)