An image rejection re-configurable multi-carrier 3G base-station transmitter

Transcription

1 An image rejection reconigurable multicarrier 3G basestation transmitter Dimitrios Estathiou Analog Devices, 79 Triad Center Drive, Greensboro, NC 2749, USA ABSTRACT Recent trends in basestations wideband transmitters, point to continuing reduction o analog RF processing at the expense o increased digital signal processing. An eicient hardware design takes advantage o digital algorithmic approaches, and with proper architectural partitioning, makes a multicarrier transmitter using a single analog upconversion practical. This paper addresses the technical challenges or WCDMA/TD SCDMA multicarrier basestation transmitter and presents a solution based on existing products. I. INTRODUCTION Despite the recent decline in cellular handset production, the wireless inrastructure is still being built. Investments in inrastructure remain in place and that basestation construction continues although at a somewhat slower pace. The combination o demand or lower cost second generation (2G systems and the initial deployment o third generation (3G systems encourages the basestation manuacturers to adopt new reconigurable hardware platorms. These hardware platorms introduce new requirements in terms o dynamic range and sampling requencies than previous generations. The basestation manuacturers request rom the component manuacturers components with enhanced perormance, more unctionality, higher integration, lower power, and lower cost. Many basestation (BTS manuacturers see a multicarrier transceiver coniguration as the main path to achieve an optimal solution or supporting a variety o wireless airinterace standards in a single inrastructure design. Technologies such as Reconigurable Radio are essential to enable what will eventually become the winning strategies o the equipment manuacturers and network operators. Investingin and developing those technologies now is the true key to success. Classic basestation architectures require a complete transceiver or every RF carrier processed (rom 4 to 8 channels or digital and analog systems respectively. These radios must be multiplied or diversity. It is easy to see why basestation electronics consume so much space, power, and cost. The beauty o a multicarrier transceiver is the elimination o redundant radios in avor o a single, highperormance radio per antenna, where each RF carrier is processed in the digital domain. However, this beneit does not come alone. There are some systems challenges associated with multicarrier transmitters due to the perormance demands o 2G and 3G airinteraces speciications and perormance limitations o existing components. This paper addresses the critical unctional blocks and technology challenges o a multicarrier transmitter subsystem or 3G basestations. Section II discusses technical challenges related to multicarrier WCDMA and TDSCDMA Transmitter. Section III presents a reconigurable subsystem or WCDMA and TD SCDMA image rejection basestation transmitter and describes the mixedsignal and digital components o this architecture. II. MULTICARRIER Tx CHALLENGES Digital to analogue converters (DAC and multicarrier power ampliiers (MCPA must preserve the spectrum o several digitally generated carriers without corruption or spurious signal generation in adjacent channels. A basestation transmitter must generate a minimum o spectral regrowth both on the individual carriers and as a result o intermodulation between the carriers. A DAC that can generate higher requencies enables a reduction in the number o upconversion stages rom two to one. Unortunately, converter perormance deteriorates at higher requencies [1]. Multicarrier transmission diers rom singlecarrier radios, which rely on analogue s to remove undesired signals that could corrupt adjacent channels. Instead, the multicarrier architectures must inherently limit distortion over the entire transmission bandwidth. The peaktoaverage power ratio (PAPR o the signal depends on the number o codes and carriers. The maximum PAPR occurs i all codes and carriers add in phase. System simulation showed that the input signal o the DAC can be clipped up to db. The perormance o the DAC should not be signiicantly decreased by the Transmit Signal Processor. To lower the linearity requirements or the multicarrier power ampliier, the ACLR speciication or the DACs shall not exceed the values speciied in Table 1a or TD SCDMA [2] and Table 1b or WCDMA [3]. A Radio Frequency (RF power ampliier is a nonlinear device. When it carries a signal that does not have a constant envelope, a group o carriers or the sum o several CDMA signals, the power ampliier generates intermodulation (IM distortion. Since the IM power alls into adjacent channels as intererence,

2 advanced wideband power ampliier linearisation schemes have become a key technology in multicarrier transceivers. oset rom center requency Max BTS ACLR value ± 1.6 MHz 65 ± 3.2 MHz 73 ± 4.8 MHz 73 oset rom center requency (a Max BTS ACLR value ± 5 MHz 55 ± MHz 6 (b Table 1. ACLR requency oset and minimum requirement. Fig. 1 shows a multicarrier subsystem that incorporates all o the elements traditionally ound in a 3G basestation transmitter, with the addition o a linearization element in order to meet multicarrier adjacent channel power speciications. The wide dynamic range o a 16bit DAC allows many Transmit Signal Processors (TSPs summed channels to be transmitted over several MHz o bandwidth where the peaktoaverage output signal ratio is high, with average output signal level at a raction o the ull scale range. The approach ollowed in this work is that basestation manuacturers are interested to build a common hardware platorm that could be easily reconigured or various wireless airinteraces. III. MULTICARRIER TDSCDMA TRANSMITTER This section presents a solution to modulate three TD SCDMA carriers or two WCDMA carriers with a TSP (AD6623, an interpolation DAC (AD9777, and a single analog modulator (AD8346. TDSCDMA radio interace is integrated by 3GPP as the low chip rate option o UTRATDD, LCR (1.28 Mcps chip rate, 1.6 MHz bandwidth. The highchiprate mode will appear as UTRATDD HCR (3.84 Mcps chip rate, 5 MHz bandwidth. Two spectrum bands have been allocated or UTRATDD, the irst one is 2 MHz (19 MHz 192 MHz and the second one is 15 MHz (2 MHz 225 MHz. The UTRAFDD (WCDMA has a chip rate o 3.84 Mcps and occupies 5 MHz o bandwidth. A 6 MHz band (21 MHz 217 MHz is allocated to UTRAFDD or BTS transmission. However, each operator could have a license or up to 2 MHz o continuous bandwidth. In this work we assume that two WCDMA or three TDSCDMA carriers are located anywhere within the 2 MHz bandwidth available to an operator. The transmitter is presented using a multichannel system architecture where Intermediate Frequency (IF upconversion is done in a digital manner (ig. 2. The highest integer oversampling o the TDSCDMA chip rate below 4 MHz is MHz (1.28 Mcps In this coniguration, the objective o TSP is to constrain the bandwidth o the output signal so that it remains below the transmit mask deined or TD SCDMA [2]. The baseband signal has a chip rate o 1.28 Mcps. The TSP running with CLK = MHz perorms the root raised cosine ing, interpolation (rollo actor α =.22 and requency shiting. The serial data source drives data at SCLK = CLK /2 = 4.96 Mbps (or = 4.96 Mbps per TSP processing channel. This coniguration is nearly optimal or the TSP. The master clock runs at MHz, which allows the programmable FIR to calculate 39 taps N FIR = CLK IN 1 2 (2 The programmable coeicient FIR interpolates the input signal by a actor o 3 and precompensates or the CIC rollo in the passband. The FIR output rate is 3.84 Msps per processing channel. The programmable power ramp up/down unit allows power ramping on a timeslot basis as speciied or TD SCDMA. The second stage, a ith order CascadedIntegratorComb (CIC5 provides an interpolation o L CIC5 = 13. The CIC5 output rate is Msps. The third stage, a second order resampling Cascaded Integrator Comb (CIC provides no interpolation o (L rcic2 = 1. The CIC2 output rate is Msps (complex samples. The CIC and Numerically Controlled Oscillator (NCO save power by running at the complex rate o MHz. The interpolated baseband TDSCDMA signal is requency shited to an IF = 6.24 MHz by a sine/cosine sequence generated by the NCO and the carriers are shited by the TSP to a requency band rom MHz to 3.76 MHz. Fig. 3a presents the TSP composite transer unction (FIR and Cascaded Integrator Comb s with a.116 db passband ripple and a stopband at ±.435 MHz. Multicarrier phase synchronization pins and phase oset registers allow intelligent management o the relative phase o independent Radio Frequency (RF channels. The calculated Error Vector Magnitude at TSP output is.47 %. An interpolation DAC is conigured to accept interleaved I & Q data rom a TSP (ig. 1. The data interace is 32 bits wide, 16 bits or the real and 16 bits or the imaginary portion. AD9777 generates a complex modulated IF signal via its dual DACs, which is then translated to RF by an analog quadrature modulator. The image rejection and requency shit capability o the DAC determines the requirements o the ollowing analog stages. DAC interpolates the data by L DAC = 8 resulting in a sample rate to

3 Msps. This coniguration allows the 43tap irst stage to run at /8 = MHz. The 8x allows the DAC to run near its maximum rate which increases separation, reduces sin(x/x rollo and reduces DAC distortions associated with large steps between samples. The complex F DAC /8 mixer stage shits the band by MHz. The TDSCDMA carriers are placed to a band rom MHz to MHz. The band is centred to an IF o MHz ( / 8 MHz. Fig. 4 shows a dashed rectangle within it three ed TDSCDMA carriers can be located at interpolating DAC output. For a twocarrier WCDMA BTS the TSP is divided into two pairs. Each processing pair s, tunes, and combines one WCDMA carrier onto a complex digital IF at MSPS. The TSP is clocked at MHz. The serial data source drives data at SCLK = CLK /2 = Mbps (or = Mbps per processing channel. Pairs o processing channels work together to the 32bit I&Q inputs at 3.84 Mcps. To realize longer s, each processing channel only computes the complete impulse response to hal o the inputs. The irst paired channel accepts the even inputs samples at 1.92 Msps, and the second paired channel accepts the odd inputs also at 1.92 Msps. When output responses are linearly combined at high rate and proper sampling phase and matching NCO phases, the complete is realized at the ull rate. The FIR perorms root raised cosine pulse shaping (a=.22 and interpolates the 1.92 Msps rate by 5 to 9.6 Msps. The second stage a ith order Cascaded Integrator Comb (CIC interpolates the FIR output by L CIC5 = 5 to 48 Msps. The third stage is a resampling second order CIC which interpolates the CIC5 output by 32/25 to Msps. The interpolated WCDMA signal is requency shited to an IF = MHz by a sine/cosine sequence generated by the NCO and the Msps complex product is combined with the results rom the other processing channels and then interleaved onto a single output bus at MHz. The inphase (I and quadrature (Q words are interleaved at MHz on a single bus to a DAC. The two carriers are shited by the TSP to a requency band o MHz to 5.36 MHz. Fig. 3b presents the TSP composite transer unction (FIR and Cascaded Integrator Comb s with a.6 db passband ripple and a stopband at ±1.5 MHz. Multicarrier phase synchronization pins and phase oset registers allow intelligent management o the relative phase o independent RF channels. The calculated Error Vector Magnitude at TSP output is 1.85%. The DAC is conigured to accept interleaved the I & Q data. The DAC interpolates the Msps complex input by L DAC = 2 to Msps. An internal PLL produces all the clocks necessary or the DAC and the TSP rom a single MHz reerence. The complex F DAC /4 mixer stage shits the band by MHz. The WCDMA carriers are placed to a band rom 36.8 MHz to 56.8 MHz. The band is centred to an IF o 46.8 MHz ( /4 MHz. Fig. 5 shows a dashed rectangle within it three ed WCDMA carriers at DAC output can be located. The complex modulated IF signal is then translated to RF by an analog quadrature modulator. In a Quadrature Modulator that ollows the interpolating DAC two mixers are operated in quadrature (sine and cosine LO s are mixed with DAC complex signal output. The two mixer outputs are summed internally to perorm mathematical operations according to the phase relationships and signs o the requency components. In this manner, the quadrature modulator augments one sideband and diminishes the other while suppressing the LO. Two dierential Vto I converters connected to the baseband/if inputs provide the baseband/if modulation signals or the mixers. The outputs o the two mixers are summed together at an ampliier. The quadrature inputs are directly modulated by the LO signal to produce the RF output. In this coniguration Quadrature Modulator translates the DAC output to the requency band o MHz or TDSCDMA and 2 MHz 217 MHz or WCDMA. The input o the device accepts 1 V p.p dierential input signal centered on a commonmode voltage ranging rom.25 to.5 Volts while the output supports a dierentialended interace to a SAW. This device maintains less than 1 % quadrature phase imbalance such that 36 db sideband suppression can be achieved (with gain calibrated to < 1 %. IV. CONCLUSION This paper reviewed a chipset or lexible multistandard basestation transmitters or TDSCDMA and WCDMA. It was presented that semiconductor technologies are improving making wideband multicarrier transmitters or multistandard basestations possible. REFERENCES [1] A. Bidra, Highspeed wideband DACs permit multicarrier cellular basestations, Electronic Design, December 18, 2, pp [2] CWTS, Physical channels and transport channels onto physical channels TS C2 V3.. October [3] 3GPP TS rd Generation Partnership Project; Technical Speciication Group Radio Access Networks UTRA (BS FDD; Radio transmission and Reception, (Release 2.

4 32 bits baseband A D bits AD9777 cos sin F DAC/ 8,4,2 sin cos I DAC Q DAC AD8346 LO /9 F L O F L O PA & SAW Linearization Circuitry F CLK PLL clock Multiplier & clock divider Fig. 1 A multicarrier transmitter block diagram. AD6623 AD Mcps 3.84 Msps Msps Msps 1.92 Mcps 9.6 Msps 48 Msps Msps (a (b Fig. 2 TSP coniguration or three TDSCDMA carriers or two WCDMA carriers. db( CIC( db( Filter( db( Pass( 12 Composite Response to First CIC5 Null 5 stop dbstop start CIC Response Composite Response Desired Response stop (a (b Fig. 3. TSP requency response o a ed TDSCDMA carrier and WCDMA carrier Composite Response Desired Response Composite Response to First CIC5 Null stop dbstop

5 MHz Translated x8 Filter Output Signal Sin(x/x Fig. 4. Three ed TDSCDMA carriers at DAC output are located anywhere in the dashed rectangle MHz Translated x8 Filter Output Signal Sin(x/x Fig. 5. Two ed WCDMA carriers at DAC output are located anywhere in the dashed rectangle.