Pre-distortion. General Principles & Implementation in Xilinx FPGAs

Transcription

1 Pre-distortion General Principles & Implementation in Xilinx FPGAs

2 Issues in Transmitter Design 3G systems place much greater requirements on linearity and efficiency of RF transmission stage Linearity constrained by tight spectral mask requirement Power Amps (PA) need to keep operational level close to the compression point to achieve high-efficiency Multicode transmission requires more backoff leading to reduced efficiency Output transmission spectral output dependent on Non-linearities of RF stages Modulation method and coding

3 Causes of distortion shown in blue Generic Transmission System DAC Analog Quadrature Modulator p/2 cos(2pf 0 t) DAC Baseband Modulator I Q Digital Baseband to IF Modulator - Amplitude imbalance - Quadrature errors - Offsets - DAC response (sinx/x) DAC Analog IF to RF Transposition High Power Amplifier+Filter - Solid state, tube - Non linear distortions - Linear distortions - Offset - DAC response (sinx/x) - SAW filter response

4 Transmitter Design Goals Minimize cost of components Minimize the Output Backoff (OBO) while keeping acceptable signal characteristics OBO = Psat-Pm Maximize the signal dynamic range at the HPA input (IBO), but without clipping IBOc = Pisat-Pic (IBOc < 0 = signal clipping inside the HPA)

5 Rationale of Pre-distortion Dynamic adjustment & correction of non-linear and linear distortions Backing off the output signal level is usually not sufficient Amplitude compression may be required Eliminate out-of-band spectrum noise Most critical issue (non-linearity's increase its level) Correction bandwidth : 3Bu to 4Bu

6 Benefits of Pre-Distortion Complexity transferred to the digital domain Simpler overall design Allows the analog power amplifier to be a simple Class AB design Frees manufacturers from complex feed-forward amplifiers Greater efficiency as analog error amplifier distortion circuitry not required

7 Distortion Correction Non-linear correction Inverse transform of the High Power Amplifier (HPA) transfer characteristic up to the saturation point Power Amp - Transfer Function Inverse Transfer Function Distortion Corrected Transfer Function Linear correction Keep residual peak ripple amplitude within required limits Residual group delay distortion to be maintained within desired limits

8 Degradation Model for Analog Quadrature Modulation From Baseband Desired output distortion limits for acceptable transmitter quality Amplitude imbalance (g) : < db Quadrature error (j) : < DAC offsets (oi, oq) : < 0.1% - 0.5% of the peak signal amplitude DAC sinx/x response Baseband degradation model () φ () g cos 0 Y () n = M( X() n + O) = X n + O g sin φ 1 ( () )

9 Degradation Issues for Analog Transposition from a Digital IF Transposition from digital IF involves Digital quadrature modulation around IF Up-conversion to a second IF + filter for image rejection Up-conversion to the final RF carrier Issues DAC sinx/x response and offset Amplitude and group delay distortions of the image rejection filter

10 Different Non-Linear Distortion Models Memoryless Model (narrow bandwidth) Equation ya(t)=g(xa(t)) where G() is a memoryless non-linear function AM/AM and AM/PM curves Represented by a set of points (256 values usually enough) or a polynomial approximation Frequency Dependent Model (large bandwidth, IOT) The AM/AM and AM/PM curves appropriate over a narrow bandwidth Results may differ substantially for sine waves outside a bandwidth of a few MHz Use Volterra series expansion: y(n)=g(x(n),x(n-1),...,x(n-p)) Non-linear order of ~5 (M=2) and time order of 2 to 5 samples Estimation of Volterra kernels g2k+1() by mean square fitting between input and output measurements

11 Non-Linear Spectral Degradation Spectrum at amplifier input In-band degradation Spectrum at amplifier output Spectrum Shoulders (spectral spreading)

12 High Power Filter Degradation Model Objective of filter Elimination of spectrum images generated by the High Power Amplifier (HPA) intermodulation products Eliminate the linear distortions between the output of the amplifier and the antenna Cannot reduce non-linear shoulders in the vicinity of the signal spectrum Will unacceptably degrade performance within the spectrum

13 Requirements of the High Power Filter Minimal amplitude and phase distortions Implement as complex filter at baseband level The correction should provide Equivalent noise degradation < 0.1 db Residual peak amplitude ripple within required limits Residual group delay distortion within acceptable limits

14 Pre-Distortion Requirements Out-of-band radiated power meets specified spectrum mask Minimal in-band effects Adaptive system (temperature variations, ) Slow adaptation rate Non-linear pre-correction functions should work at upsampled rate : Limitation of out-of-band shoulders Up sampling factor Normally 2 to 4

15 Pre-Distortion Functions (Memoryless case) Functions performed by the pre-distortion algorithm for memoryless non-linear effects Amplitude compression Signal dependent OBO optimization Signal clipping + shoulder filtering or adapted coding scheme Linear correction Complex adaptive FIR filter Non-linear correction Inverse Transform Look Up Table AM /AM and AM /PM Curves inversion Adaptation algorithm Slow rate (software implementation)

16 General Architecture of Adaptive Pre-distortion Systems Baseband signal - Amplitude compression - Shoulder level control - Rate adaptation - Linear correction - Non-linear correction Pre-processing Pre-distortion RF analog chain RF output Input signals Measurement signals LO Correlation and coefficient updating Measurement chain - Time synchronization - AM/AM & AM/PM curves estimation - "LMS" estimation of linear distortions

17 Amplitude Compression Issues Loss of power efficiency if the amplifier must "pass" all the signal dynamic range CDMA ~12 db Control of the signal dynamic range at the amplifier input The signal may be clipped without noticeable degradation at the receiver side Clipping must not occur within the HPA or the precorrection filters Limits the shoulder level on output

18 Amplitude Compression Guidelines Amplitude compression must be implemented at the transmitter input Signal clipping + low-pass filter for shoulder removal Should operate at a higher rate than the signal useful bandwidth Limitation of in-band degradation (Shoulder Aliasing) Interpolation filter on input Need to compromise Working frequency versus filter complexity

19 Amplitude Compression Implementation - Example 1 Sampling frequency 2B u to 4B u Target peak level x I x Q Interpolation Filter Cordic Algorithm ρ θ Comparator Cordic Algorithm Shoulder Filter y I y Q Useful bandwidth B u

20 Amplitude Compression Implementation - Example 1 Rectangular to polar conversion with the Cordic algorithm (16 bits) Full Parallel : < 700 slices Serial (16 CLK cycles per output) : < 300 slices Polar to rectangular conversion with the Cordic algorithm (16 bits) Full Parallel : < 750 slices Serial (16 CLK cycles per output) : < 350 slices Shoulder filter Number of taps defined by the spectrum mask Usually at least 40 to 60 taps May have complex shape (multiple channel processing) Complex taps Distributed arithmetic structure well adapted for sampling rates between MHz

21 Amplitude Compression Example 2 x I Sampling frequency 2B u to 4B u y I x Q Interpolation Filter Delay + y Q Useful bandwidth B u I/Q Clipping signal Shoulder Filter Peak Power Target peak level Clipping Factor Soft clipping gain : - 0 if no clipping - 1 if full clipping

22 Amplitude Compression Example 2 Very efficient Uses Virtex-II and Virtex-II Pro embedded multipliers Computation of the clipping gain may be done with a RAM block Gain multiplication & shoulder filter may be integrated in the direct signal path As per Example 1 Shoulder filter requirements Same as Example 1

23 Pre-correction of Linear Distortions Input filter G i (f) i Look-Up Table Output filter G o (f) The input filter Gi(f) corrects the HPF linear distortions Inverse transform the HPF response within the signal bandwidth May operate at symbol rate Complex FIR filter, with adaptive coefficients Filter length usually 16 to 32 taps MAC implementation usually chosen Output filter Go(f) Must operate at a higher rate Should invert the RF modulation equivalent filter over the total correction bandwidth Not all implementations require this filter

24 Non-linear Memoryless x I x Q Sampling frequency 2B u to 4B u Cordic Algorithm Pre-correction r y r x f x LUT (RAM block) Df Example1: Polar Implementation - f y Cordic Algorithm y I y Q Inversion of the AM/AM & AM/PM amplifier curves Inversion of the amplifier curves up to the saturation point Implementation using a Look-Up Table RAMBlock Typically utilizes 1 double port RAM block I/Q to ρ/θ and ρ/θ to I/Q conversions on input/output using CORDIC algorithm

25 Non-linear Pre-correction Sampling frequency F s ~ 2B u to 4B u I/Q time multiplexed x I, x Q FPGA operating frequency : 4.F s y I x 2 I2 I +x 2 Q 1 Multiplier + 1 Accumulator LUT (BRAM) Df g Sine/cosine LUT (BRAM) 2 Accus + Reset + Capture y Q Example 2: I/Q Implementation y i and y q are symmetrical functions with of x i and x q Specification in the first quadrant is sufficient to define them completely Larger memory size than ρ/θ pre-correction : 12-bit input signal with 8-bit quantization of I/Q axis of amplifier curves 2x4b m-bit memory entries = 128 Kwords of 12 bits Memory reduction is possible 6-bit quantization of I/Q axis + bilinear interpolation on output = 8 K words of 12 bits

26 Estimation of Correction Coefficients Model the amplifier characteristic The overall dynamic scale needs to be calculated Normally 32K to 64K samples required at modulation rate to calculate coefficients Feedback structure of the return path RF to baseband demodulation via real time (FPGA) Analog quadrature demodulation must be avoided Digital demodulation needed DDS + complex multiplication + filter Calculate new coefficients in software (as low rate) Microblaze or Embedded PowerPC in Virtex-II Pro

27 Other Schemes Frequency dependent schemes Time dependencies are added to the Look-Up Table RAM RAM size can grow substantially Joint linear and non-linear correction Volterra Neural network based

28 Xilinx Value Proposition in Pre-Distortion Applications Xilinx FPGAs provide the ideal feature set required for pre-distortion functions XtremeDSP capability Extremely high-speed embedded multipliers Block memory for coefficient storage Flexibility and Reconfigurability Adapt designs during development and after deployment Soft and embedded processors New coefficient calculation and control of the pre-distortion filter carried out using an on-chip processor solution

29 Xilinx Pre-Distortion System Solution Platform FPGA Antenna From Channel Combiner I Q Amplitude Compression Pre-Distortion Function Linear Filter Non-Linear Correction DAC DAC RF Transmitter Power Amp Tx Bandpass Filter Dual Port Me mory Filter Coefficients & Non-Linear Transform Table System Control Bus MicroBlaze or PowerPC Buffer Me mory IF to Baseband Digital Down Converter ADC RF Receiver Xilinx Memory CPU Non-Xilinx Mixed Signal Embedded

30 Xilinx Software and IP Solutions Xilinx has a comprehensive range of IP and software to ensure speedy pre-distortion algorithm and filter development System Generator Allows algorithmic development and targeting to silicon in a high-level DSP development toolset Mathworks & Simulink Coregen Used to generate the desired filter in a simple and easy-to-use GUI based tool IP Many blocks of IP available from Xilinx and our AllianceCore partners

31 IP Center Keep up to date with the latest cores and reference designs available from Xilinx and our AllianceCore partners

32 Xilinx CORE Generator List of available IP from or Fully Parameterizable

33 Reed Solomon FIR Filter Generator Wireless IP Currently Available (Distributed Arithmetic or MAC Based) Polyphase decimator Polyphase interpolator Halfband filters Hilbert transform FFTs Direct Digital Synthesizer (NCO) Includes quadrature output CORDIC Many more under development Viterbi Encoder/Decoder Turbo Convolutional Encoder/Decoder 3GPP Interleaver/ De-interleaver Digital Down Converter PN Sequence Generator Gold code support Correlators High Speed Viterbi (>150MHz) Turbo Product Codecs

34 CORDIC CORDIC Engine A n-bits Input Stage Shift Add-Sub Stages Output Stage Output Clock Control Signals Features Vector Rotation (Polar to Rectangular) Vector Translation (Rectangular to Polar) Trigonometric, Hyperbolic and Square Root equations Serial or Parallel implementation Deliverables Design Source Behavioral Model Instantiation Code Test Bench Core Source Smart-IP Technology Netlist VHDL and Verilog VHDL and Verilog No CORE Generator, IP Center Applications Math Functions used in Beam Forming, Smart Antennas etc. Device Family Size Performance Customization Input and Output width Compensation scaling Rounding Phase Format Spartan-II,Virtex/-E/-II/PRO 200 slices, 16b Square root 164 MHz, xc2v50-5

35 System Generator for DSP Visual data flow paradigm Polymorphic block libraries Bit and cycle true modeling Seamlessly integrated with Simulink and MATLAB Test bench and data analysis Automatic code generation Synthesizable VHDL IP cores HDL test bench Project and constraint files

36 Summary The use of pre-distortion offers equipment manufacturers a way of rapidly reducing the overall cost of their systems Cut costs in the complex analog domain Use relatively cheap digital technology to compensate for poor analog performance Xilinx FPGAs have all the features needed to implement complex pre-distortion functions

37 Questions?