Outline. Background of Analog Functional Testing. Phase Delay in Multiplier/Accumulator (MAC)-based ORA

Transcription

1 Phase Delay Measurement and Calibration in Built-In Analog Functional Testing Jie Qin, Charles Stroud, and Foster Dai Dept. of Electrical & Computer Engineering Auburn University

2 Outline Background of Analog Functional Testing Built-In Self-Test Architecture Phase Delay in Multiplier/Accumulator (MAC)-based ORA Experimental Results Conclusions 3/5/07 IEEE Southeastern Symp. on System Theory 2

3 Background - Frequency Response Measurement Almost the most popular and important analog functional measurement Can be performed through one-tone test Generate a tone to stimulate the device under test (DUT) Monitor the output and perform spectrum analysis Sweep the tone over the whole interested band Magnitude Amplifier Transfer Function Test tones generated using DDS Frequency 3/5/07 IEEE Southeastern Symp. on System Theory 3

4 Background Nonlinearity Measurement Third-order intercept point (IP3) is one of the most important nonlinearity measures Can be measured through a two-tone tone test f 1 f 2 Generate two tones with close frequency spacing to stimulate the device under test (DUT) Monitor the output of the DUT and perform spectrum analysis 3 4 ω1 2 ω1 2 2 ω α1a f 1 f 2 f 2 - f 1 f 1 +f 2 2f 1 - f 2 2f 2 - f 1 2f 1 2f 2 α 1 ω A P α3a 2 α3a 2ω ω f 1 3f 2 1 Freq 7 8 freq freq 3/5/07 IEEE Southeastern Symp. on System Theory 4

5 Background Noise Measurement Noise Figure (NF) is a measure of the noise generated by a device itself Defined as the ratio of the input signal-to to-noise ratio (SNR( in ) to output SNR SNR out Can be measured through a one-tone SNR measurement Generate a tone to activate the DUT Monitor the output of the DUT at the whole interested band The noise level can be obtained with the signal level as a reference point 3/5/07 IEEE Southeastern Symp. on System Theory 5

6 Background Design Goals for BIST Goals for mixed-signal BIST Extract the frequency spectrum information from DUT response for Frequency Response Nonlinearity Measurement Noise Measurement Implementation using simple circuitry Small area penalty Minimal performance penalty to analog circuitry. Conventional way to perform spectrum analysis is FFT High area penalty High power consumption 3/5/07 IEEE Southeastern Symp. on System Theory 6

7 Background Basic Ideas of BIST Proposed BIST approach based Direct Digital Synthesizer (DDS)-based TPG Can generate various required waveforms Multiplier/accumulator (MAC)-based ORA Used for spectrum analysis Implemented in a much simpler, cheaper and more flexible circuit compared with the FFT-based ORA Everything is for simpler circuitry Only measure the spectrum at one frequency at a time Sweep the whole interested band to capture the complete spectrum 3/5/07 IEEE Southeastern Symp. on System Theory 7

8 Digital System Inputs Digital System Outputs BIST for Mixed-Signal Systems Digital circuitry tests analog circuitry BIST Start BIST Done Results Minimize impact to analog circuitry Use existing DAC/ADC in mixed-signal system System Function Mux DAC TPG ORA Test Control Digital Circuitry System ADC Function Analog Circuit Analog Circuitry Analog Circuit Analog MUX Analog System Outputs Analog System Inputs 3/5/07 IEEE Southeastern Symp. on System Theory 8

9 Built-In Self-Test Architecture Test Controller DAC Amp f 1, θ 1 NCO1 Sin(2πf 1 nt clk +θ 1 ) f 2, θ 2 NCO2 Sin(2πf 2 nt clk +θ 2 ) Test Pattern Generator (TPG) MUX2 MUX1 f 1 (nt clk ) ADC MUX4 MUL1 f(nt clk ) MUX3 Accm1 DC 1 DUT Output Response Analyzer (ORA) f 3, θ 3 Sin(2πf 3 nt clk +θ 3 ) NCO3 f 2 (nt clk ) MUL2 Accm2 DC 2 3/5/07 IEEE Southeastern Symp. on System Theory 9

10 MAC-based ORA DC 1 and DC 2 accumulator values can be described as DC = f( nt ) cos( ωnt ) DC = f ( nt ) sin( ωnt ) 2 1 n n clk clk Signal f(nt clk ) Fourier Transform F(ω) can be expressed through DC 1 and DC 2 ( ) ( ) j ω ntclk j F ω = f nt e = DC( ω) + j DC ( ω) = A( ω) e n clk clk clk 1 2 Magnitude response A(ω) and phase delay ΔΦ(ω) A(ω) is the more important ΔΦ(ω) still has to be considered for accurate A(ω) φ( ω) 3/5/07 IEEE Southeastern Symp. on System Theory 10

11 Phase Delay in MAC-based ORA Phase delay measured by: φω ( ) = tg DC ( ω) DC ( ω) For on-chip test, full arctan look-up table (LUT) in the first quadrant can be used to calculate ΔΦ(ω) Absolute phase offset ΔΦ o (ω) can be calculated according to: 1 DC2 ( ω) tg DC1( ω) DC2( ω) DC1 ( ω) φo ( ω) = 1 DC1 ( ω) tg DC1( ω) DC2( ω) DC2 ( ω) 3/5/07 IEEE Southeastern Symp. on System Theory 11

12 Phase Delay in MAC-based ORA (cont.) Phase delay can be determined through absolute phase offset Φ o (ω) according to following table: DC 1 2 >0 φ(ω) = φ ο (ω) DC 1 2 <0 φ(ω) =360 φ ο (ω) DC 1 2 >0 φ(ω) =180 φ ο (ω) DC 1 2 <0 φ(ω) =180 + φ ο (ω) DC 1 DC 2 DC 1 DC 2 φ(ω) =90 φ ο (ω) φ(ω) =270 + φ ο (ω) φ(ω) =90 + φ ο (ω) φ(ω) =270 φ ο (ω) The arctan LUT can be reduced by half since value range of ΔΦ o (ω) varies from 0 0 to 45 When DC 2 /DC 1 is very small, arctan(dc 2 /DC 1 ) can be approximated by DC 2 /DC 1 Size of arctan LUT can be compressed 3/5/07 IEEE Southeastern Symp. on System Theory 12

13 Phase Delay in MAC-based ORA (cont.) Once phase delay is obtained, magnitude response A(ω) can be calculated 3 different ways: Approach #1 A F e f nt nt j φω ( ) ( ω) = ( ω) = ( clk ) cos( ω clk φ( ω)) n Approach #2 Approach #3 DC1 DC 2 A( ω) = = cos φ ( ω) sin φ ( ω) 2 1 A ( ω ) = DC + DC 2 2 3/5/07 IEEE Southeastern Symp. on System Theory 13

14 Phase Delay in MAC-based ORA (cont.) Pros and cons of 3 approaches Approach # 1 # 2 # 3 Hardware overhead low higher highest Test time long short short Constraints cannot be used for SNR measurement none none Propagation error yes yes none 3/5/07 IEEE Southeastern Symp. on System Theory 14

15 Experimental Results I Phase delay introduced by digital portion of the BIST circuitry Bug in original implementation Actual measurements with BIST System Function TPG DAC ADC ORA to/from DUT phase error due to the delay in TPG phase error with delay removed 3/5/07 IEEE Southeastern Symp. on System Theory 15

16 Experimental Results II Phase delay introduced by DAC/ADC pair Phase delay accounts for error in [18] F. Dai, C. Stroud, and D. Yang, Automatic Linearity and Frequency Response Tests with Built-in in Pattern Generator and Analyzer, IEEE Trans. on VLSI Systems., vol. 14, no. 6, pp , 572, System Function TPG DAC ADC to/from DUT ORA 3/5/07 IEEE Southeastern Symp. on System Theory 16

17 Experimental Result III FPGA resources used by the MAC-based ORA Increases linearly with M (# accumulator bits) Increases almost exponentially with N (# multiplier bits) Multipliers included in slice count for MAC # of accumulator bits, M Number of Slices for MAC # of multiplier bits, N Number of Slices for FFT Type # of slices # of bit multipliers Pipelined Burst I/O Minimum Resources /5/07 IEEE Southeastern Symp. on System Theory 17

18 Summary and Conclusions Phase delay is important to implementation and accuracy of MAC-based ORA Compared with FFT-based approaches MAC-based ORA can be realized using much more flexible and simpler BIST circuitry with less area penalty MAC frequency resolution can be easily tuned with step size of sweeping frequency MAC can measure spectrum information of interest at several frequency points, or in a narrow bandwidth 3/5/07 IEEE Southeastern Symp. on System Theory 18