Outline. Motivation. Analog Functional Testing in Mixed-Signal Systems. Motivation and Background. Built-In Self-Test Architecture

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1 Aalog Fuctioal Testig i Mixed-Sigal s Jie Qi Dept. of Electrical & Computer Egieerig Aubur Uiversity Co-Advisors: Charles Stroud ad Foster Dai Outlie Motivatio ad Backgroud Built-I Self-Test Architecture Desig of Device Uder Test (DUT) Experimetal Results Coclusios ad Future Research Motivatio Aalog circuits are typically measured maually Cost ad time iefficiet It is ot easy to measure aalog circuits i systems Lack of accessibility Performace variatio caused by test equipmet Mixed-Sigal Built-I Self-Test (BIST) is promisig Automated testig sequece I-system measuremets with available resources Calibratio ad adaptive cotrol Frequecy Respose Measuremet Almost the most popular ad importat aalog fuctioal measuremet Ca be performed through sigle toe test Geerate a toe to stimulate the device uder test (DUT) Moitor the output ad perform spectrum aalysis Sweep the toe over the whole iterested bad Magitude Amplifier Trasfer Fuctio Test toes geerated usig DDS Frequecy 3 4

2 Noliearity Measuremet Third-order itercept poit (IP3) is oe of the most importat oliearity measures Ca be measured through a two-toe toe test Geerate two toes with close frequecy spacig to stimulate the device uder test (DUT) Moitor the output of the DUT ad perform spectrum aalysis f 1 f f f 1 f 1 f f f 1 f 1 + f f 1 f 3f 1 3f Noise Measuremet Noise Figure (NF) is a measure of the oise geerated by a device itself Defied as the ratio of the iput sigal-to to-oise ratio (SNR( i ) to output SNR out Ca be measured through a oe-toe SNR measuremet Geerate a toe to active the DUT Moitor the output of the DUT at the whole iterested bad The oise level ca be obtaied with the sigal level as a referece poit 5 6 Requiremets for BIST Goals for mixed-sigal BIST Extract the frequecy spectrum iformatio from DUT 1 respose for Frequecy Respose Liearity Measuremet Noise Measuremet Implemetatio usig simple circuitry Small area pealty Miimal performace pealty to aalog circuitry. Covetioal way to obtai frequecy spectrum is FFT High area pealty High power cosumptio Proposed BIST Proposed BIST approach uses DDS 1 -based Test Patter Geerator (TPG) Ca geerate various stimuli required for Frequecy Respose Liearity Measuremet Noise Measuremet MAC -based Output Respose Aalyzer (ORA) Ca be realized i a much simpler, cheaper ad more flexible circuit compared with the FFT-based ORA 1. DUT: Device Uder Test. FFT: Fast Fourier Trasform 7 1. DDS: Direct Digital Sythesizer. MAC: Multiplier/ACcumulator 8

3 DDS-based TPG NCO 1 geerates a digitized siusoidal waveform Frequecy word f w ad iitial phase word θ w Phase trucatio for smaller LUT size TPG cosists of 3 NCOs Required for test stimuli ad ORA θ w f w f =1/T Phase Accumulator Z -1 Phase Trucatio Basic Structure of NCO p si/cos LUT ' fw f f = si(πft +θ) MAC-based ORA ORA performs spectral aalysis with oly two MACs Oe MAC for i-phase while the other for out-of of-phase 1 = f ( T ) cos( ω T ) = f ( T ) si( ω T ) Magitude respose A ) ad phase delay ΔΦ A ( ω ) = 1 ( ω) 1 + φ( ω) = tg 1( ω) Aalysis is doe at oe frequecy at a time Sweep the whole iterested f(t ) bad to capture the complete Output Respose spectrum Aalyzer (ORA) Much more efficiet i terms of hardware resources cos(ωt ) MUL1 Accm1 1 compared with FFT-based ORA si(ωt ) MUL Accm 1. NCO: Numerically Cotrolled Oscillator. LUT: Look-Up Table 9 1 Phase Delay i MAC-based ORA To build arcta LUT to calculate ΔΦ for o-chip tests LUT ca be reduced to value rage of ΔΦ o ( to 45 ) ( ω) tg 1( ω) ( ω) 1( ω) >; 1 > φ = φ ο φ =9 φ ο φo ( ω) = 1 1( ω) >; 1 < φ =36 φ ο φ =7 + φ ο tg 1( ω) ( ω) 1 ( ω) <; > φ =18 φ ο φ =9 + φ ο <; 1 < φ =18 + φ ο φ =7 φ ο LUT ca be further compressed Whe /1 is very small, arcta(/1) ca be approximated by /1 Taylor Series Expasio 11 Magitude Respose i MAC-based ORA Oce phase delay is obtaied, A ca be calculated 3 differet ways: j φ ( ω) Approach #1 A( ω) = F( ω) e = f ( T ) cos( ωt φ( ω)) Approach # Approach #3 1 1 A( ω) = = cos φ ( ω) si φ ( ω) 1 A ( ω) = + = f ( T ) cos( ωt ) Approach # 1 # # 3 Hardware overhead Test time Costraits Propagatio error low log caot be used for oise measuremet yes Pros ad Cos of 3 approaches high short oe yes high short oe oe 1

4 f 1, θ 1 f, θ Built-I Self-Test Architecture NCO1 NCO Si(πf 1 T +θ 1 ) Si(πf T +θ ) Test Patter Geerator (TPG) f 3, θ 3 Si(πf 3 T +θ 3 ) NCO3 Test Cotroller MUX MUX1 f 1 (T ) f (T ) DAC MUX4 MUL1 A f(t ) MUL Number ad locatio of MUXs i aalog system determies accuracy of fuctioal measuremets Amp MUX3 Accm1 Accm 1 DUT Output Respose Aalyzer (ORA) 13 Digital Iputs BIST Start BIST Doe Result Digital Outputs BIST for Mixed-Sigal s Digital circuitry tests aalog circuitry Miimize impact to aalog circuitry Use existig DAC/A i mixed-sigal system Fuctio Mux DAC TPG Aalog Circuit Test Aalog Cotrol MUX Digital Aalog ORA Circuitry Circuitry Aalog A Fuctio Circuit Aalog Outputs Aalog Iputs 14 Test ad Evaluatio of BIST Practical Issues of a BIST implemetatio Quality of test stimuli Wide operatio rage BIST itself eed to be evaluated A operatioal amplifier with tuable performace was fabricated ad served as a DUT Implemeted BIST could be evaluated over its performace variatio rage BIST results ca be compared with Simulatio results Measuremet results from test equipmet Basic Structure of Op-Amp Iput differetial pair: M1 ad M Secod Stage Commo-Emitter Amplifier: M5 Output Stage: M6 ad Q1 Compesatio Capacitor: C 16

5 Frequecy Respose Tuability The GBW 1 of the op-amp is bias depedet The first two stages (M1,( M ad M5) g m Gai (db) The output stage (M6( ad Q1) GB g I D, M 8 C C V C 1 m = = R + E GB ωt R R E B The badwidth could be tued with its bias curret T Liearity Tuability The liearity of the op-amp is bias depedet The IM3 1 product of a BJT differetial pair is It works for CMOS differetial pair as well The liearity could be tued with bias curret Power (dbm) Power (dbm) Power (dbm) IM I 3 Q b 3 b b 1 b =1 b 3 b b 1 b =1 b 3 b b 1 b =1 b 3 b b 1 b = k 1k 1k 1M 1M 1M Frequecy (Hz) Simulated Frequecy Respose Tuability 1. GBW: uit-gai badwidth Frequecy (khz) Frequecy (khz) Frequecy (khz) (a) Curret switch b 3 b b 1 b =1. (b) Curret switch b 3 b b 1 b =1. (c) Curret switch b 3 b b 1 b =1. Simulated Liearity Tuability 1. IM3: 3 rd -order iter-modulatio product 18. BJT: bipolar-juctio trasistor Noise Figure (NF) Tuability The NF of the op-amp is determied by early stage The oise figure of a cascaded system 1 1 F = F + 1 ( F 1) ( F3 1) G + G G 1 1 Resistor at the iputs could be used to tue oise figure as thermal oise source V = 4kTRB ref Extra Block for Tuability Programmable curret source for the op-amp Cotrolled by curret switch I = ( 8b + 4b + b + b ) I 3 1 BIAS Simulated NF Tuability 19 Programmable resistor bak for the op-amp Cotrolled by resistor switch R1 R R3 R4, b = b1 b b3 b4 R =, b =1

6 Overall Desig of DUT A built-i i shift register to accept commad word from outside To cotrol the tuability of the DUT To decrease the umber of required pis effectively Three pis of CLK, EN ad DIN DUT was fabricated with.5um BICOMS techology ad occupied a area of mm Aalog MUX DAC A Implemeted BIST circuitry BIST Implemetatio v1 PC Iterface FPGA PC Iterface FPGA A Two implemetatios with same architecture differet resolutio ad speed DAC DAC Buffer DUT BIST Implemetatio v A Buffer Layout Diagram Die Photo 1 DDS-geerated Test Toes ORA with Fiite Resolutio SNFR displayed =8dBc/Hz SNFR displayed =9dBc/Hz SNFR actual =1dBc/Hz SNFR actual =11dBc/Hz SNFR actual =11dBc/Hz SNFR actual =89dBc/Hz Toe from DDS-based TPG (f s =1.5MHz, Word Legth = 8bit) Toe from Agilet 335A waveform geerator Actual sigal-to to-oise floor ratio SNFRactual dbc SNFR Hz = displayed 1log 1( RBW ) Noise Floor of DDS-geerated Toes is maily cotributed by the quatizatio oise from fiite word legth Calculated SNR from measured SNFR over [, fs/] is aroud 3dB Simulated SNR i time domai is 36.dB 3 Spectral aalysis doe by ideal ORA Spectral aalysis doe by ORA with fiite resolutio ORA with fiite resolutio also itroduces calculatio oise Simulatio result shows aroud 1dB degradatio. 4

7 Dyamic Rage of BIST Circtuitry SNFR actual =6dBc/Hz Frequecy Respose Measuremet BIST results match the other results Magitude Respose matches the maually measuremet FFT fuctio provided by the oscilloscope (fairly accurate) Phase Respose matches the simulatio results Time lag read from the oscilloscope (very rough estimatio) Magitude Respose (db) Simulatio Results with Spectre Simulator Measured Results with Exteral Equipmet Measured Results with BIST circuitry -5 1k 1k 1k 1M 1M Frequecy (Hz) Magitude Respose (db) Simulatio Results with Spectre Simulator Measured Results with Exteral Equipmet Measured Results with BIST circuitry -5 1k 1k 1k 1M 1M Frequecy (Hz) Spectral aalysis doe by actual BIST circtuitry The actual measuremet doe by BIST is aroud 6dBc/Hz Maily limited by switchig oise from the digital circuitry 5 Phase Respose (degree) 1 5 Simulatio Results with Spectre Simulator Measured Results with Exteral Equipmet Measured Results with BIST circuitry 1k 1k 1k 1M 1M Frequecy (Hz) Phase Respose (degree) 1 5 Simulatio Results with Spectre Simulator Measured Results with Exteral Equipmet Measured Results with BIST circuitry -5 1k 1k 1k 1M 1M Frequecy (Hz) (a) Curret switch b 3 b b 1 b =1. (b) Curret switch b 3 b b 1 b =1. 6 Gai (db) Measured Results with Exteral Equipmet Simulatio Results with Spectre Simulator Liearity Measuremet P1dB 1 is measured for liearity performace Easier to measure with test equipmets Measuremet results with exteral equipmet match simulated results Maximum differece of 1dB for 4 cofiguratios BIST results do t t match A desig mistake of output buffer (without eough curret drivability) ility) Limited voltage swig also limits the effective dyamic rage of the BIST circuitry Iput Power (dbm) Gai (db) Measured Results with Exteral Equipmet Simulatio Results with Spectre Simulator Iput Power (dbm) (a) Curret switch b 3 b b 1 b =1. (b) Curret switch b 3 b b 1 b =1. 1. P1dB: 1dB compressio poit 7 Resource Usage of Proposed BIST Compariso betwee the proposed BIST ad a FFT processor Five times more slice umber Block ram ad 18x18 multiplier as a plus Resource used by proposed BIST Proposed BIST circuitry is much simpler ad cheaper, ad ca TYPE # OF # OF BLOCK # OF TRANSFORM SLICES RAM MULT FREQUENCY Pipelied khz Burst I/O khz Miimum Resources khz Resource used by FFT processor FPGA USED BY TOTAL % ATTRIBUTE BIST IN FPGA USAGE # of slices % # of flip-flops 63 1,536 17% # of 4-iput LUTs 656 1,536 4% Maximum BIST Clock Frequecy = 48.5 MHz also achieve more flexibility tha FFT-based approach Able to tue the step size, frequecy rage easily 8

8 Summary ad Coclusios The proposed BIST circuitry is able to perform a suite of aalog fuctioal tests Accurate frequecy respose measuremet Liearity ad oise measuremet is somewhat costraied by the effective dyamic rage of the proposed BIST system The proposed BIST circuitry is efficiet i terms of area, power cosumptio, ad cost Future work It is hard to apply the curret architecture to RF system directly due to various practical issues Goals Simple aalog modules Work i RFIC eviromet 9 Publicatio List [1]Jie Qi, Charles Stroud, Foster Dai, Phase Delay i MAC- based Aalog Fuctioal Testig i Mixed-Sigal s, Proc. IEEE North Atlatic Test Workshop, 6 []Jie Qi, Charles Stroud, Foster Dai, Phase Delay Measuremet ad Calibratio i Built-I Aalog Fuctioal Testig, Proc. IEEE Southeaster Symp.. o Theory,, 7 [3]Jie Qi, Charles Stroud, Foster Dai, Noise Figure Measuremet Usig Mixed-Sigal BIST, Proc. IEEE Iteratioal Symp.. o Circuits ad s, 7 [4]Jie Qi, Charles Stroud, Foster Dai, FPGA-Based Aalog Fuctioal Measuremets for Adaptive Cotrol i Mixed- Sigal s, IEEE Tras. o Idustrial Electroics, Vol. 54, No. 4, 7 [5]Jie Qi, Charles Stroud, Foster Dai, Test ad Verificatio of Mixed-Sigal BIST Approaches, Submitted to Iteratioal Test Coferece, 8 3