Linearity Enhancement Algorithms for I-Q Signal Generation

Transcription

1 B6-1 10:15-10:45 Nov. 6, 2015 (Fri) 1 /55 Invited paper Linearity Enhancement Algorithms for I-Q Signal Generation - DWA and Self-Calibration Techniques - M. Murakami H. Kobayashi S. N. B. Mohyar T. Miki O. Kobayashi Gunma University STARC

2 Outline 2 /55 Research Background Complex Multi-BP ΔΣ DA Modulator DWA Algorithm - Conventional Algorithm - Proposed Algorithm Self-Calibration Conclusion

3 Outline 3 /55 Research Background Complex Multi-BP ΔΣ DA Modulator DWA Algorithm - Conventional Algorithm - Proposed Algorithm Self-Calibration Conclusion

4 Necessity of I,Q signal 4 /55 RF analog front-end of Receiver IC RF cos(ωlot) In-phase mixer ADC DSP -sin(ωlot) Quadrature-phase Need testing!

5 Research Goal 5 /55 Demand for low cost testing of communication IC High quality I,Q test signal generation for receiver IC with Low cost

6 I,Q Signal Generation 6 /55 1 Analog centric bit DSP 2 Digital centric(1) 1 3 bit DSP 3 Digital centric(2) 1 3 bit DSP

7 1 Analog Centric 7 / bit DSP Nyquist DAC Large Nyquist-rate DACs and Steep analog filters

8 Delta Sigma DA Converter 8 /55 Digital centric 2 2 real-bp ΔΣ DACs signal noise signal noise 1 3 bit DAC Delta Sigma Digital modulator 1~3 bit DAC Oversampling Relaxes analog filters

9 Delta Sigma DA Converter 9 /55 Digital centric 2 2 real-bp ΔΣ DACs signal noise signal noise 1 3 bit DAC Unused band Signal band Delta Sigma Digital modulator 1~3 bit DAC Oversampling Relaxes analog filters

10 Delta Sigma DA Converter 10 /55 Real vs Complex 2 2 real-bp ΔΣ DACs signal noise signal noise 3 1 complex-bp ΔΣ DAC 1 3 bit DAC Unused band noise Signal band signal 1 3 bit DAC Signal band

11 11 /55 Complex Delta Sigma is Superior Real vs Complex 2 2 real-bp ΔΣ DACs 3 1 complex-bp ΔΣ DAC 1 3 bit DAC signal noise Wasted noise Get signal noise signal 1 3 bit DAC Wide band, High SNR

12 12 /55 Complex Delta Sigma is Superior SNDR Signal to Noise and Distortion Ratio Real signal noise signal noise Complex noise signal 15dB better SNDR for complex BP ΔΣ modulator High quality I,Q signals

13 Complex Signal 13 /55 Real signal Iin, Qin Complex signal Iin + jqin j = -1 Complex signal processing is NOT complex. (K.Martin)

14 I,Q Signal Generation 14 /55 DSP, DAC + ΔΣ + Complex = Low cost, high quality signal! Digital rich!

15 Outline 15 /55 Research Background Complex Multi-BP ΔΣ DA Modulator DWA Algorithm - Conventional Algorithm - Proposed Algorithm Self-Calibration Conclusion

16 16 /55 Principle of Complex BP Noise Shape Complex resonator Quantization noises Power Signal Transfer Function = 1 ω Noise Transfer Function = 0

17 17 /55 Principle of Complex BP Noise Shape Complex resonator Quantization noises Power Signal Transfer Function = 1 1 ω 0 Noise Transfer Function = 0

18 18 /55 2nd-order Complex Multi-BP ΔΣ DAC Output spectrum Single-band Multi-band

19 19 /55 Necessity of Multi-Tone Signal Linearity testing of Mixer Up/Down converter Radio communication system, etc. Multi-tone signal Noise Power Ratio (NPR) Input Output DUT NPR Distortion by DUT ω DUT:Device Under Test ω

20 20 /55 Necessity of Multi-tone Signal Linearity testing of Mixer Up/Down Converter Radio communication system etc... Need! Multi-tone signal Noise Power Ratio (NPR) Input Output DUT NPR Distortion by DUT ω DUT:Device Under Test ω

21 Power Complex Resonator 21 /55 Output spectrum pole pole pole pole pole -0.5 ωin / ωs 0.5 Single-band -0.5 ωin / ωs 0.5 Multi-band

22 Power Complex Resonator 22 /55 Asymmetric Asymmetric Output spectrum pole pole pole pole pole -0.5 ωin / ωs 0.5 Single-band -0.5 ωin / ωs 0.5 Multi-band

23 Outline 23 /55 Research Background Complex Multi-BP ΔΣ DA Modulator DWA Algorithm - Conventional Algorithm - Proposed Algorithm Self-Calibration DWA: Data Weighted Averaging Conclusion One of Data Element Matching (DEM) algorithms

24 Multi-bit DA modulator 24 /55 Multi-bit DA modulator(2~3bit) Quantization noise reduction Linearity degradation 1bit Multi-bit Down Error

25 Multi-bit DAC 25 /55 Normal unary DAC

26 Multi-bit DAC 26 /55 Accumulate mismatch of particular cell Normal unary DAC

27 Multi-bit DAC + DWA 27 /55 Memorize next cell selection start point DWA* DAC *Data Weighted Averaging Select the element with DSP algorithm

28 DWA = ΔΣ 28 /55 Integration Non-Linearity δ Differentiation Input DAC Output z - 1 z - 1 δ affected by only Differentiation δ Can t be realized directly Input Pointer DAC Output Memorize next cell selection start point Equivalent circuit for implementation

29 Effect of DWA 29 /55 Normal DWA

30 Signal Band 30 /55 REAL zero point at DC LowPass High Pass Asymmetry COMPLEX with respect to ω=0. ωin / ωs

31 Type of DWA 31 / DWA = DSP algorithm

32 Outline 32 /55 Research Background Complex Multi-BP ΔΣ DA Modulator DWA Algorithm - Conventional Algorithm - Proposed Algorithm Self-Calibration Conclusion

33 33 /55 Equivalent Circuit of Complex DWA Complex resonance δi Complex notch Iin DAC1 + Iout z - N z - N z - N δq z - N + Qin DAC2 Qout δi, δq affected by only complex notch DAC input can be Can t be realized directly

34 34 /55 Equivalent Circuit Implementation Iin Iout Qin Qout Attach pointers Exchange upper-path and lower-path every N clock Complex DWA is realized.

35 DAC Input 35 /55 Complex Multi-Bandpass DWA Algorithm N = 4(four zero points) DAC1 (LP operation) DAC2 (HP operation) Iin Qin I0 I1 I2 I3 I4 I5 I6 I Iin Qin I0 I1 I2 I3 I4 I5 I6 I

36 36 /55 Simulation Result ~Ideal Linear DAC~

37 37 /55 Simulation Result ~Actual Non-Linear DAC~ δi δq Notches filled with noise

38 Simulation Result 38 /55 ~Actual Non-Linear DAC + DWA~ δi DWA δq Notches filled with noise

39 Simulation Result 39 /55 ~Actual Non-Linear DAC + DWA~ δi DWA DWA δq DWA Notches filled with noise Steep Notches

40 Simulation Result 40 /55 ~Actual Non-Linear DAC + DWA~ N (number of notches) N increases SNDR decreases

41 Outline 41 /55 Research Background Complex Multi-BP ΔΣ DA Modulator DWA Algorithm - Conventional Algorithm - Proposed Algorithm Self-Calibration Conclusion

42 Look Up Table 42 /55 Example Cat Age Human Age Memory LUT 3 33 address data

43 Look Up Table 43 /55 Example Cat Age Human Age Memory LUT 7 55 address data

44 DAC Nonlinearity Measurement Results are stored in LUTs 44 /55 ΔΣADC inside SoC

45 ΔΣ DAC with Self-Calibration of DAC1, DAC2 CLK(1) 45 /55

46 ΔΣ DAC with Self-Calibration of DAC1, DAC2 46 /55 CLK(2)

47 ΔΣ DAC with Self-Calibration of DAC1, DAC2 47 /55 CLK(3)

48 48 /55 Simulation Conditions : DAC Unit Cell Variation Standard deviation 1.0% Nonlinearity DAC1 DAC2 Nonlinearity Current Amount of Each Unit Cell DAC 1 DAC 2 DAC1 Total Current :7.98 DAC2 Total Current: I0 I1 I2 I3 I4 I5 I6 I7

49 Simulation Results 49 /55 Simulation Conditions δ=1.0% δ=0.9% δ=0.7% δ=0.5% δ=0.3% δ=0.1%

50 Simulation Results 50 /55 Simulation Conditions δ=1.0% δ=0.9% δ=0.7% δ=0.5% δ=0.3% δ=0.1% When DAC nonlinearity is large, self-calibration (3) is more effective than DWA(2).

51 Pros and Cons of Self-Calibration 51 /55 Pros DWA Self-Calibration Cons DAC Nonlinearity Noise Shaping Specific Bands All Bands Better SNDR than DWA is obtained. DAC nonlinearity measurement withδσ ADC inside SoC is required. Digital modulator circuit size becomes large (due to 2 LUTs and fixed-point (instead of integer) arithmetics.

52 52 /55 Further Applications High frequency signal generation Y = cos ω in t cos ω c t sin ω in t sin ω c t = cos(ω in +ω c )t. Sine wave generation with fine time shift Image rejection ratio measurement

53 Outline 53 /55 Research Background Complex Multi-BP ΔΣ DA Modulator DWA Algorithm - Conventional Algorithm - Proposed Algorithm Self-Calibration Conclusion

54 Conclusion 54 /55 I,Q signal generation with digital centric for communication IC. Complex multi-bp ΔΣ DAC Multi-bit DAC Relaxes the analog filter requirements Degrades system linearity DWA algorithm Self-calibration algorithm Low cost, high quality I,Q signal generation.

55 Final Statement 55 /55 Signal processing algorithms can enhance analog circuit performance. Thank you for your kind attention 謝謝