Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator

Transcription

1 DOI 0.007/s Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator Kazuyuki Wakabayashi Keisuke Kato Takafumi Yamada Osamu Kobayashi Haruo Kobayashi Fumitaka Abe Kiichi Niitsu Received: 9 October 20 / Accepted: 2 March 202 Springer Science+Business Media, LLC 202 Abstract This paper describes algorithms for generating a low-distortion single-tone signal, for testing ADCs, using an arbitrary waveform generator (AWG). The AWG consists of DSP (or waveform memory) and DAC, and the nonlinearity of the DAC generates distortion components. We propose here to use DSP algorithms to precompensate for the distortion. The DSP part of the AWG can interleave multiple signals with the same frequency but different phases at the input to the DAC, in order to precompensate for distortion caused by DAC nonlinearity. Theoretical analysis, simulation, and experimental results all demonstrate the effectiveness of this approach. Keywords ADC testing Arbitrary waveform generator Digital pre-distortion Sinusoidal signal Distortion shaping Introduction LSI production testing is becoming important in the semiconductor industry, because testing cost is increas- ing while the cost of silicon is decreasing. ADCs are key components of mixed-signal SOCs, so to keep SoC chip cost low low-cost testing of ADCs is very important [ 3, 8,, 3]. This paper describes algorithms for generating a lowdistortion single-tone signal for ADC testing using a relatively low-performance (hence low-cost) arbitrary waveform generator (AWG). The AWG consists of DSP (or waveform memory) and DAC, and DAC nonlinearity causes distortion components [7]. We propose here to precompensate for the distortion using DSP algorithms. To be more precise, the proposed technique moves the unwanted tones farther from the wanted ones so that the following analog filtering becomes easier, and we will call this as distortion-shaping. The DSP part of the AWG can interleave multiple signals with the same frequency but different phase at the input to the DAC, in order to precompensate for distortion caused by the DAC nonlinearity (Fig. ). Theoretical analysis, simulation, and experimental results all show the effectiveness of this approach. Responsible Editor: H.-M. Chang K. Wakabayashi K. Kato T. Yamada H. Kobayashi (B) F. Abe K. Niitsu Electronic Engineering Department, Gunma University, -5- Tenjin-cho, Kiryu Gunma, , Japan k_haruo@el.gunma-u.ac.jp O. Kobayashi Semiconductor Technology Academic Research Center (STARC), Yokohama, , Japan Fig. ADC testing, where the analog signal input is generated by an AWG. Sinusoidal input, and distortion components in the output signal

2 2 Proposed Algorithm for Low-Distortion Sinusoidal Signal Generation with Two-Signal Interleave We use the following two-signal interleaved input for the DAC (Fig. 2): D in (n) = { X0 (n) in case n: even X (n) in case n: odd. () We denote the sampling period of the DAC as T s and its sampling frequency as f s (where T s f s = ). 2. HD3 Cancellation Algorithm We consider the case that third-order harmonic distortion (HD3) is dominant in the DAC and even harmonic components are small (e.g., when the DAC circuit and output signal are fully differential [9]). Y(nT s ) = a D in (n) + a 3 D in (n) 3. (2) Then we have the following DAC output from Eqs., 2: { a X Y(nT s ) = 0 (n) + a 3 X 0 (n) 3 in case n: even a X (n) + a 3 X (n) 3 (3) in case n: odd. Equation 3 can be written as follows [6]: Y(nT s ) = 2 [ + ( )n ][a X 0 (n) + a 3 X 0 (n) 3 ] + 2 [ ( )n ][a X (n) + a 3 X (n) 3 ]. (4) Note that ( ) n = cos(nπ) = cos(2π( f s /2)nT s ). (5) Fig. 3 Proposed method for sinusoidal signal generation with HD3 cancellation For a low-hd3 sinusoidal signal generation, we use the following X 0, X (Fig. 3): X 0 (n) = A sin(2π f in nt s + π/6) (6) X (n) = A sin(2π f in nt s π/6). (7) Then it follows from Eqs. 4, 5, 6 and 7 that Y(nT s ) = 3 2 (a A + 34 a 3 A 3 ) sin(2π f in nt s ) (a A+ 34 ) ( ( a 3 A 3 fs cos 2π + 2 ( ( 4 a 3 A 3 fs cos 2π 2 3 f in )nt s ) 2 f in ) ) nt s. (8) Fig. 2 Proposed method to generate low-distortion signal with an AWG. DSP provides the input signal X 0 and X alternatively to the following DAC, and distortion components (such as HD3) are cancelled We see that the HD3 (3 f in ) component is cancelled in Eq. 8. Numerical simulation results shown in Fig. 4 confirm that the HD3 component is cancelled (where a =.0, a 3 = 0.005, f in /f s = 5/024, A =.0). Since the high-frequency spurious components ( f s /2 3 f in, f s /2 f in ) are far from the signal component f in,they are relatively easy to remove by adding an analog filter after the DAC. We remark that the identification of a, a 3 values in Eq. 3 is not required in our algorithm.

3 a b Fig. 5 Proposed method for sinusoidal signal generation with HD2 cancellation For low-hd2 sinusoidal signal generation, we use the following X 0, X (Fig. 5): X 0 (n) = A sin(2π f in nt s + π/4), () X (n) = A sin(2π f in nt s π/4). (2) a Fig. 4 Simulation results of the proposed sinusoidal signal generation method in Fig. 3. a Conventional method. b Proposed method 2.2 HD2 Cancellation Algorithm Next consider the case that second-order harmonic distortion (HD2) is dominant in the DAC distortion, and DAC output is as follows: b Y(nT s ) = a D in (n) + a 2 D in (n) 2 = { a X 0 (n) + a 2 X 0 (n) 2 in case n: even a X (n) + a 2 X (n) 2 in case n: odd. (9) Equation 9 can be written as follows: Y(nT s ) = 2 [ + ( )n ][a X 0 (n) + a 2 X 0 (n) 2 ] + 2 [ ( )n ][a X (n) + a 2 X (n) 2 ]. (0) Fig. 6 Simulation results of the proposed sinusoidal signal generation method in Fig. 5. a Conventional method. b Proposed method

4 Then it follows from Eqs. 5, 0, and 2 that 2 Y(nT s ) = a 2 A a A sin (2π f in nt s ) ( ( ) ) a A 2 fs cos 2π 2 f in nt s + ( ( ) ) 2 a 2 A 2 fs sin 2π 2 3 f in nt s. (3) We see that the HD2 (2 f in ) component is cancelled in Eq. 3. Simulation results are also shown in Fig. 6 (where a =.0, a 2 = 0.005, f in /f s = 5/024, A =.0). 3 Experiments We have conducted experiments to show the effectiveness of our HD3 reduction algorithm for sinusoidal signal generation. We used an Agilent 3220A AWG and observed the output spectrum with an ADVANTEST R3267 spectrum analyzer (Fig. 7). Figure 8 shows that, for f in = 200 khz, our algorithm in Section 2. reduces the power of the HD3 component. Quantitative results of these experiments for f in = 200 khz are analyzed in Fig. 9. The X-axis indicates signal power for the conventional method; in Fig. 9a the Y-axis shows the power of HD3 component for conventional and proposed methods, and in Fig. 9b the Y-axis shows the power reduction of the signal and HD3 components for the proposed method. Note that the power reduction of the signal component is Fig. 8 Experiment for sinusoidal signal generation with an AWG. a Conventional and proposed methods. b Output power spectrum around the fundamental and HD3 components in both cases. c Measured power spectrum from 0 to f s. d Measured power spectrum from 0 to 5 f s Fig. 7 Experimental instruments for the proposed method.3 db (which agrees with the theoretical result), however the power reduction of the HD3 component is more than 4 db, which is substantial.

5 For example, we consider the case that HD3 and HD2 are dominant in the DAC. We have the following DAC output from Eq. 4: Y(nT s ) = a D in (n) + a 2 D in (n) 2 + a 3 D in (n) 3 a X 0 (n)+a 2 X 0 (n) 2 +a 3 X 0 (n) 3 (n=4k) a = X (n)+a 2 X (n) 2 +a 3 X (n) 3 (n=4k+) a X 2 (n)+a 2 X 2 (n) 2 +a 3 X 2 (n) 3 (n=4k+2) a X 3 (n)+a 2 X 3 (n) 2 +a 3 X 3 (n) 3 (n=4k+3). (6) For a low-hd3, HD2 sinusoidal signal generation, we use the following X 0, X, X 2 and X 3 (Fig. 0): X 0 (n) = A sin(2π f in nt s (5/2)π) X (n) = A sin(2π f in nt s (/2)π) Fig. 9 Experimental results. a HD3 in the output signal for conventional and proposed methods. b Reduction of the fundamental signal and HD3 components for the proposed method X 2 (n) = A sin(2π f in nt s + (/2)π) X 3 (n) = A sin(2π f in nt s + (5/2)π). (7) Here note that 4 Generalization of Proposed Harmonics Cancellation Algorithms 4. Four-Signal Interleave Algorithm We consider to use the following four-signal interleaved input for the DAC to cancel two harmonic distortion components (k 0 -th and k -th harmonics) simultaneously: (5/2)π = (/4)π + (/6)π, (/2)π = (/4)π (/6)π. Numerical simulation results shown in Fig. confirm that both HD3 and HD2 components are cancelled simultaneously (where a =.0, a 2 = 0.005, a 3 = 0.005, f in /f s = 5/024, A =.0). The detailed analysisisgiveninappendix. X 0 (n) = A sin(2π f in nt s + 0 ) (n = 4k) X D in (n)= (n) = A sin(2π f in nt s + ) (n = 4k + ) X 2 (n) = A sin(2π f in nt s + 2 ) (n = 4k + 2) X 3 (n) = A sin(2π f in nt s + 3 ) (n = 4k + 3). (4) Here k is an integer, and [ 0 = 2k 0 2k [ 2 = + 2k 0 2k ] [ π, = + 2k 0 2k ] [ π, 3 = + + 2k 0 2k ] π ] π. (5) Fig. 0 Proposed method for sinusoidal signal generation with HD2, HD3 cancellation

6 Fig. 2 Proposed method for sinusoidal signal generation with HD3, HD5, HD7 cancellation For example, we consider the case that HD3, HD5 and HD7 are dominant in the DAC. We have the following DAC output from Eq. 8: Y(nT s ) = a D in (n) + a 3 D in (n) 3 + a 5 D in (n) 5 + a 7 D in (n) 7. (9) For a low-hd3, HD5, HD7 sinusoidal signal generation, we use the following X 0, X, X 2.. and X 7 (Fig. 2): X l (n) = A sin(2π f in nt s + l ), (l = 0,, 2, 3,..., 7). Fig. Simulation results of the proposed sinusoidal signal generation method in Fig. 7. a Conventional method. b Proposed method (20) 4.2 Eight-Signal Interleave Algorithm We consider to use the following eight-signal interleaved input for the DAC to cancel three harmonic distortion components (k 0 -th, k -th and k 2 -th harmonics) simultaneously: X 0 (n) = A sin(2π f in nt s + 0 ) (n = 4k) X (n) = A sin(2π f in nt s + ) (n = 4k + ) X 2 (n) = A sin(2π f in nt s + 2 ) (n = 4k + 2) X 3 (n) = A sin(2π f in nt s + 3 ) (n = 4k + 3) D in (n) = X 4 (n) = A sin(2π f in nt s + 4 ) (n = 4k + 4) X 5 (n) = A sin(2π f in nt s + 5 ) (n = 4k + 5) X 6 (n) = A sin(2π f in nt s + 6 ) (n = 4k + 6) X 7 (n) = A sin(2π f in nt s + 7 ) (n = 4k + 7). (8) Here k is an integer. Fig. 3 Simulation results of the proposed sinusoidal signal generation method with 8-interleave in Fig. 2. a Conventional method. b Simulation method

7 Here 0 =[ (/6) (/0) (/4)]π =[ (/6) (/0) + (/4)]π 2 =[ (/6) + (/0) (/4)]π 3 =[ (/6) + (/0) + (/4)]π 4 =[+(/6) (/0) (/4)]π 5 =[+(/6) (/0) + (/4)]π 6 =[+(/6) + (/0) (/4)]π 7 =[+(/6) + (/0) + (/4)]π. Fig. 5 Simulation results (waveforms) for change of the interleave order of 8 phases Fig. 4 Simulation results (output power spectrum) for change of the interleave order of 8 phases Numerical simulation results shown in Fig. 3 confirm that HD3, HD5 and HD7 components are cancelled simultaneously. We have conducted simulation by changing the interleave order of the input signals. We see in Figs. 4, 5 that HD3, HD5, HD7 components are cancelled even if the order is changed, but high frequency spurious

8 5 Conclusion We have proposed a novel method to generate lowdistortion single-tone signals for ADC testing using a relatively low-performance (hence low-cost) AWG. In the AWG, the DSP part provides the interleaving of different-phase signals at the input of the DAC to cancel the distortion components. We have shown the effectiveness of this approach using theoretical analysis, simulation and experiments. Here are some concluding remarks: Fig. 6 Sampling frequency f s and input frequency f in for HD3, HD5 and HD7 simultaneous cancellation components power and waveforms are changed. We also note that as the number of the interleaved input signals increases, the sampling frequency f s must increase with respect to the input frequency f in. Figure 6 explains the case of HD3, HD5, HD7 cancellation with the eight-interleave method. We close this section by remarking that our algorithm can be generalized that the interleave of 2 k sinusoidal inputs with the same frequency but different phases can cancel k harmonic distortion components in the sinusoidal output.. The proposed method requires just the modification of the program in the DSP part of AWG, and there is no need for modification of the hardware configuration. 2. Calibration or adjustment of the analog circuit part is not needed. 3. Exact identification of the DAC nonlinearity is not required. 4. The concept of our algorithms is similar to the predistortion method in power amplifiers [4, 5, 0]. 5. In this paper, the power spectrum of the DAC output Y(nT s ) is considered only for f s /2 f f s /2 for simplicity. The power spectrum of the actual DAC output Y(t) includes its replica and all of them are multiplied by sinc(2π ft s ),which attenuates the high frequency components [9]. Fig. 7 Numerical simulation results of power spectrum beyond f s when the DAC output is in zero-th hold a b

9 6. We have the following observations regarding to the analog filter: (6-) We have conducted numerical simulation beyond the Nyquist frequency ( f s /2) for the conventional and proposed methods, assuming the DAC output is in zero-th hold and a = 2.0, a 3 = 0.002, f in /f s = 25/52, A =.0 (Fig. 7). Also Fig. 8 shows the measured power spectrum beyond the Nyquist frequency. We see in Figs. 8 and 7 that the tones appear around at f s, 2 f s, 3 f s,... for the conventional method, and around at (/2) f s, (2/2) f s, (3/2) f s,... for the proposed method. (6-2) These tones should be removed by an analog filter following the AWG even for the conventional method, and AWG manufacturers say that in many cases, a high-order (such as seventh-order LC Butterworth) analog filter is used in practice. (6-3) Our proposed method can be used with the same order analog filter (but whose corner frequency is less than half) as the one for the conventional method, and by limiting the maximum signal frequency f in to less than half of the one for the conventional method. In other words, the proposed method is applicable for an existing AWG with the penalty of the limitation of the maximum signal frequency. (6-4) The rapid advancement of LSI technology makes the DAC sampling speed faster, but the device mismatches (which cause the DAC nonlinearity) would not be improved, hence the proposed approach would become more effective as the LSI technology progress goes on. If the sampling frequency becomes more than twice for a next generation AWG, the required analog filter could be comparable for the conventional method with a present generation AWG, for a given maximum signal frequency. 7. The proposed technique moves the unwanted tones farther from the wanted ones so that filtering becomes easier. As the sampling frequency f s increases for given wanted tones, the unwanted tones go much farther away. We will call this as distortion-shaping, which is a new concept similar to but different from noise-shaping. 8. We have shown in [4] that our proposed algorithm is also applicable to DAC as well as Nyquistrate DAC. 9. We have shown in [2, 4] that our proposed algorithm is extendable to low IMD3 two-tone signal generation. Acknowledgments We would like to thank T. Matsuura, N. Takai, Y. Yano, T. Gake, T. J. Yamaguchi, H. Miyashita, S. Kishigami, K. Rikino, S. Uemori and K. Wilkinson for valuable discussions. Appendix This appendix describes the explicit power spectrum of the DAC output Y(nT s ) for the simultaneous cancellation algorithm of HD3 and HD2 in Section 4.. Equation 4 can be written as follows: D in (n) = 4 [ ( + W n + W 2n + W 3n )X 0 (n) + ( + W n + W 2(n ) + W 3(n ) )X (n) + ( + W n 2 + W 2(n 2) + W 3(n 2) )X 2 (n) + ( + W n 3 + W 2(n 3) + W 3(n 3) )X 3 (n) ]. (2) Here W = exp( jπ/2). Then explicit Y(nT s ) can be obtained from Eqs. 6, 7 and 2 as follows: Y(nT s ) = 6 2 ca2 + 4 (aa+ 34 ba3 ) sin(2π f in nt s ) (aa+ 34 ) 8 ba3 [ ( ( ) ) 4 f s + f in nt s ( ( ) )] + cos 2π 4 f s + f in nt s 6 2 (aa+ 34 ) 8 ba3 [ ( ( ) ) 4 f s f in nt s ( ( ) )] + cos 2π 4 f s f in nt s + 3 ca 2 8

10 [ ( ( ( cos 2π [ ( ( cos 2π [ ( ( ( + cos 2π [ ( ( 2 4 ( + cos 2π ) nt s ) 4 f s + 2 f in ( )] 4 f s +2 f in )nt s ( ) ) 4 f s 2 f in nt s ( ) )] 4 f s 2 f in nt s + ) ) nt s 4 f s + 3 f in ( ) )] 4 f s + 3 f in nt s ) ) nt s 4 f s 3 f in ( ) )] 4 f s 3 f in nt s ( ( 2π (aa+ 34 ba3 ) cos 2 8 ba3 cos ( ( 2π 2 f s 3 f in + 3 ca f s f in ) ) nt s. 2 6 ba3 2 6 ba3 )nt s ) We see that 2 f in, 3 f in components are cancelled in Y(nT s ). References. Arabi K (200) Mixed-signal test impact to SoC commercialization. In: IEEE VLSI test symposium 2. Burns M, Roberts GW (2000) An introduction in mixedsignal IC test and measurement. Oxford Univ Press 3. Cheng K-T, Chang H-M (200) Recent advances in analog, mixed-signal and RF testing. IPSJ trans on system LSI design methodology, vol 3, pp Cripps SC (999) RF power amplifier for wireless communications. Artec House, pp Cripps SC (2002) Advanced techniques in RF power amplifier design. Artec House, pp Kurosawa N, Kobayashi H, Maruyama K, Sugawara H, Kobayashi K (200) Explicit analysis of channel mismatch effects in time-interleaved ADC systems. IEEE Trans Circuits Syst I 48(3): Maeda A (2008) A method to generate a very low distortion, high frequency sine waveform using an AWG. In: IEEE international test conference, Santa Clara, CA 8. Maloberti F (2007) Data converters. Springer 9. Plassche R (2003) CMOS integrated analog-to-digital and digital-to-analog converters, 2nd edn, Chapters, 4 and 6. Kluwer Academic Publishers, Boston 0. Shrestha R, Mensink E, Klumperink EAM, Wienk GJM, Nauta B (2006) A multi-path technique canceling harmonics and sidebands in a wideband power upconverter. In: Tech digest of IEEE international solid-state circuits conference, San Francisco. Uemori S, Yamaguchi TJ, Ito S, Tan Y, Kobayashi H, Takai N, Niitsu K, Ishikawa N (200) ADC linearity test signal generation algorithm. In: IEEE Asia Pacific conference on circuits and systems, Kuala Lumpur 2. Wakabayashi K, Yamada T, Uemori S, Kobayashi O, Kato K, Kobayashi H, Niitsu K, Miyashita H, Kishigami S, Rikino K, Yano Y, Gake T (20) Low-distortion single-tone and two-tone sinewave generation algorithms using an arbitrary waveform generator. In: IEEE international mixed-signals, sensors and systems test workshop, Santa Barbara, CA 3. Yagi T, Kobayashi H, Tan Y, Ito S, Uemori S, Takai N, Yamaguchi TJ (200) Production test consideration for mixed-signal IC with background calibration. IEEJ Trans on Electrical and Electronic Eng 5(6): Yamada T, Kobayashi O, Kato K, Wakabayashi K, Kobayashi H, Matsuura T, Yano Y, Gake T, Niitsu K, Takai N, Yamaguchi TJ (20) Low-distortion single-tone and twotone sinewave generation using DAC. In: IEEE international test conference (poster session), Anaheim, CA Kazuyuki Wakabayashi received the B.S. degree from Tokyo University of Technology in 2009 and the M.S. degree in electronic engineering from Gunma University in 20. He is currently working for Fujitsu Ltd. where he is engaged in firmware design for optical transceivers. His research interests include ADC testing technology, power supply and power amplifier circuits. Keisuke Kato received the B.S. degree in electronic engineering from Gunma University in 20 and he is currently a master course student there. His research interests lie in ADC testing technology. Takafumi Yamada received the B.S. and M.S. degrees in electronic engineering from Gunma University in 2009 and 20 respectively. He is currently working for Nippon Signal Co., Ltd. His research interests include sigma-delta AD/DA modulator design and ADC testing technology. Osamu Kobayashi received the B.S. and M.S. degrees in electric and electronic engineering from Tokyo Institute of Technology in 982 and 984 respectively. He joined Fujitsu Ltd. Kanagawa, Japan in 984, and was engaged in developing analog IPs for CMOS Mixed Signal LSI. From , he joined Fujitsu Laboratories LTD. He is currently working for Semiconductor Technology Academic Research Center. Haruo Kobayashi received the B.S. and M.S. degrees in information physics from University of Tokyo in 980 and 982 respectively, the M.S. degree in electrical engineering from the University of California at Los Angeles (UCLA) in 989, and the Ph. D. degree in electrical engineering from Waseda University in 995. He joined Yokogawa Electric Corp. Tokyo, Japan in 982, and was engaged in research and development related to measuring instruments. In 997, he joined Gunma University and presently is a Professor in electronic engineering department there. His research interests include mixed-signal integrated circuit design and signal processing algorithms. Fumitaka Abe received the B.S. degree (honored) in electronic engineering from Gunma University in 202, and he is currently

11 a master course student there. His research interests lie in ADC testing technology. Kiichi Niitsu received the B.S. degree summa cum laude, M.S. and Ph.D. degrees in electrical engineering from Keio University, Yokohama, Japan, in 2006, 2008 and 200, respectively. He is currently an Assistant Professor at Gunma University. Since 2005, he was engaged in a research on the low-power design in the wireless inter-chip interface for high-performance, low-power 3D system integration and for short-range inter-chip communication. His current research interest lies in the power-aware analog VLSI design and DFT techniques for mixed-signal VLSIs. From , Dr. Niitsu was a Research Fellow of the JSPS, a Research Assistant of the GCOE Program at Keio University.