Phase Noise Measurement Techniques Using Delta-Sigma TDC

Transcription

1 19 th IEEE IMS3TW, Porto Alegre, Brazil Sept. 17, 2014 Phase Noise Measurement Techniques Using Delta-Sigma TDC Yusuke Osawa Daiki Hirabayashi Naohiro Harigai Haruo Kobayashi Kiichi Niitsu Osamu Kobayashi Gunma University Nagoya University STARC Gunma University Kobayashi Lab 1/38

2 Outline 2/38 Research Background & Objective Delta-Sigma TDC Phase Noise Measurement using ΔΣTDC with Reference Clock Phase Noise Measurement using ΔΣTDC without Reference Clock - Self-Referenced Clock Technique Conclusion

3 Outline 3/38 Research Background & Objective Delta-Sigma TDC Phase Noise Measurement using ΔΣTDC with Reference Clock Phase Noise Measurement using ΔΣTDC without Reference Clock - Self-Referenced Clock Technique Conclusion

4 Research Background 4/38 Phase noise of clock can cause malfunctions of electronic systems Oscillator phase noise Df (0) Df (T) Df (2T) Timing Jitter : Df Electronic system performance degradation RF circuit & system ADC Test & measurement for phase noise, jitter is important

5 Conventional MethodⅠ Conventional Phase Noise Measurement 5/38 Expensive : Spectrum Analyzer Long testing time: ~10 seconds Mass production Test cost high

6 Counter Output Conventional MethodⅡ 6/38 On-chip Jitter Measurement Circuit Cascaded TDA CLK (Period :T ) DT in Digital ntdelay (n 3) TDA Latch Counter m bit Digital Code (CDF) DT Can NOT measure jitter power spectrum [1] K. Niitsu, et al., CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier with Duty-Cycle Compensation, IEEE Journal of Solid-State Circuits, Nov

7 Power Research Objective 7/38 Low cost, high quality phase noise measurement w/o Spectrum Analyzer Clock Under Test CLKref w/ BIST or BOST DS TDC Simple circuit FFT BIST : Built-In Self-Test BOST : Built-Out Self-Test Phase Noise f

8 Outline 8/38 Research Background & Objective Delta-Sigma TDC Phase Noise Measurement using ΔΣTDC with Reference Clock Phase Noise Measurement using ΔΣTDC without Reference Clock - Self-Referenced Clock Technique Conclusion

9 Power Phase Noise Measurement Flow 9/38 Phase noise : Frequency characteristics Phase Noise f Time domain Freq. domain CUT with phase noise Phase noise measurement Power spectrum CUT : Clock Under Test

10 Proposed Method Time domain 10/38 Freq. domain CUT with phase noise Phase noise measurement Power spectrum Delta-Sigma TDC Time resolution improved by longer measurement time Ex: τ = 1ns, N DATA =64K T_resolution = 0.03ps TDC : Time-to-Digital Converter

11 Principle of ΔΣTDC 11/38 CLK1 CLK2 ΔΣTDC delay: t Dout 0 or 1 CLK1 CLK2 DT DT DT DT short # of 1 s few Dout # of 1 s is proportional to DT Dout long many

12 ΔΣTDC Configuration 12/38 CLK1 DT CLK2 M U X t M U X M U X Phase Detector Up Down Δ Σ Integrator INTout < 0:Dout=0 INTout > 1:Dout=1 INTout - + Dout Timing Generator

13 Outline 13/38 Research Background & Objective Delta-Sigma TDC Phase Noise Measurement using ΔΣTDC with Reference Clock Phase Noise Measurement using ΔΣTDC without Reference Clock - Self-Referenced Clock Technique Conclusion

14 Power Power Time Difference Time Difference Principle of Phase Noise Measurement CLK1 without phase noise DT DT DT CLK1 with phase noise DT+t 1 DT+t 2 DT+t 3 14/38 CLK1 CLK1 CLK2 CLK2 DT DT DT DT DT+t 1 DT+t 2 DT+t 3 DT+t 4 FFT Time FFT Time DC component due to DT DC component due to DT Phase noise Noise shaping Noise shaping DC Frequency DC Frequency

15 Clock Under Test [CUT] Mathematical Analysis Zero-Crossing Point 0 T 2T mt 15/38 : m-th zero-crossing point variation function (noise component) In case of sinusoidal phase fluctuation : phase noise (time domain) : phase noise (time domain) : phase noise (freq. domain)

16 MATLAB Simulation 16/38 w/ Phase Noise VTD (Variable Time Delay) CLK CLK VTD CUT (Clock Under Test) REF DS TDC Dout w/o Phase Noise

17 Simulation Conditions 17/ CLK CLK VTD CUT REF DSTDC t : 200ns Dout Input freq. Phase variation(sinusoidal) Phase noise frequency : fj varied Jitter variation : Number of data: 4096

18 Simulation Conditions 18/ CLK CLK VTD CUT REF DSTDC t : 200ns Dout Input freq. Phase variation(sinusoidal) Phase noise frequency : varied Jitter variation : Single sine wave Multiple sine waves Number of data: 4096

19 Power [db] Power [db] W/O Phase Noise W/ Phase Noise:10kHz Simulation Results Frequency [khz] Frequency [khz] -13.7dB phase noise -13.1dB 19/38 Theoretical value

20 Power [db] Simulation Results 2 20/38 W/ Phase noise:50khz Phase noise Frequency [khz]

21 Power [db] Simulation Results 3 21/38 Phase noise:10khz & 50kHz Phase noise -13.2dB -13.8dB Frequency [khz] Theoretical value Power = -13.1[dB]

22 Outline 22/38 Research Background & Objective Delta-Sigma TDC Phase Noise Measurement using ΔΣTDC with Reference Clock Phase Noise Measurement using ΔΣTDC without Reference Clock - Self-Referenced Clock Technique Conclusion

23 Problem of Proposed Method I 23/38 CUT REF w/ Phase Noise DS TDC Dout w/o Phase Noise Difficult to implement

24 Self-Referenced Phase Noise Measurement Method 24/38 w/ Phase Noise CUT DS TDC Dout βt-delay No need for jitterless reference clock βt-delay: β is not required to be an integer.

25 Proposed Methods Ⅰ&Ⅱ 25/38 MethodⅠ Timing jitter measurement MethodⅡ Period jitter measurement

26 Mathematical Analysis 26/38 1 Measurement of each period : phase noise (time domain) In case of sinusoidal phase variation

27 Mathematical Analysis 27/38 1 phase noise (time domain) In case of sinusoidal phase variation phase noise (frequency domain) phase noise power at ω1 ω1: phase noise freq. [low freq.] T : input CLK period (=1/f)

28 Simulation Conditions 28/38 w/ Phase Noise CLK VTD CUT Dout βt-delay Input freq. Phase variation (sinusoidal) Phase noise frequency : varied Jitter variation : Single sinusoidal Multiple sinusoidal Number of data: 4096

29 Power [db] Power [db] Phase noise:1khz Simulation Results 1&2 29/38 0 Phase noise Phase noise:10khz Frequency [khz] Frequency [khz] Phase noise

30 Power [db] Power [db] Phase noise:100khz Simulation Results 3& Phase 位相ノイズ noise Phase noise:10khz&50khz Frequency [khz] Frequency [khz] 30/38

31 Power [db] Comparison of Theory and Simulation Results 31/ シミュレーション 理論値 Phase variation frequency [khz] simulation theory Theoretical expression

32 Simulation Conditiions 32/38 w/ Phase Noise CLK VTD CUT Dout βt-delay Input freq. Phase variation(sinusoidal) Phase noise frequency : Jitter variation : β value deviation by ±5% from 1.0 β=0.95 β=1.05 Number of data: 4096

33 Power [db] Power [db] Simulation Results(delay β variation) β = 0.95 (error -5%) β = 1.05 (error +5%) Frequency [khz] dB Frequency [khz] -30.0dB 33/38

34 Power [db] Power [db] Simulation Results(delay β variation) β = 0.95 (error 誤差 -5%) Phase noise : 10kHz 100 β = 1.05 (error 誤差 +5%) 0 Frequency [khz] -30.3dB Frequency [khz] -30.0dB -30.2dB phase noise 34/38

35 Outline 35/38 Research Background & Objective Delta-Sigma TDC Phase Noise Measurement using ΔΣTDC with Reference Clock Phase Noise Measurement using ΔΣTDC without Reference Clock - Self-Referenced Clock Technique Conclusions

36 Conclusion 36/38 Proposal of two phase measurement techniques with DSTDC Low cost testing without requiring spectrum analyzer On-chip high-precision phase noise measurement Fine time resolution measurement possible with ΔΣTDC Phase noise power spectrum obtained by FFT of TDC digital output 1MHz carrier (clock), 64K TDC output data Phase noise power spectrum of 0 to 0.5MHz away from 1MHz with 15.2Hz resolution. MATLAB simulation verification Verified by superimposing several sinusoidal phase variation components Compared theoretical analysis and simulation results Self-referenced clock method with several β delay coefficient values

37 37/38 Time is GOLD!! ΔΣTDC is the key.

38 Acknowledgement 38/38 We would like to thank Semiconductor Technology Academic Research Center (STARC) for kind support of this project.

39 39/38