ΔΣ Digital-to-Time Converter and its Application to SSCG *

Transcription

1 ΔΣ Digital-to-Time Converter and its Application to SSCG * 1 Ramin Khatami, 1 H. Kobayashi, 1 N. Takai, 1 Y. Kobori, 2 T. Yamaguchi, 2 E. Shikata, 2 T. Kaneko, 3 K. Ueda 1 Gunma University 2 AKM Technology Corporation 3 Asahi Kasei Microdevices Corporation With Special Thanks to NEC C&C Foundation *SSCG : Spread Spectrum Clock Generator The 4th IEICE International Conference on Integrated Circuits Design and Verification (ICDV 2013) Hi Chi Minh City-Vietnam

2 Outline I. Background II. Principle i. PCMΔΣDTC Algorithm ii. PPMΔΣDTC Algorithm iii. PWMΔΣDTC Algorithm iv. PRJΔΣDTC Algorithm v. Other Possible Algorithms III. Analysis IV. Result V. Conclusion 2

3 Outline I. Background II. Principle i. PCMΔΣDTC Algorithm ii. PPMΔΣDTC Algorithm iii. PWMΔΣDTC Algorithm iv. PRJΔΣDTC Algorithm v. Other Possible Algorithms III. Analysis IV. Result V. Conclusion 3

4 Common Object in All Electronic Devices Clock Signal Circuit Clock is everywhere 4

5 Power Power Power Power Volts Volts Spread Spectrum Clock Technique Time Time Frequency Frequency EMI Limit EMI Limit Frequency Frequency 5

6 EMI Problem Class A: Industrial Class B: Home EMI Regulation (CISPR22 ) in Japan Ignoring is Dangerous Solving is difficult Lead to Malfunctioning of devices Time Consuming Costly 6

7 Volts Volts SSGC Approach Time Time Solving Digital Problem By Analog Approach 7

8 Power Conventional SSGC Problems 1 Wasting huge bandwidth 2 Interfere with other desired signals Frequency 8

9 Power Exclusive Noise Spectrum Selection Our Target: EMI Limit Ex. FM band f v f [Hz] EMI Limit Frequency 9

10 Goal To compete with conventional methods, Our method should be: Simple Low cost Effective 10

11 Converters Path Devices miniaturization, speed, high frequency Spreading ΔΣ oversampling Applications Time domain signal processing From ΔΣADC to ΔΣTDC From ΔΣDAC to??? 11

12 Time Domain v.s. Voltage Domain ΔΣTDC ΔΣADC Analog Time Voltage Digital ΔΣDTC ΔΣDAC Kobayashi Ring 12

13 ΔΣDAC & ΔΣ DTC Analogy ΔΣDAC Digital Input Digital ΔΣ Modulator 1 or 0 1bit DAC Pulse Density Analog Output ΔΣDTC Digital Input Digital ΔΣ Modulator time domain 1 or 0 1bit DTC One bit Resolution Timing Signal 13

14 Outline I. Background II. Principle I. PCMΔΣDTC Algorithm ii. PPMΔΣDTC Algorithm iii. PWMΔΣDTC Algorithm iv. PRJΔΣDTC Algorithm v. Other Possible Algorithms III. Analysis IV. Result V. Conclusion 14

15 Pulse Cycle Modulation Output Pulse Cycle Period = f (D out ) Exa. : (D out =10110) D out = 0 D out = 1 S out S out 0 T 0 T 2T D out = 1, 0, 1, 1, 0 0 T 2T 3T 4T 5T 6T 7T 8T S out 15

16 PCMΔΣDTC Configuration D in Digital Input Generation circuit + D out PCM DTC S out CLK Clock Generator D in + Buffer Memory D out PCM DTC S out Clock Generator 16

17 Outline I. Background II. Principle i. PCMΔΣDTC Algorithm ii. PPMΔΣDTC Algorithm iii. PWMΔΣDTC Algorithm iv. PRJΔΣDTC Algorithm v. Other Possible Algorithms III. Analyze IV. Result V. Conclusion 17

18 Pulse Position Modulation Output pulse position (or phase) = g(d out ) Ex. (D=10110) D out = 0 D out = 1 S out φ = 0 S out φ = C 0 T 0 T D out = 1, 0, 1, 1, 0 0 T 2T 3T 4T 5T S out 18

19 PPMΔΣDTC - Configuration Digital Input ΔΣ Modulator Clk τ MUX clkout High Frequency Clock 19

20 Outline I. Background II. Principle i. PCMΔΣDTC Algorithm ii. PPMΔΣDTC Algorithm iii. PWMΔΣDTC Algorithm iv. PRJΔΣDTC Algorithm v. Other Possible Algorithms III. Analysis IV. Result V. Conclusion 20

21 Pulse Width Modulation Output pulse width = h(d out ) Exa. : (D out =10110) D out = 0 τ L S out D out = 1 S out τ H 0 T 0 T D out = 1, 0, 1, 1, 0 0 T 2T 3T 4T 5T S out 21

22 PWMΔΣDTC - Configuration Digital Input ΔΣ Modulator Sawtooth Wave Generator Clk clkout 22

23 Outline I. Background II. Principle i. PCMΔΣDTC Algorithm ii. PPMΔΣDTC Algorithm iii. PWMΔΣDTC Algorithm iv. PRJΔΣDTC Algorithm v. Other Possible Algorithms III. Analysis IV. Result V. Conclusion 23

24 Pseudo Random Jitter Output pulse cycle = k(d out,h) Exa. : (D out =10110) D out = 0 D out = 1 S out S out S out 0 T 0 T 2T 0 T 2T 3T D out (0) = 1, D out (1) = 0, D out (2) = 1, D out (3) = 1, D out (4) = 0 0 T 2T 3T 4T 5T 6T 7T 8T S out 24

25 PRJΔΣDTC - Configuration Digital Input ΔΣ Modulator dτ nτ mτ MUX Clk out Clk PRPG Pseudo Random Pulse Generator 25

26 Outline I. Background II. Principle i. PCMΔΣDTC Algorithm ii. PPMΔΣDTC Algorithm iii. PWMΔΣDTC Algorithm iv. PRJΔΣDTC Algorithm v. Other Possible Algorithms III. Analysis IV. Result V. Conclusion 26

27 Compound DTC PCMDTC: based on digital Input Alter T S out φ τ P T PPMDTC: Alter φ S out φ τ P T τ P PWMDTC: Alter τ P S out φ τ P PRJDTC: Alter T randomly PPCMDTC, PPWMDTC,PPCRJCDTC, S out φ T 27

28 Outline I. Background II. Principle i. PCMΔΣDTC Algorithm ii. PPMΔΣDTC Algorithm iii. PWMΔΣDTC Algorithm iv. PRJΔΣDTC Algorithm v. Other Possible Algorithms III. Analysis IV. Result V. Conclusion 28

29 SSGC with Exclusive Noise Spectrum using ΔΣDTC Digital Pulse τ p T C = 1 (base), T = nt C, τ P =mt C, φ =2πq/n PCMΔΣDTC S out φ T, = 1, 2, 3, 4,, PPMΔΣDTC, = 1, 2, 3, 4,, 29

30 SSGC using Delta-Sigma DTC Digital Pulse τ p T C = 1 (base), T = nt C, τ P =mt C, φ =2πq/n PWMΔΣDTC S out φ T, = 1, 2, 3, 4,, PRJΔΣDTC 30

31 Outline I. Background II. Principle i. PCMΔΣDTC Algorithm ii. PPMΔΣDTC Algorithm iii. PWMΔΣDTC Algorithm iv. PRJΔΣDTC Algorithm v. Other Possible Algorithms III. Analysis IV. Result V. Conclusion 31

32 Result Clock s PSD(Without DTC) 66 db in Base & in Each Clock Harmonics (66) 32 f

33 PCMΔΣDTC -16dB 50 db (50) -35 db T L =5 T H = 7 f

34 PPMΔΣDTC -2dB (64) 64 db -31dB φ=0 T L =5 T H =5 φ=2 f

35 PWMΔΣDTC (67) -4dB 62 db -37 db T L =5 τ L =1 T H =5 τ H =3 f

36 PRJΔΣDTC -15 db 51 db (52) -37 db T L =5 T H =5 or 6 or 7 f

37 Compound DTC: PRJWPΔΣDTC -17 db (63) 49 db T L =5 T H =5 or 6 or db f φ=

38 Outline I. Background II. Principle i. PCMΔΣDTC Algorithm ii. PPMΔΣDTC Algorithm iii. PWMΔΣDTC Algorithm iv. PRJΔΣDTC Algorithm v. Other Possible Algorithms III. Analysis IV. Result V. Conclusion 38

39 Result Low Cost Simplicity Accuracy +Completely Digital Circuit +High Frequency clock Spreading Usage Spectrum of SSCG With Exclusive Noise Spectrum! 39

40 The End 小林先生ありがとう ご清聴有り難う御座います Cảm ơn bạn rất nhiều 非常感谢 Thank You Very Much خیلی ممنون Muchas gracias Большое спасибо Vielen Danken 40

41 Presentation Presentation Start 41

42 Presentation Kobayashi Ring Conclusion 42

43 Presentation Question and Answer 43