Delta-Sigma Digital-to-Time Converter and its Application to SSCG

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1 THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS IEICE ICDV 23 Delta-Sigma -to-time Converter and its Application to SSCG Ramin Khatami, Haruo Kobayashi, Nobukazu Takai, Yasunori Kobori Tetsuji Yamaguchi, Eiji Shikata Tsuyoshi Kaneko, Kimio Ueda Division o Electronics and Inormatics, Gunma University, Kiryu Japan ramin@khatami.me, k_haruo@el.gunma.ac.jp AKM Technology Corporation Asahi Kasei Microdevices Corporation Abstract This paper proposes an innovative method o converting digital signal to time-domain analog signal, which ully enjoys robustness and digital circuit riendliness. This technique utilizes a digital delta-sigma ( Σ) modulator ollowing a digital-to-time converter (DTC) circuit with various modulation methods. As an application o the proposed method, novel spread-spectrum clock generation (SSCG) algorithms (such as or DC-DC converters) have been investigated which can select the noise spectrum spread bands; e.g., they can exclude the noise spectrum spread in AM, FM radio bands. The proposed circuit takes advantage o digital technology, which is simple, ast (reachable at high clock requency) and lexible (programmable). Keywords -to-time Converter, Σ, Spread Spectrum Clock Generation, Time-Domain, EMI, Band Selection. Introduction Constant miniaturization, speeding up and rising requency o semiconductor devices in recent years have accelerated usage and application o oversampling methods []. The delta-sigma method opens up broad range o analyzing signal in the time domain possibility. Handling signal processing in time domain, does not just enhance processing signal in ully digitized circuit which has been the trend in recent years [2]. Beneits o signal processing in time domain has caught so many eyes in recent years and lead to many new ields opening like: Time to Converter (TDC) which is time-domain equivalent o delta-sigma digital-to-analog converters (Fig. a). This paper proposes a simple method o converting the digital signal to the timing signal, which is basically DAC correspondent in time domain; this technique utilizes a digital delta-sigma ( Σ) modulator ollowing a DTC circuit with various modulation methods. As an application o the proposed method, novel spreadspectrum clock generation (SSCG) algorithms (such as or DC-DC converters) have been investigated which can select the noise spectrum spread bands; e.g., they can exclude the noise spectrum spread e.g., in AM, FM radio bands (Fig.2). This can be used as an EMI reduction technique [3]-[]. In section 2, we explain the concept and theory o the proposed delta-sigma DTC. In section 3, we present applications o the proposed DTC to SSCG or EMI reduction. The proposed method can be implemented ully digital circuit and select the noise spectrum spread bands, which could be called as a second generation SSCG. We show several modulation methods with their simulation results. Section 4 provides conclusion. 2. Principle o ΣDTC 2.. Fundamental Theory Traditionally, inormation has been processed and encoded in the voltage domain; however, more recently inormation encoding in time domain has considerably gained popularity. Data conversion in theory is simply the process o working with signals in dierent domains. The DTC is a converter device which maps a digital value to a timing signal. Basic distinction between DTC and DAC is the domains where they unction; the DTC operates in time domain, whereas the DAC operates in voltage domain. The process o converting signal rom digital to analog (or vice versa) usually involves many techniques including iltering and smoothing o the signal beore and ater the conversion. In this regard, our proposed DTC is in ull compliance with its conventional methods. The DTC includes a digital Σ converter (Fig. 3); here, samples are interpolated with an analog low pass ilter (LPF). In time domain, a LPF is used to smooth the Copyright c 23 by IEIC

2 signal by cutting high requency components. The delta-sigma DTC idea is - to our knowkedge- only used or very recent work [] which employs DTC driven phase signal conversion or automatic test equipment (ATE) applications. This work diers in two main points rom it; First, our proposed methods apply pulse cycle and width modulation with some innovative ways in addition to phase modulation, and also utilize an asynchronous counter to perorm as a low pass ilter in time domain which - due to its digital nature - is very simple compared to PLL. Now we introduce timing pulse deinition. An electric pulse wave is a periodic square waveorm which alternates at a steady requency between two ixed points. Thus the pulse requency, position and width are the undamental characteristics which deine a pulse. We will deal with all these three elements to orm our DTC signal. T, φ, τ p in Fig. 4 are index names or the pulse cycle period (or reciprocal o requency), position (or phase) and width, respectively PCM ΣDTC We consider Pulse Cycle Modulation (PCM), which is a manipulation o representing each timing signal pulse cycle (Figs. 5, 6). For example, digital is mapped to a time signal with cyclic period o T while " is with 2T; then in case o digital inputs sequence D=, the output signal is shown in Fig. 5. Block diagram o the Σ PCM DTC is illustrated in Fig. 6. Because o unlimited variable periods which we can choose rom requency, PCMDTC could be superior to other ollowing methods in regard to multi-bit modulation PPM ΣDTC Pulse Position Modulation (PPM) Σ DTC encodes each digital signal value by shiting output pulse signal beginning position Figs. 7, 8). So or instance, i we have output pulse with the requency o, digital " is mapped to pulse with zero shiting position (phase = ), and digital " is mapped to pulse with shiting position o a constant C (where C T ). A sample modulation o digital value similar to PCMDTC () is shown in Fig. 7. Two major dierences and beneits o PPMDTC compared to the previous method are as ollows: First, output signal length is independent o numbers o " s and " s. Second, it consists o only a delay element and an digital multiplexer (Fig. 8). This circuit capability o handling high-requency signal in digital circuit might be game changer actor to choose it over other methods in applications PWM ΣDTC Pulse Width Modulation (PWM) DTC changes the output signal width based on digital input value (Figs. 9, ). It implementation may be a little bit complex, but but its beneits surace up when it is used in conjuncture with other methods, which we will discuss later in this section PRJ ΣDTC Pseudo Random Jitter (PRJ) DTC is very similar to pulse cycle modulator (PCM), because, like PCM, the major distinction between two timing output signals or two distinct digital inputs are pulse requency (cycle period). However in PRJ, output signal requency changes arbitrarily between two (or more or multi-bit DTCs) constant values 2. This technique can be achieved by randomly delaying output signal so that it looks like a big jitter in output pulse. Fig. shows a sample output o PRJ DTC or a digital input sequence o Compound Methods We can extend our proposed DTC methods by combining o PCM, PPM, PWM or randomly changing any o three main characteristic(cycle, position and width) or more eective SSCGs. 3. Spread Spectrum Techniques 3.. Spread Spectrum Technique Introduction One o the biggest obstacles in miniaturization, higher operating requency and packaging all system in a single chip, arguably is Electro-Magnetic Intererence (EMI) [9]. EMI does not just degrade or limit the eective perormance o the circuit, but also it hardens manuacturers struggle to keep up with law and regulations enorced by dierent countries (like FCC). It is well-known that, during system development, critical signalintegrity and EMI simulations are diicult, time-consuming, and error-prone due to their reliance on hard-to-predict models and parameter extractions. Fig. 3 shows noise spectrum power o a typical digital system; noise spectrum peaks appear in base band and they are harmonic requencies. Constant requency intervals are due to the system clock, in act, EMI main source in digital circuits is clock signal. Although limitation o interering signal power in higher requency ( 23MHz) is slightly looser (Fig.4), it is becoming constantly harder to contain those circuits below the threshold without signiicant shielding, which results in adding to circuit size.

3 3.2. Spread Spectrum Clock Generator Spreading spectrum techniques o the clock signal have been widely used or EMI reduction in digital processor and DC-DC converter areas. Their conventional methods use requency-modulating the system clock with a low-requency signal as well as other modulation schemes. This approach creates requency spectrum with sideband harmonics. Intentionally broad-banding the narrow-band repetitive system clock simultaneously reduces the peak spectral energy in both the undamental and the harmonic requencies. I the clock requency spreads widely, the peak power is reduced and EMI problem is suppressed. However, in many applications some signal bands (such as AM, FM radio requency bands) are important and it is not desirable or the spread clock requency components enter into the bands. We present here that SSCGs with our proposed delta-sigma DTC methods can adjust emission bands and excluding (or surpassing) noise emission in speciic bands. 4. Simulation Results Eectiveness o the proposed delta-sigma DTC methods applied to SSCG has been veriied by numerical simulation. 4.. SSCG Simulation Methodology Sine wave with requency o s/n, sampled in N points with sampling requency s is ed to DTC as digital input. Ater being noise-shaped by a irst-order delta-sigma converter, output has been digital-to-time modulated according to the relevant method. Original clock (without sigma-delta DTC modulation) signal base peak power and its harmonics reach to 66dB (Fig. 5) SSCG using PCM ΣDTC Spread spectrum with PCM DTC suppresses spectrum peak signiicantly and also creates notches at some locations. The power spectrum o previously introduced signal by various DTC has been presented in Fig. 6, where we derive that notch locations are given by eq.(). Here we assume that periods T H and T L corresponding to digital signals and are integer (n H, n L) multiples o constant minimum base period (T C), respectively. notch = K (nh + nl) s () 2 n H n L where: K = n H n L, n H n L 2,,. n H and n L are positive integers, deined as n H = T H/T C, n L = T L/T C SSCG using PPM ΣDTC Spread spectrum power o the PPM DTC method is illustrated in Fig. 7. I we assume that each pulse period (T H, T L ) is integer (n H, n L) multiple o base period T C and each pulse phase (φ H, φ L corresponding to digital signals, respectively) are integer (q H, q L) multiples o constant minimum base period (T C), then we observe that PPM DTC has capability to lower noise in particular bandwidth given by eq.(2), although PPM DTC inluence on signals peaks may not be suicient. notch = K s (2) q H q L where K = q H q L, q H q L 2,,. q H and q H are positive integers, deined as q H = n H(φ H/2π), 4.4. SSCG using PWM ΣDTC results q L = n L(φ L/2π). Fig. 8 shows the demonstration o PWM method; in the same manner as PPM DTC, PWM may not have any notable perormance on peak reduction, but it creates deep notches in certain bands pretty well, whose locations are given by eq.(3). notch = K s (3) m H m L where K = m H m L, m H m L 2,,. m H and m L are positive integers, deined as m H = τ H TC, 4.5. SSCG using PRJ ΣDTC m L = τ L TC. Finally, Fig. 9 illustrates sample signal o generated/modulated PRJDTC. We observe that this method is very eective in lowering system signals peaks and yields notch i careully designed. Set the pulse period corresponding to digital to be T L which is integer (n L) multiples o constant minimum base period (T C), and also design so that the pulse period corresponding to digital value arbitrarily alters between T H and T H2, which are integers (n H, n H2) multiples o T C. Then we ound that the notch requency locations are determined by eq.(4). where K = G, G 2,,. notch K( 4nL + p + q ) s (4) 4G Here G is the greatest common divisor between p and q and p = n H n L, q = n H2 n L. For the matter o completeness in Fig. 2 a compound method o PWMDTC + PRJDTC is shown. We notice the aect o PWM DTC in hammering signal high in side bands o the notches in Fig. 2a.

4 ΔΣ TDC 5. Conclusion ΔΣ ADC Time ΔΣ TDC Voltage ΔΣ ADC Time Voltage We have introduced and demonstrated proposed delta-sigma DTC methods which bring digital signal to timing signal. These ΔΣ DAC ΔΣ DAC ΔΣDTC methods are ully implementable only using digital circuitry with (a) suitability or higher requency circuits application. Their eectiveness and expected results have been veriied by computational simulations.we have also applied our proposed methods to easy and (b) Figure : Σ converters in time and voltage domains, and positioning o Σ DTC. yet practical spectrum spread clock generator. We expect that our proposed DTC methods will ind a lot o other applications in addition to SSCG. s Acknowledgment We would like to thank Koichi Hamashita and [Hz] Jun-ichi Matsuda or their kind support o this project.this research is supported by Adaptable and Seamless Technology Transer Pros gram through target-driven R&D, JST. s [Hz] v [Hz] Reerences [] R. Schreier, G. C. Temes, Understanding Delta-Sigma Data Converters, IEEE Press (25). [2] S. Uemori, M. Ishii, H. Kobayashi, Multi-Bit Digma-Delta TDC Architecture or Signal Timing Measurement, IEEE International Mixed-Signals, Sensors and Systems Test Workshop, Taipei (May 22). [3] H.G. Skinner, K. P. Slattery, Why Spread Spectrum Clocking o Computing Devices is not Cheating, IEEE International Symposium on Electromagnetic Compatibility, vol., pp , Montreal (Aug. 2). Figure 2: Spread spectrum technique. Input or ΔΣ Input or ΔΣ τp φ T=/ Figure 4: Pulse model used or Σ DTC modulation. [8] I. Mori, Y. Yamada, S. A. Wibowo, M. Kono, H. Kobayashi, Y. Fujimura, N. Takai, T. Sugiyama, I. Fukai, N. Onishi, I. Takeda, J. Matsuda, EMI Reduction by Spread-Spectrum Clocking in ly-controlled DC-DC Converters, IEICE Trans. Fundamentals, vole92-a, no.4, pp.4- (April 29). [] K. Chuai, S. Aouini, G. W. Roberts, A Low Cost ATE Phase Signal Generation Technique or Test Applications, IEEE International Test Conerence, pp.-, Austin (Nov. 2) Counter Figure 3: ΣDAC and Σ DTC analogy. [6] A. Kumar, P. Madaan, Reducing EMI in Systems Through Spread Spectrum Clock Generators, Cypress Semiconductor Corp Technical Report (Feb. 2). [] H. Sadamura, M. Namekata, M. Kono, H. Kobayashi, N. Ishikawa, EMI Reduction Technique o Switching Regularities and Its Measurement Veriication, IEICE Trans. vol. J86C, no., pp (Nov. 23) bit DTC Multi-bit One bit Resolution Resolution Timing Timing Signal Signal Asynchronous (b) Σ DTC coniguration. [5] SSCG Spread Spectrum Clock Generator, Fujitsu Semiconductor Corp Technical Report, AD4-4-4E (Oct. 2). [9] T. Daimon, H. Sadamura, T. Shindou, H. Kobayashi, M. Kono, T. Myono, T. Suzuki, S. Kawai, T. Daimon, H. Sadamura, T. Iijima, Spread-Spectrum Clocking in Switching Regulators or EMI Reduction, IEICE Trans. Fundamentals, vol. E86A, no. 2, pp (Feb. 23). Analog LPF Smoothed Analog Output (a) Σ DAC coniguration. [4] C. D. Hoekstra, Frequency Modulation o System Clocks or EMI Reduction, Hewlett-Packard Journal, no.3, pp.7(aug. 997). [7] M. Iijima, S. Miyata, Y. Miyazaki, K. Okada, T. Saitou, Spread Spectrum Clock Generation circuit, Jitter Generation Circuit and Semiconductor Device, U.S. Patent: US79526 B2 (26). bit DAC Pulse Density Analog Output Dout = Dout = τp τp Sout Sout T T 2T (a) Time signal representation or digital " & ". Dout() =, Dout() =, Dout(2) =, Dout(3) =, Dout(4) = T 2T 3T 4T 5T 6T 7T 8T Sout (b) Time signal o by represented by above time signals. Figure 5: PCMDTC Example

5 Input Generation circuit D in D out Σ PCM DTC Input Clk ΔΣ D in CLK (a) PCM ( Σ) DTC block diagram. Σ Buer Memory D out PCM DTC Figure : PWMDTC circuit block diagram. clkout Clock Generator D out = D out = (b) Alternative PCM ( Σ) DTC block diagram. T T 2T T 2T 3T Figure 6: PCMDTC circuit block diagram. D out = D out = (a) Time signal representation or digital high" and low". D out () =, D out () =, D out (2) =, D out (3) =, D out (4) = φ = φ = C T T (a) Time signal representation or digital " & ". D out () =, D out (2) =, D out (3)=, D out (4)=, D out (5)= T 2T 3T 4T 5T 6T 7T 8T (b) Time signal o represented by the above time signals. T 2T 3T 4T 5T S out (b) Time signal o represented by the above time signals. Input Figure 7: PPMDTC example. ΔΣ Clk τ MUX clkout Figure 8: PPMDTC circuit block diagram. Electric ield strength Input Clk Figure : PRJDTC example. ΔΣ PRPG Pseudo Random Pulse Generator nτ mτ MUX Figure 2: PRJDTC circuit block diagram. dτ Clk out D out = τ p =α D out = τ p =β Frequncy T T Figure 3: Typical System EMI Noise Spectrum (a) Time signal representation or digital " and ". D out () =, D out (2) =, D out (3)=, D out (4)=, D out (5)= Class A: Industrial Class B: Home T 2T 3T 4T 5T S out (b) Time signal o represented by the above time signals. Figure 9: PWMDTC example Figure 4: EMI power regulation.

6 66 db 67 db (67) (68) -37 db τl= τh=3 τl= τh=2 (a) τh = 2 Figure 5: Base peak power without DTC modulation. (b) τh = 3 66 db 6 db -43 db 49 db -48 db 5 db (49) (5) τl= τh=4 τl= τh=5-35 db TH= 6 TH τl= τh= =7 τl= τh= (a) TH = 6 (c) τh = 4 (d) τh = 5 Figure 8: Spreading clock power spectrum by various PWMDTCs. (b) TH = 7 5 db 5 db (5) (5) 5 db -38 db τl= TH= 8 τl= τh= (c) TH = 8 (5) TH= 9 τh= 49 db (52) -43 db τl= τh= (d) TH = 9 τl= J=2, 3, 4 τh= J=3, 4, 5, 6 (a) J = 2, 4 (b) J = 3, 6 Figure 6: Spreading clock power spectrum by various PCMDTCs. 54 db 52[dB] (52) τl= -3dB τl= τh= φl= τh= J=5, 6, 7, 8, 9, J=4, 5, 6,7, 8 τl= τl= τh= τh= φ=2 (c) J = 4, 8 (d) J = 5, Figure 9: Spreading clock power spectrum by various PRJDTCs. (a) qh = (b) qh = 2 49 db (63) -38 db (65) τl= τh= 5[dB] - 4 db φ=3 (c) qh = 3 τl= τh= -4 db - db φ=4 (d) qh = 4 Figure 7: Spreading clock power spectrum by various PPMDTCs. φ=2 τp= τh=5 J=2, 3, 4 (a) J = 2, 4 & τh = 5 τl= TH=5 τh=7 J=3, 4, 5, 6 (b) J = 3, 6 & τh = 7 Figure 2: Spreading clock power spectrum by PRJWMDTCs.