An All-Digital Direct Digital Synthesizer Fully Implemented on FPGA

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1 1 An All-Digital Direct Digital Synthesizer Fully Implemented on FPGA Hesham Omran, Khaled Shara, and Magdy Ibrahim Electronics and Communications Engineering Department Faculty o Engineering, Ain Shams University, Cairo, Egypt hesham.a.o@gmail.com Abstract In this paper an all-digital pulse put direct digital synthesizer (DDS) is described. The synthesizer is ully implemented on FPGA and does not require any external analog components. Selective over-sampling and tapped delay line are used to reduce jitter and improve spectral perormance. Selective over-sampling relaxes the requirements on the delay line with a minor eect on power consumption and circuit complexity. The delay line is implemented using the FPGA digital clock manager (DCM). The synthesizer generates clock signals with maximum put requency up to clk. It achieves sub-hz resolution and sub- s switching time. Experimental measurements validate system operation with spurious ree dynamic range (SFDR) greater than 40 db. Index Terms Direct digital synthesizer (DDS), ieldprogrammable gate array (FPGA), over-sampling, spurious ree dynamic range (SFDR). D I. INTRODUCTION IRECT digital synthesizer (DDS) is a popular technique or requency synthesis. It oers several advantages, including very ine tuning resolution and very ast switching speed [1]. A conventional DDS is shown in Fig. 1. The phase accumulator accumulates the requency control word (), also known as phase increment (PINC), with every rising edge o clk. The put o the accumulator is a saw-tooth wave, which is the sampled version o the sine wave phase. Every phase value is converted, usually ater truncation, to its corresponding sine wave amplitude. Several techniques or phase to amplitude conversion exist [2], [3]. The simplest one is using a look-up table (LUT). The digital samples rom the LUT are converted to analog voltage by the digital-to-analog converter (DAC). The sampled zero-order hold (ZOH) DAC put contains images o the put tone (multiplied by sinc unction), which requires steep low-pass iltering (LPF), and limits the maximum practical put requency to one-third o clk. Despite its name, DDS contains two analog blocks: DAC and LPF. The LPF is implemented by discrete components. DAC integration is possible, but it is a challenging task, especially with the continuous down-scaling o supply voltage in deep-submicron (DSM) technologies. The LUT, usually implemented as a read-only memory (ROM), and DAC represent two bottlenecks in terms o speed and power consumption. Several architectures were proposed to reduce the ROM size [2] [4]. Another approach is to eliminate the ROM by including the phase-to-amplitude conversion unction in the DAC. This ROM-less non-linear DAC DDS can operate in the GHz range, but with excessive power consumption [5], [6]. Fig. 1. Block diagram o conventional DDS. The accumulator put (N-bit) is truncated to P-bit phase word beore addressing the LUT. Both requency and phase inormation o DDS are completely stored in the phase accumulator. The phase accumulator put is shown in Fig. 2(a). From the igure we can deduce the simple relations that govern the operation o DDS [2] N 2 = T clk T = N clk (1) 2 clk N Δ = (2) 2 Where is the requency o the put signal and is the requency tuning resolution. II. PULSE OUTPUT DDS A. Time Domain Perspective Since DDS is a synchronous system, transitions occur only at rising clock edges. This means that zero-crossings are not accurate in the put o both the accumulator and the LUT. In conventional DDS, accurate zero-crossings are obtained by the LPF, which perorms interpolation in the amplitude domain as shown in Fig. 2(b). Another DDS architecture is the pulse put DDS [2], [7], [8], also known as phase interpolation DDS [9], [10]. This architecture relies on the act that the accumulator carry bit has the same average requency predicted by (1). But since /10/$ IEEE

2 2 transitions occur only at rising clock edges, this signal will suer rom unacceptable jitter as shown in Fig. 2(c). The accurate zero-crossing occurs at the instant when the accumulator reaches 2 N. I we can detect this instant by interpolating the accumulator put, we can trigger a pulse to achieve an accurate jitter-ree clock signal as shown in Fig. 2(d). Thus, interpolation is done in phase domain instead o amplitude domain. Fig. 3. Accumulator at the instant o overlow. maximum cycle-to-cycle jitter is reduced rom T clk to Fig. 2. Waveorms o DDS. (a) Accumulator put. (b) DAC and LPF put. (c) Accumulator carry bit. (d) Carry bit ater phase correction (put o pulse put DDS). Fig. 3 depicts the accumulator at the instant o overlow. I we can advance the carry bit rising edge by t d a jitter-ree clock is obtained. Since it is not possible to advance a signal in time, we can delay it by (T clk t d ) instead, noting that T clk delay applied to all edges has no eect on inal put. From the simple geometry o Fig. 3, we can deduce that t d is given by R t d = T clk (3) Where R is the residue in the accumulator ater overlow. Several techniques exist to achieve this variable delay. In an analog approach, the delay t d is generated by intersecting a ramp with a reerence voltage. This approach introduces more analog blocks than those already existing in conventional DDS, as two DACs and a comparator are required [11], [12]. In a digital approach, a divider and a digital-to-phase, or digital-to-time, converter (DPC or DTC) are used. Equation (3) is used to calculate a delay word (DW) according to the resolution o the DPC. I the DPC is D-bits then the delay word is given by [2] R D DW = ( 1 ). 2 (4) The DPC is usually implemented as a tapped delay line with a delay-locked loop (DLL) to lock the total line delay with the input clock period [8], [10], [13], [14]. In this case the T clk D [15]. The bottleneck o this approach is the maximum 2 number o taps that can be practically implemented. This number is limited by the implementation o the tap-select multiplexer and the unavoidable non-linearity eects in the delay line [8], [10]. Comparing the later approach with a conventional DDS, we can see a one-to-one correspondence. The phase to amplitude conversion (LUT) is replaced by phase to delay word conversion (divider) while the DAC is replaced by a DPC, i.e., analog signal is in phase domain instead o amplitude domain. But a delay line is easier to implement in a digital CMOS technology than a DAC. Other approaches to implement phase interpolation DDS were proposed [16], [17]. B. Frequency Domain Perspective Viewed in time domain we noticed that phase interpolation can reduce the jitter o the carry bit and produce a more accurate clock signal. A requency domain perspective shows that phase interpolation process is equivalent to over-sampling. Using a D-bit DPC is equivalent to using an eective clock rate e = clk 2 D [14]. To illustrate this, we begin with the spectrum o an ideal square wave o requency 31/256 MHz as shown in Fig. 4(a). The spectrum contains the undamental and its odd harmonics. Next, we generate the same requency using a DDS with N = 8, = 31, and clk = 1 MHz. Taking the put rom the MSB o the accumulator, or the carry bit ater T-FF, the square wave will have transitions only at rising edges o clk. This is equivalent to sampling the ideal square wave in Fig. 4(a) with a sampling requency clk. Fig. 4(b) shows that harmonics above clk /2 are olded back and orth in the region 0 clk /2, appearing as spurs, which degrade the SFDR. The spectrum repeats at multiples o clk as in any sampled system (practically multiplied by sinc unction due to ZOH characteristics). Now, we introduce phase interpolation with a 2-bit delay word. This means we have our valid transition instants within each cycle o clk, i.e., the eective

3 3 Magnitude (dbfs) Magnitude (dbfs) Magnitude (dbfs) Frequency (Hz) x sampling requency is now e = clk 4 = 4 MHz. This is conirmed by Fig. 4(c) where the sampling requency is clearly increased to e = 4 MHz and olding happens at e /2 instead o clk /2. Thus, the harmonics olded back as spurs will have smaller magnitudes than case (b), i.e., SFDR is improved. In addition, images appear at multiples o e instead o clk, which relaxes the requirements on LPF. From the above argument, a simple expression to estimate SFDR can be deduced [14]. Let the largest harmonic olded back between the undamental and its 2 nd harmonic be o order k with magnitude 1/k, then e < e k < 2 k = 1 D 1 e 2 clk SFDR = 20log 20log = 20log 1/ k clk SFDR 6D + 20log ( db) (5) Where denotes truncation. Thus each bit in the delay word introduces a 6 db improvement in SFDR. III. SYSTEM DESCRIPTION Fig. 5 shows a simpliied block diagram o the system. An over-sampling clock ( OV ) o 100 MHz is available as input, then it is internally divided by 16 to produce 6.25 MHz system clock ( clk ). Fundamental Harmonics Spurs Frequency (Hz) x Frequency (Hz) x 10 6 Fig. 4. Spectra o square wave (simulation results). (a) Ideal square wave. (b) MSB o accumulator. (c) MSB ater phase correction with a 2-bit delay word. A. Accumulator and Divider A 24-bit accumulator is used. This allows a tuning resolution o Hz as given by (2). The divider is implemented as a simple restoring divider [18]. A nonpipelined version is used to enable aster switching speed. The quotient o the divider is a 6-bit delay word (DW) given by R D DW = 2 (6) Where D = 6. The our most signiicant bits are used with selective over-sampling while the two least signiicant bits select one o the our phases rom the digital clock manager (DCM). B. Phase Interpolation The most trivial way to reduce jitter and increase SFDR o pulse put DDS is to increase its sampling clock. But this means excessive power consumption and tighter timing constraints or all blocks. In addition, to maintain the same requency resolution given by (2), the accumulator width must by increased as well. In selective over-sampling, the DDS is clocked at the normal system clock ( clk ), while an oversampling clock ( OV ) is used selectively to reduce jitter and increase SFDR. This has minor impact on power dissipation and design complexity, while providing signiicant improvement in system perormance. Phase interpolation is done in two stages. The irst stage uses selective over-sampling, where OV = clk 16. This stage relaxes the requirements on the tapped delay line, i.e., with selective over-sampling a 64-tap delay line is required to produce the same jitter/sfdr improvement, which can not be implemented on an FPGA. Instead o using a 16-to-1 multiplexer to select the correct edge o the over-sampling clock [14], a simple 4-bit counter is used. The counter is loaded with DW(5:2) and incremented at every rising edge o OV. When counter reaches ull scale (0xF), a single-period pulse is generated, which is used as a window in the next phase interpolation stage. Pre-loading the counter with DW(5:2) simpliies the design as only a comparator to a constant is implemented. Otherwise, a ull comparator is required, which requires substantially more gates. The counter is loaded and incremented to generate the window pulse within a single period o clk, which allows synthesis o clock requencies up to clk with timing problems. A DCM is used in the second stage. The DCM provides our phases o the over-sampling clock ( OV ) [19] acting as a 4-tap delay line. DW(1:0) is used to select one o the our edges alling within the window pulse rom the irst stage. The put ( ) has a small pulse width (1/ OV ), which can be modiied using T-FF or one shot pulse generator. IV. SIMULATION RESULTS Fig. 6 shows VHDL simulation results or clk = 6.25 MHz. For the purpose o clarity the igure is drawn or an oversampling ratio o 4 instead o 16 and only 4-bit delay word. For the given case, (PINC) = 0xB, which gives = MHz, greater than clk /2. The carry bit cannot be used to generate this requency as it is sampled at clk. The

4 4 Fig. 5. Simpliied block diagram o the system. WE and CE stands or Write Enable and Clock Enable respectively. Fig. 6. VHDL timing simulation or (PINC) = 0xB. (Figure is drawn or N = 4 and 4-bit DW or the purpose o clarity). latency o the system is only 4 clock cycles, which enables very ast requency switching speed. V. EXPERIMENTAL RESULTS A. Implementation Details The system was implemented on Xilinx Virtex-II Pro FPGA (XC2VP30). Device utilization summary is given in Table I. Global clock network is used or ring all the clocks in the system to minimize skew. More optimization can be done to reduce the utilization. The divider can be implemented using a more eicient architecture and the clock division rom OV to clk can be implemented using a simple counter instead o using another DCM. TABLE I DEVICE UTILIZATION (XC2VP30-7FF896) Resource Used Available Utilization Slice Flip Flops 71 27,392 1% Total 4-input LUTs ,392 1% Global Clocks (GCKs) % DCMs % Equivalent Gate Count 17,626 B. Measurement Results Fig. 7(a) compares the put waveorms o the jittery carry bit and the phase interpolated DDS put. Both waveorms are drawn ater T-FF to get 50% duty cycle. Fig. 7(b) illustrates the ast switching speed o the circuit, where a new is supplied at the input o the DDS, and then WE is asserted. is switched rom 2.43 MHz to 5.3 MHz in less than 1 s. In Fig. 8 the spectrum o the carry bit is compared to the spectrum o the DDS put. SFDR is calculated with respect to the highest spur between the undamental and the 2 nd harmonic. For put requency 550 khz the carry bit has SFDR 22 db, whereas DDS put has SFDR 56 db, giving a 34 db improvement. Fig. 9 shows put spectrum or 1.21 MHz and 2.64 MHz, with SFDR 50 and 44 db respectively. Fig. 10 shows that approximate ormula in (5) provides a very good match to measured data. Table II summarizes the perormance o this work. VI. CONCLUSION An all-digital DDS with sub-hz resolution and sub- s switching time has been presented. The DDS is ully implemented on FPGA; it does not need external DAC or delay-line. The design is suitable as a parameterized drop-in

5 5 (a) (a) Fundamental 3 rd harmonic (b) Fig. 7. Time-domain measurements. (a) The carry bit (upper) and DDS put (lower) or = 0x ( = 2.43 MHz). (b) WE (upper) and DDS put (lower) showing requency switching rom = 0x ( = 2.43 MHz) to = 0xD91687 ( = 5.3 MHz). Both carry bit and DDS put are measured ater T-FF. module in FPGAs. With an ASIC implementation, the design can operate at much higher requencies. The perormance can be urther improved using noise shaping techniques. Highest spur ACKNOWLEDGMENT The authors thank the members o OFDM Project team or providing the FPGA kit. REFERENCES [1] Analog Devices, Inc., A Technical Tutorial on Digital Signal Synthesis, Application Note, [2] Jouko Vankka, Digital Synthesizers and Transmitters or Sotware Radio, Springer, [3] J.M.P. Langlois and D. Al-Khalili, Phase to sinusoid amplitude conversion techniques or direct digital requency synthesis, IEE Proc.-Circuits, Devices, and Systems, vol. 151, no. 6, December [4] A. G. M. Strollo, D. De Caro, and N. Petra, A 630 MHz, 76 mw Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique, IEEE Journal o Solid-State Circuits, vol. 42, no. 2, February [5] Yu Xueeng, F. F. Dai, J. D. Irwin, and R. C. Jaeger, A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18-μm SiGe BiCMOS Technology, IEEE Journal o Solid-State Circuits, vol. 43, no. 6, June [6] Zhihe Zhou and George S. La Rue, A 12-Bit Nonlinear DAC or Direct Digital Frequency Synthesis, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 9, October [7] Bar-Giora Goldberg, Digital Frequency Synthesis Demystiied, LLH Technology Publishing, (b) Fig. 8. Spectrum o (a) carry bit and (b) DDS put or = 0x2D0E56 ( 1.1 MHz). Both carry bit and DDS put are measured ater T-FF. [8] R. Richter and H. -J. Jentschel, A virtual clock enhancement method or DDS using an analog delay line, IEEE Journal o Solid-State Circuits, vol. 36, no. 7, July [9] A. Yamagishi, H. Nosaka, M. Muraguchi, and T. Tsukahara, A phaseinterpolation direct digital synthesizer with an adaptive integrator, IEEE Transactions on Microwave Theory and Techniques, vol. 48, no. 6, June [10] F. Baronti, L. Fanucci, D. Lunardini, R. Roncella, and R. Saletti, A high-resolution DLL-based digital-to-time converter or DDS applications, IEEE International Frequency Control Symposium and PDA Exhibition, [11] J. Nieznanski, An alternative approach to the ROM-less direct digital synthesis, IEEE Journal o Solid-State Circuits, vol. 33, no. 1, January [12] H. Nosaka, Y. Yamaguchi, A. Yamagishi, H. Fukuyama, and M. Muraguchi, A low-power direct digital synthesizer using a seladjusting phase-interpolation technique, IEEE Journal o Solid-State Circuits, vol. 36, no. 8, August 2001.

6 6 60 Analytical Measured 55 SFDR (db) / clk Fig. 10. Comparison o measured data with the approximate ormula in (5). (a) Implementation Clock requency ( clk) No. o interpolation levels (2 D ) 64 Technique Eective clock ( e) Maximum put requency Resolution ( ) Switching speed TABLE II PERFORMANCE SUMMARY FPGA (XC2VP30) 6.25 MHz Selective over-sampling & delay line 400 MHz clk Hz 0.64 μs SFDR up to clk/2 > 40 db (see Fig. 10) (b) Fig. 9. Spectrum o DDS put or (a) = 0x ( 2.43 MHz) and (b) = 0xD91687 ( 5.3 MHz). Both measured ater T-FF. [13] T. Rahkonen and H. Eksyma, A 3-V programmable clock generator with a built-in phase interpolator, Midwest Symposium on Circuits and Systems, [14] A. Heiskanen, A. Mantyniemi, and T. Rahkonen, A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dbc spurious level, IEEE International Symposium on Circuits and Systems, [15] A. M. Fahim, Low-power, low-jitter direct digital synthesizer with analog interpolation, Proceedings o the 2004 IEEE International Frequency Control Symposium and Exposition, [16] T. Finateu et al., A 500-MHz Phase-Interpolation Direct Digital Synthesizer, IEEE Asian Solid-State Circuits Conerence, [17] U. Meyer-Base, S. Wol, and F. Taylor, Accumulator Synthesizer with Error-Compensation, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 7, July [18] J. -P. Deschamps, G. J. A. Bioul, and G. D. Sutter, Synthesis o Arithmetic Circuits: FPGA, ASIC and Embedded Systems, Wiley, [19] Xilinx, Inc., Virtex-II Pro and Virtex-II Pro X FPGA User Guide, UG012 (v4.2), November 2007.