ASIC Design and Implementation of a Novel Arbitrary Function Generator Using Orthogonal Functions

Transcription

1 Advance in Electronic and Electric Engineering. ISSN , Volume 4, Number 1 (2014), pp. 1-8 Research India Publications ASIC Design and Implementation of a Novel Arbitrary Function Generator Using Orthogonal Functions A. Abbasi 1, SA. Abbasi 2, A.R.M. Alamoud 3 and S.A. Loan 4 1,2,3 Department of Electrical Engineering, College of Engineering, King Saud University, Riyadh 11421, SAUDI ARABIA. 4 Department of Electronics and Com. Engineering, Jamia MilliaIslamia, New Delhi , INDIA. 1 aabbasi@ksu.edu.sa, 2 abbasi@ksu.edu.sa, 3 alamoud@ksu.edu.sa, 4 sajadiitk@gmail.com Abstract Arbitrary function generators often known as Arbitrary Waveform Generators (AWGs) are becoming increasingly important for many military and commercial applications. Many approaches for design and fabrication of AWGs are used. However, all of them suffer from various drawbacks and are therefore not acceptable for all application. A novel approach has therefore been attempted for generating arbitrary waveforms using orthogonal functions. The orthogonal functions, specially the Rademacher and Walsh functions are being increasingly used by engineers for various Digital Signal Processing (DSP) applications since such applications require fast processing time in order to meet the challenges of the real time systems. A set of Rademacher and Walsh Functions has been used to develop a standalone arbitrary function generator. The design is targeted to the stateof-the-art Cell Based Integrated Circuits (CBIC) technology. High level design techniques are used with the help of advanced EDA tools from SYNOPSYS International. Optimized VHDL models have been developed and used for design entry. The design is thoroughly verified using advanced verifications tools. The design is implemented and processing has been done with 90nm CMOS Technology from TSMC foundry. The simulation, design and implementation results are presented It is observed that the results obtained, are far better than the results reported earlier in the literature.

2 2 A. Abbasi et al Keywords: ASIC; CBIC; rademacher functions, walsh functions, arbitrary waveform generator. 1. Introduction Arbitrary waveforms are used in a wide range of applications in many commercial and military fields (Tie-Liang and Yu-lin, 2001).Many possibilities for Arbitrary WaveformsGeneration (AWG) are open to a designer, ranging from Phase-Locked- Loop (PLL)-based techniques (Larsen, 1998) for very high-frequency synthesis, to dynamic programming of Digital-to-Analog Converter (DAC) outputs (Vankka, 1997) to generate arbitrary waveforms at lower frequencies. The Direct Digital Frequency synthesizers are widely used in many communications and measurement systems. The technique, however, required large ROM and was more complex than even simple sinusoids. Another technique known as Direct Digital Synthesis (DDS) is alsobeing used to synthesize AC signals for instrumentation, and digital communications (Kroupa et al., 2000; Hsieh et al. 2003). This technique is based on the Shannon s sample theory and its basic principle is to convert the waveform s sampled discrete value to analog signal using DAC (digital-analog converter).(vankka, 1997)presented the design of a Direct Digital Synthesizer (DDS) with an on-chip D/A converter fabricated with 0.8-µm BiCMOS technology. This design made improvements and reduced delays and line loading caused by interchip connections. However, the DDS technique still suffered from drawbacks such as a large set of the spurious signals.another scheme of AWG which contains many multi-level converters has been presented by (Yunping and Lijun, 2000). This technique was more useful for power applications. A prototype of a single chip AWG was presented by (Tie-Liang and Yulin, 2001)and it was implemented on a Virtex-E FPGA but suffers from the drawbacks of being very complex and expensive. (Hsiehet al, 2003) used FPGAs to implement an n-channel AWG with various add-on functions. (Baronti, et al, 2002) described a Digital-to-Time Converter (DTC) based on a Delay-Locked Loop (DLL) for phase interpolation in Direct Digital Synthesis (DDS) applications. The conversion is made in two steps using digitally controllable delay cells with configurable shunt-capacitors load. The circuit is able to interpolate a 120 MHz clock, generating a delay proportional to an 8-bit digital control word with 32 ps resolution. The DDS system clock frequency is thus virtually enhanced up to about 30 GHz, achieving a strong reduction of the spurious component level. The 256 levels interpolation is achieved using only 35 delay elements (excluding dummy cells). (Langlois and Al-Khalili, 2004) presented a review of phase to sine amplitude conversion (PSAC) techniques for direct digital frequency synthesis (DDFS). Principles of DDFS are first considered, and then approaches for the reduction of system complexity are identified. It is shown that the basic problem for the design of the phase to sine amplitude converter, whether the system has single phase or quadrature outputs, is the reproduction of an approximated sine function for first quadrant angles. The state of the art in PSAC design is then reviewed following a systematic classification of techniques, namely angular decomposition, angular rotation, sine amplitude compression, polynomial

3 ASIC Design and Implementation of a Novel Arbitrary Function Generator Using 3 approximation, and analogue approaches. (Torres-Company et al, 2006) presented an all-incoherent technique for the generation of arbitrary electromagnetic intensity profiles. It is based on spectral filtering of a broadband continuous-wave light source so that the filtered spectral density function (SDF) becomes the user-defined waveform. After large temporal modulation and subsequent distortion in a first-order dispersive medium, the incoherent mapping of the filtered SDF to the time domain occurs. Optical-to-electrical conversion in a fast photodiode allows the optical intensity to be mapped into the electrical domain. It has however, been observed that none of the techniques available so far are entirely satisfactory and hence there is a need to use a new approach.it has been shown earlier(abbasi and Alamoud, 2005) that well known orthogonal functions viz. the Rademacher functions and Walsh functions may be used to generatearbitrary signals. It has been demonstrated that virtually any periodic signal can be synthesized. A detailed theoretical analysis along with the isolated generation of some signals has been presented.in the present work, the above technique is extended and used to design, implement and prototype an arbitrary signal generator which can be used to generate any arbitrary signal with a single hardware. This has been done by incorporating the generation of expansion coefficients in the hardware itself rather than relying upon MATLAB based calculations as is done in (Abbasi and Alamoud, 2005; Abbasi and Qasim, 2006). This has resulted in a truly stand-alone arbitrary waveform generator. The rest of the paper is organized as follows. Section 2 discusses the new technique of arbitrary signal generation using orthogonal functions.thehigh level design of arbitrary signal generation is described in section 3. The implementation is discussed in section 4. Results and Discussions are given in section 5. Conclusions are presented in section The New Technique for Arbitrary Signal Generation An attempt at hardware realization of Rademacher functions and Walsh functions and the generation of digital and analog sinusoidal waveforms was described by (Bin Ateeq, et al, 2002). The Rademacher and Walsh functions are a set of discrete valued functions that can be reduced to modulo-2 addition. These functions have received increasing attention in recent years in a variety of engineering areas such as communication, signal processing, system analysis, and control (Tie-Liang and Yu-lin, 2001). Walsh functions take only two amplitude values, +1 and -1 and hence can be represented as binary signals.it is possible to formulate Walsh series expansion for functions of periodic characteristics given by (Bin Ateeq, et al, 2002): f(x) A 0 ψ(0,x) + A 1 ψ(1,x) + A 2 ψ(2,x) + (1) where, f(x) is the desired function to be generated. The expansion coefficients A n are calculated as: 1 A n = f(x)ψ(n,x)dx 0 (2)

4 4 A. Abbasi et al Using the above equations, any digital periodic signalcan be generated by the following steps: 1. Determination of Expansion coefficients 2. Generation of the Rademacher functions 3. Generation of Walsh functions 4. Generation of periodic signals using expansion coefficients 3. High Level Design of Arbitrary Signal Generation The Very High Speed Hardware Description Language (VHDL) has been used for design. The important steps in VHDL coding are described below. 4.1 Generation of Rademacher and Walsh functions We have observed that the Rademacher functions may be realized as the output at various stages of a Binary Counter. This greatly simplifies the generation of Rademacher functions and hence this technique has been used for the realization of these functions instead of the direct realization as suggested by the mathematicians. The Walsh functions are computed as products of Rademacher functions (Golubov et al, 1991), based on the gray code conversion of the Walsh function index sequence, as given below. ψ(n, x) = [φ(i + 1, x)] n {0,1}wheren = 2 n Since the Walsh functions are two-level signals, positive (+1) and negative (-1), they can be easily implemented in digital form. It may be seen that by replacing the value +1 by binary 0 and 1 by binary 1, multiplication is replaced by the XOR operation. 4.2 Calculation of expansion coefficients The snippet of the VHDL code for generation of first two expansion coefficients is given below. A0<=F(1)+F(2)+F(3)+F(4)+F(5)+F(6)+F(7)+F(8)+F(9)+F(10)+F(11)+F( 12)+F(13)+F(14)+F(15)+F(16)+F(17)+F(18)+F(19)+F(20)+F(21)+F(22) +F(23)+F(24)+F(25)+F(26)+F(27)+F(28)+F(29)+F(30)+F(31)+F(32); A1<=F(1)+F(2)+F(3)+F(4)+F(5)+F(6)+F(7)+F(8)+F(9)+F(10)+F(11)+F( 12)+F(13)+F(14)+F(15)+F(16)-F(17)-F(18)-F(19)-F(20)-F(21)-F(22)- F(23)-F(24)-F(25)-F(26)-F(27)-F(28)-F(29) -F(30)-F (31)-F(32); The complete VHDL code for the arbitrary signal generator was written on the basis of the process mentioned above. Initially a simple form of VHDL code was written. It was then iterated many times to produce a superior code.

5 ASIC Design and Implementation of a Novel Arbitrary Function Generator Using 5 4. Implementation The design of the AWG is targeted to 90nm CMOS LP (Low Power) HVT (High Threshold Voltage) technology from TSMC. In this technology, 9 metal layers fabrication process is adopted. The odd numbered metal layer are used for horizontal connections and even numbered for vertical connections. Metal layer 1 is used for standard cells placement, Metal layer 2 for vertical clock and signal routing, Metal layer 3 for horizontal clock and signal routing. Metal layer 4 to Metal layer 9 aremainly used for power and ground straps. However, some of the signal routing also occurs from Metal layer 4 to Metal layer 7 to avoid DRC errors. Metal layer 8 and 9 are specifically for power mesh, which is connected to the power ring. Power Mesh is also connected to the Metal layer 1 through Vias. 5. Results and Discussions Any number of terms may be used for Walsh series approximation. Larger the number of terms used, higher the accuracy at the expense of more hardware. The 32-term Walsh series approximation with 32 samples per period has been found to give fairly accurate results and has been selected for demonstration purposes. In all of the cases, the error was found to be zero. This is the advantage of direct digital realization. If the analog version of the signals is to be generated, the results will have only the quantization error. This error may be further reduced, if necessary, by taking a larger number of samples at the expense of more hardware. The Power analysis shows the total dynamic power to be 7.536mW. Total area for this implementation is 194 mm 2 out of which 154 mm 2 is dedicated to core area where all the routing and standard cells are placed. Rest of the 40 mm 2 is used for I/O Ports cells, and power ring. Design is verified behaviorally, after performing Layout design. Delays are measured at different instances of the clock. Maximum delay, through timing analysis is found to be 5.11ns. This is far better than the previously claimed results of 9.5 ns. Fig. 1 shows the input to the synthesized net list and Fig. 2 shows the output waveform. Fig. 1: Input to the synthesized net list.

6 6 A. Abbasi et al Fig. 2: Output waveform of the synthesized net-list. 6. Conclusion The design and implementation of a novel stand-alone arbitrary waveform/signal generator is described. The technique implemented is based upon the use of orthogonal functions for the synthesis of digital signals and takes the advantage of ease of implementation with high level design techniques and excellent performance of the state-of-the-art CBIC technology. It was observed that with this technique, any periodic digital signal can be generated with a single hardware and thus the arbitrary signal generation system is stand-alone and doesn t require the support of any computer hardware or software like MATLAB, as was needed in earlier attempts. The implementation is targeted to 90nm CMOS LP (Low Power) HVT (High Threshold Voltage) technology from TSMC in which, 9 metal layers fabrication process is adopted. 7. Acknowledgements The authors gratefully acknowledge the financial supportfrom National Plan for Science, Technology and Innovation (NPST), Saudi Arabia under project no. 11-NAN

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