QAN19 Modulating Direct Digital Synthesizer in a QuickLogic FPGA

Transcription

1 DDS Overview DDS Block Diagram QAN19 Modulating Direct Digital Synthesizer in a QuickLogic FPGA In the pursuit of more complex phase continuous modulation techniques, the control of the output waveform becomes increasingly more difficult with analog circuitry. In these designs, using a non-linear digital design eliminates the need for circuit board adjustments over yield and temperature. A digital design that meets these goals is a Direct Digital Synthesizer DDS. A DDS system simply takes a constant reference clock input and divides it down a to a specified output frequency digitally quantized or sampled at the reference clock frequency. This form of frequency control makes DDS systems ideal for systems that require precise frequency sweeps such as radar chirps or fast frequency hoppers. With control of the frequency output derived from the digital input word, DDS systems can be used as a PLL allowing precise frequency changes phase continuously. As will be shown, DDS systems can also be designed to control the phase of the output carrier using a digital phase word input. With digital control over the carrier phase, a high spectral density phase modulated carrier can easily be generated. This article is intended to give the reader a basic understanding of a DDS design, and an understanding of the spurious output response. This article will also present a sample design running at 45MHz in a high speed field programmable gate array from QuickLogic. A basic DDS system consists of a numerically controlled oscillator (NCO) used to generate the output carrier wave, and a digital to analog converter (DAC) used to take the digital sinusoidal word from the NCO and generate a sampled analog carrier. Since the DAC output is sampled at the reference clock frequency, a wave form smoothing low pass filter is typically used to eliminate alias components. Figure 1 is a basic block diagram of a typical DDS system design. The generation of the output carrier from the reference sample clock input is performed by the NCO. The basic components of the NCO are a phase accumulator and a sinusoidal ROM lookup table. An optional phase modulator can also be include in the NCO design. This phase modulator will add phase offset to the output of the phase accumulator just before the ROM lookup table. This will enhance the DDS system design by adding the capabilities to phase modulate the carrier output of the NCO. Figure 2 is a detailed block diagram of a typical NCO design showing the optional phase modulator Dan Morelli, VP of Engineering Accelent Systems Inc. 8 Application Notes

2 FIGURE 1: Typical DDS System. Optional Phase Word Phase Word Write Strobe Frequency Word Frequency Word Write Strobe Phase Accum NCO Phase Mod Sin ROM Table Sin Output Sample CLK Digital to Analog Converter Analog Output Anti-Alias Low Pass Filter Sample CLK Input FIGURE 2: Typical NCO Design. Optional Phase Word (Y-1:0) Phase Word Write Strobe Synchronous Load Frequency Word (N-1:0) Frequency Word Write Strobe Synchronous Load N Phase Accumulator Register Y Optional phase adder for phase modulation Sinusoidal ROM Lookup Table Sin Output (D-1:0) To better understand the functions of the NCO design, first consider the basic NCO design which includes only a phase accumulator and a sinusoidal ROM lookup table. The function of these two blocks of the NCO design are best understood when compared to the graphical representation of Euler s formula e jωt = cos(ωt) + jsin(ωt). The graphical representation of Euler s formula, as shown in Figure 3, is a unit vector rotating around the center axis of the real and imaginary plane at a velocity of ω rad/s. Plotting the imaginary component versus time projects a sine wave while plotting the real component versus time projects a cosine wave. The phase accumulator of the NCO is analogous, or could be considered, the generator of the angular velocity component ω rad/s. The phase accumulator is loaded, synchronous to the reference sample clock, with an N bit frequency word

3 This frequency word is continuously accumulated with the last sampled phase value by an N bit adder. The output of the adder is sampled at the reference sample clock by an N bit register. When the accumulator reaches the N bit maximum value, the accumulator rolls over and continues. Plotting the sampled accumulator values versus time produces a saw tooth wave form as shown below in Figure Troll = = Fout FW( N 10 : ) Fclk N * 2 Where Troll is the phase accumulator rollover period Fout is the DDS system output carrier frequency Fclk is the reference sample clock frequency FW(N-1:0) is the frequency word input value and the frequency granularity is FW(N-1:0)/2 N The sampled output of the phase accumulator is then used to address a ROM lookup table of sinusoidal magnitude values. This conversion of the sampled phase to a sinusoidal magnitude is analogous to the projection of the real or imaginary component in time. Since the number of bits used by the phase accumulator determines the granularity of the frequency adjustment steps, a typical phase accumulator size is 24 to 32 bits. Since the size of the sinusoidal ROM table is directly proportional to the addressing range, not all 24 or 32 bits of the phase accumulator are used to address the ROM sinusoidal table. Only the upper Y bits of the phase accumulator are used to address the sinusoidal ROM table, where Y < N bits and Y is typically but not necessarily equal to D, and D is the number of output magnitude bits from the sinusoidal ROM table. FIGURE 3 Euler s Equation Represented Graphically ω π 2π 2 N Troll Phase Time 8 Application Notes

4 DDS Design Considerations Since an NCO outputs a carrier based on a digital representation of the phase and magnitude of the sinusoidal wave form, designers have complete control over frequency, phase, and even amplitude of the output carrier. By adding a phase port and a phase adder to the basic NCO design, the output carrier of the NCO can be M array phase modulated where M equals the number of phase port bits and where M is less than or equal to the Y number of bits used to address the sinusoidal ROM table. For system designs that require amplitude modulation such as QAM, a magnitude port can be added to adjust the sinusoidal ROM table output. Note that this port is not shown in Figure 2 and that this feature is not demonstrated in the sample QuickLogic FPGA design. Finally, frequency modulation is a given with the basic NCO design. The frequency port can directly adjust the carrier output frequency. Since frequency words are loaded into the DDS synchronous to the sample clock, frequency changes are phase continuous. Although DDS systems give the designer complete control of complex modulation synthesis, the representation of sinusoidal phase and magnitude in a non-linear digital format introduces new design complexities. In sampling any continuous-time signal, one must consider the sampling theory and quantization error. To understand the effects of the sampling theory on a DDS system, it is best to look at the DDS synthesis processes in both the time and frequency domain. As stated above, the NCO generates a sinusoidal wave form by accumulating the phase at a specified rate and then uses the phase value to address a ROM table of sinusoidal amplitude values. Thus, the NCO is essentially taking a sinusoidal wave form and sampling it with the rising or falling edge of the NCO input reference sampling clock. Figure 4 shows the time and frequency domain of the NCO processing. Note that this representation does not assume quantization. Based on the loaded frequency word, the NCO produces a set of amplitude output values at a set period. The frequency domain representation of this sinusoid is an impulse function at the specified frequency. The NCO, however, outputs discrete digital samples of this sinusoid at the NCO reference clock rate. In the time domain, the NCO output is a function of the sampling clock edge strobes multiplied by the sinusoid wave form producing a train of impulses at the sinusoid amplitude. In the frequency domain, the sampling strobes of the reference clock produce a train of impulses at frequencies of K times the NCO clock frequency where K = , 0, 1, 2... Since the sampling clock was multiplied by the sinusoid in the time domain, the frequency domain components of the sinusoid and the sampling clock need to be convolved to produce the frequency domain representation of the NCO output

5 The frequency domain results are the impulse function at the fundamental frequency of the sinusoid and the alias impulse functions occurring at K times the NCO clock frequency plus or minus the fundamental frequency. The fundamental and alias component occur at: K*Fclk - Fout K*Fclk + Fout Where K =... -1, 0, 1, 2... and K = 0 is the NCO sinusoid fundamental frequency Fout is the specified NCO sinusoid output frequency Fclk is the NCO reference clock frequency FIGURE 4 NCO Output Representation Time and Frequency Domain T F(ω) s(t) = δ(t-nts) f(t) = sin(2πt/t) S(ω) 2π/T -4Ts -3Ts -2Ts -Ts Ts 2Ts 3Ts 4Ts 2π/Ts 4π/Ts Fnco(ω) = F(ω) * S(ω) fnco(t) = f(t) x s(t) 2π/T 2π/Ts -2π/T 2π/Ts+2π/T The DAC of the DDS system takes the NCO output values and translates these values into analog voltages. Figure 4 shows the time and frequency domain representations of the DAC processing starting with the NCO output. The DAC output is a sample and hold circuit that takes the NCO digital amplitude words and converts the value into an analog voltage and holds the value for one sample clock period. The time domain plot of the DAC processing is the convolution of the NCO sampled output values with a pulse of one sample clock period. The frequency domain plot of the sampling pulse is a sin(x)/x function with the first null at the sample clock frequency. Since the time domain was convolved, the frequency domain is multiplied. This multiplication dampens the NCO output with the sin(x)/x envelope. This attenuation at the DAC output can be calculated as follows and a sample output spectrum is shown in Figure 5: Application Notes

6 Atten(F) = 20log[(sin(πF/Fclk)/πF/Fclk)] Where F is the output frequency Fclk is the sample clock frequency FIGURE 5: DAC Output Representation in Time and Frequency Domain F(ω) Fnco(ω) = F(ω) * S(ω) fnco(t) = f(t) x s(t) -4Ts -3Ts -2Ts -Ts Ts 2Ts 3Ts 4Ts d(t) Ts D(ω) 2π/T 2π/Ts -2π/T 2π/Ts+2π/T 2π/Ts 4π/Ts fdac(t)=fnco(t)*d(t) Fdac(ω) = Fnco(ω) * D(ω) 2π/T 2π/Ts -2π/T 2π/Ts+2π/T Aside from the sampling theory, the quantization of the real values into digital form must also be considered in the performance analysis of a DDS system. The spurious response of a DDS system is primarily dictated by two quantization parameters. These parameters are the phase quantization by the phase accumulator and the magnitude quantization by the ROM sinusoidal table and the DAC. As mentioned above, only the upper Y bits of the phase accumulator are used to address the ROM lookup table. It should be noted, however, that using only the upper Y bits of the phase accumulator introduces a phase truncation. When a frequency word containing a non-zero value in the lower (N-Y-1:0) bits is loaded into the DDS system, the lower non-zero bits will accumulate to the upper Y bits and cause a phase truncation. The frequency at which the phase truncation occurs can be calculated by the following: Ftrunc = FW(N-Y- 1:0)/2 N-Y * Fclk. A phase truncation will periodically (at the Ftrunc rate) phase modulate the output carrier forward 2π/2 8 to compensate for frequency word granularity greater than 2 Y. The phase jump caused by the accumulation of phase truncated bits produces spurs around the fundamental

7 These spurs are located plus and minus the truncation frequency from the fundamental frequency and the magnitude of the spurs will be - 20log(2 Y )dbc. A sample output of a phase truncation spur is shown in Figure 5. In a typical NCO design, the ROM sinusoidal table will hold a ¼ sine wave (0, π/2) of magnitude values. The ROM table is generated by taking all possible phase value addresses and map to a real magnitude sine value rounded to the nearest D bits. Thus, the maximum error output is ±- ½ LSB giving a worst case spur of -20log(2 D )dbc. Like the NCO ROM table, a DAC quantizes the digital magnitude values. A DAC, however, outputs an analog voltage corresponding to the digital input value. When designing the NCO sinusoidal ROM table, one should take some empirical data on the DAC linearity to better understand the interaction between the ROM table and the DAC. The quantization for a DAC is specified against an ideal linear plot of digital input versus analog output. Two linearity parameters, differential and integral linearity, are used to specify a DAC s performance. Differential linearity is the output step size from bit to bit. A DAC must guarantee a differential linearity of a maximum 1 LSB. When an input code is increased, the DAC output must increase. If the DAC voltage does not increase versus an increase digital input value, the DAC is said to be missing codes. Thus, a 10 bit DAC that has a differential linearity of greater that 1 LSB is only accurate to 9 or less bits. The number of accurate output bits will specify the DDS spurious performance as -20log(2 dl ) where dl is the number differential linear bits.. Integral linearity is a measure of the DAC s overall linear performance versus an ideal linear straight line. The straight line plot can be either a best straight line where DC offsets are possible at both the min and max outputs of the DAC, or the straight line can cross the end points of the min and max output values. A DAC will tend to have a characteristic curve that is traversed over the output range. Depending on the shape and symmetry (symmetry about the half way point of the DAC output) of this curve, output harmonics of the DDS fundamental output frequency will be produced. As these harmonics approach and cross the Nyquist frequency of Fclk/2, the harmonics become under sampled and reflect back into the band of interest, 0 to Fclk/2. This problem is best illustrated by setting the NCO output to Fclk/4 plus a slight offset. The third harmonic will fall minus 3 folds the small offset from the fundamental and the second harmonic will cross the Nyquist frequency by 2 folds the small offset leaving a reflected image back in the band of interest A sample plot of this frequency setup is shown in Figure Application Notes

8 DDS Design Example in an FPGA Other DAC characteristic that will produce harmonic distortion is any disruption of the symmetry of the output wave form such as a different rise and fall time. These characteristics can typically be corrected by board components external to the DAC such as an RF transformer, board layout issues, attenuation pads etc. Given the complexities of the DDS system, engineers should consider implementing the design using separate devices for the numericallycontrolled oscillator, the digital to analog converter, and the low pass filter. This approach allows for signal observation at many points in the system, yet is compact enough to be practical as an end-solution. Alternatively, the discrete implementation can serve as a prototyping vehicle for a single-chip mixed signal ASIC. The author developed a version of the design using a Harris HI5721 evaluation board for the DAC. The NCO at the heart of the DDS design, and a random generator to test signal modulation, was implemented into about 65% of a QuickLogic field programmable gate array (FPGA). This FPGA, a QL16x24B 4000-gate device, was chosen for its high performance, ease-of-use, and powerful development tools. The NCO design included the following: Developed in Verilog with the 8 bit CLA adder schematic captured and netlisted to Verilog 32 bit frequency word input 32 phase accumulator pipelined over 8 bits 8 bit phase modulation word input 8 bit sine ROM look-up table The design was described mostly in Verilog, with an 8 bit carry look ahead adder modified from QuickLogic s macro library netlisted to Verilog. The whole design cycle was less than four days (two days to describe the design and a day and a half to prototype the hardware). Everything worked perfectly the first time, with the design running at an impressive 45MHz as predicted by the software simulation tools. Plots used in the article to illustrate DDS performance parameters were provided from the test configuration

9 Figure 6 below shows the external IO interface to the NCO design. The function of each signal is described in the following table. Figure 6: The External IO Interface Appendix: External Interface Signals and Design Module FREQWORD[31:0] PHASEWORD[7:0] FWWRN PWWRN SYSCLK PNCLK RESETN NCO QuickLogic QL16x24B FPGA 32 DACOUT[7:0] DACCLK SIN COS MSIN MCOS IDATA QDATA Signal Function Table FREQWORD[31:0] PHASEWORD[7:0] FWWRN This input is the frequency control word to the NCO. This word controls the phase accumulator rate, and thus, the output frequency of the DACOUT sinusoidal wave form. The output carrier frequency is calculated by the following : Fout = FREQWORD[31:0] * (SYSCLK/ 2 32 ) Hz This input is the phase modulation control word to the NCO. This word controls the phase offset following the phase accumulator. This phase offset is used to phase modulate the output carrier. The phase offset is calculated by the following : Pout = PHASEWORD[7:0] * (2π/2 8 ) radians This input is the low asserted frequency word write strobe. This strobe input registers the FREQWORD input on the rising edge. This strobe can be asynchronous to the SYSCLK Application Notes

10 PWWRN SYSCLK PNCLK RESETN DACOUT[7:0] DACCLK SIN COS MSIN MCOS IDATA QDATA This input is the low asserted phase word write strobe. This strobe input registers the PHASEWORD input on the rising edge. This strobe can be asynchronous to the SYSCLK. This is the reference system clock input to the NCO. This clock is the sampling clock of the output carrier. This input is the pseudo-noise generator clock input. This clock sets the data rate of the I and Q data outputs. This input is a low asserted global reset. When asserted, the internal phase and frequency word registers are cleared stopping the output carrier at 0 radians. This output is the sinusoidal DAC amplitude word. This word is valid on the rising edge of the DACCLK. The sinusoidal wave form output is represented by the following : f(t) = sin(2πfout(t) + Pout) This output is the DAC clock strobe. This clock is the SYSCLK feed back to an output pin compensating for the latency of the NCO IO pins. The DACOUT amplitude words will be valid on the rising edge of the DACCLK. This output is a single bit digital sine wave output. This sine wave output comes from the MSB of the phase accumulator. The output frequency of this pin is controlled by the frequency word input. This output is a single bit digital cosine wave output. This cosine wave output comes form the MSB and next most significant bit of the phase accumulator. The output frequency of this pin is controlled by the frequency word input. This output is a single bit digital sine wave output. This sine wave output comes from the MSB of the phase modulator. The output frequency of this pin is controlled by the frequency word input and phase offset by the phase word input. This sine wave output is the same as the SIN output with a phase offset of plus 2π/2 8 * PHASEWORD. This output is a single bit digital cosine wave output. This cosine wave output comes form the MSB and next most significant bit of the phase modulator. The output frequency of this pin is controlled by the frequency word input and the phase offset by the phase word input. This cosine wave output is the same as the COS output with a phase offset of plus 2π/2 8 * PHASEWORD. This output is a pseudo noise random pattern. This output is not a functional part of the NCO design but used to demonstrate phase modulation using the phase port. This output is a pseudo noise random pattern. This output is not a functional part of the NCO design but used to demonstrate phase modulation using the phase port

11 Top Level (dds.v) The top level of the NCO design instantiates the functional blocks of the NCO design and the PN generator block. PN Generator (pngen.v) This module is not part of the NCO design but is used to produce a sample random data pattern to modulate the carrier output. This module uses the PNCLK input to clock two Gold code 5 bit PN generators. The outputs of the PN generators are IDATA and QDATA outputs. The lower level block of this NCO design consist of a synchronous frequency word input register, a synchronous phase word input register, a 32 bit pipe lined phase accumulator, an 8 bit phase adder, and a sin lockup table. A detailed description of each of the NCO blocks and the PN generator are provided in the following sections. Load Frequency Word (loadfw.v) The load frequency word block is a synchronizing loading circuit. The FREQWORD[31:0] input drives a the data input to the 32 bit fwreg register that is sampled on the rising edge of the FWWRN write strobe. The FWWRN strobe also drives the data input to a metastable flip flop fwwrnm that is used in conjunction with a synchronous register fwwrns to produce a FWWRN rising edge strobe. This rising edge strobe loadp1 is then piped for an additional 3 clock cycles producing the load strobes loadp2, loadp3, and loadp4. The load strobes are used to signal when to update the synchronous pipe line 8 bit registers pipefw1, pipefw2, pipefw3, and pipefw4 to the sampled frequency word content. The pipe line registers are concatenated to produce the 32 bit synchronous frequency word output SYNCFREQ[31:0] that is staggered to compensate for the 32 bit pipe lined phase adder. Phase Word Accumulator (phasea.v) The phase accumulator block is a 32 bit accumulator that is pipe lined in 8 bit sections. This module instanciates a schematic captured carry lock ahead CLA adder that has a carry in and carry out port. The synchronous frequency word, staggered to match the pipe lined accumulator, is loaded into the B input of the CLA adders. The sum output of the CLA adders are registered in the pipe registered with the output tied back to the A input of the CLA adders. The carry output of the CLA adders is registered in the pipec registers with the output tied to the next most significant CLA adder carry input. The most significant sum output register pipe4 is assigned to the PHASE output port giving a phase value quantized to 8 bits. A digital sine and cosine value is also calculated from the pipe4 register and brought out of the chip as SIN and COS Description of Design Blocks 8 Application Notes

12 Load Phase Word (loadpw.v) The load phase word block is a synchronizing loading circuit. The PHASEWORD[7:0] input drives the data input to the 32 bit pwreg register that is sampled on the rising edge of the PWWRN write strobe. The PWWRN strobe also drives the data input to a metastable flip flop pwwrnm that is used in conjunction with a synchronous register pwwrns to produce a FWWRN rising edge strobe. This rising edge strobe load is used to signal when to update the synchronous phase word register phswd. The phswd register is assigned to the synchronous phase word output SYNCPHSWD[7:0]. Phase Modulator (phasemod.v) The phase modulator block is used to phase offset the phase accumulator 8 bit quantized output with the synchronous phase word from the load phase word block. This module instantiates a CLA adder with the A input tied to the synchronous phase output and the B input tied to the phase accumulator output. The sum output of the adder is registered in the mphsreg register and assigned to the MODPHASE output port. A modulated version of the sine and cosine values are calculated and brought out of the chip as MSIN and MCOS. Sine Lockup (sinlup.v) This module takes the modulated phase value form the phase modulator block and translated the quantized 8 bit value into a sine wave form amplitude value quantized to 8 bits. The translation from phase to amplitude is performed by a sine ROM table that in instantiated in this module. The ROM table is reduced to a ¼ of the symmetrical sine wave form and the MSB of the sine wave form is equivalent to the modulated phase input. This module performs the calculations to reconstruct a complete period of the sine wave form from the ¼ representation of the ROM table and the MSB of the modulated phase input. To better understand the processing of this module, consider the following. The modulated phase value is a 0 to 2π value quantized to 8 bits 2π/2 8. The quantized value for π/2, π, 3π/2, and 2π are 0x3F, 0x7F, 0xBF, and 0xFF. The amplitude values for 0 to π/2 is stored in the ROM table. The amplitude values for π/2 to π are the ROM table output in the reverse order. The amplitude values for π to 3π/2 are the same output as the amplitude value from 0 to π/2 with the output from the ROM table inverted. Finally the amplitude value for 3π/2 to 2π are the same as for π to 3π/2 with the ROM table accessed in reverse

13 This module manages the address values to the ROM table and the amplitude outputs to form the complete period of the sine wave form. The first process of generating the sine wave function is the addressing of the ROM table such that phase angles p/2 to p and 3p/2 to 2p are addressed in the reverse order. Reverse addressing is accomplished by simply inverting the ROM table address input vector. The phase modulated address input is inverted when the MODPHASE[6] is one and is then registered in the phaseadd register. The phase address is used to address the ROM sine table with the output registered in the qwavesin_ff register. To construct the negative amplitude values of the sine wave form, the MSB of the modulate phase word input is registered twice in modphase_msb1_ff and modphase_msb2_ff, compensating for the two cycle latency of the phaseadd and qwavesin_ff registers. The delayed MSB bit is used to invert the ROM table output when one. The altered ROM table output and the invert of the delayed modulated phase word MSB are finally registered in by the dac_ff register and then assigned to the DACOUT output port. Sine ROM Table (romtab.v) This module is the sine wave form ROM table. This table converts the phase word input to a sine amplitude output. To conserve area, only ¼ of the symmetrical sine wave form is stored in the ROM. The sine values stored in this table are the 0 to π/2 unsigned values quantized to 8 bits. Thus, the ROM table requires a 6 bit phase address input and outputs a 7 bit amplitude output. The sinlup module processes the phase and amplitude values to produce a complete sine period. Dan Morelli has over 9 years of design and management experience. His areas of expertise include spread spectrum communications (involving GPS, TDRSS, and ), PC chip set and system architecture, cell library development (for ECL devices) and ASIC development. He has been published and has multiple patents awarded and pending. Dan currently works for Accelent Systems Inc., an electronic design consulting company, where he is a founder and the VP of Engineering. Designer Profile Application Notes

14 8-156 QAN19