UNIVERSITY OF NAIROBI

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1 UNIVERSITY OF NAIROBI COMPUTER-BASED FUNCTION GENERATOR PROJECT INDEX: PRJ80 BY MUTUKU KELVIN KAVITA F17/28384/2009 SUPERVISOR: DR MWEMA EXAMINER: PROF. ELIJAH MWANGI PROJECT REPORT SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENT FOR THE AWARD OF THE DEGREE OF BACHELOR OF SCIENCE IN ELECTRICAL AND ELECTRONIC ENGINEERING OF THE UNIVERSITY OF NAIROBI DATE OF SUBMISSION: 28th APRIL 2014 DEPARTMENT OF ELECTRICAL AND INFORMATION ENGINEERING I

2 DECLARATION OF ORIGINALITY NAME OF STUDENT: MUTUKU KELVIN KAVITA REGISTRATION NUMBER: F17/28384/2009 COLLEGE: Architecture and Engineering FACULTY/SCHOOL/INSTITUTE: Engineering DEPARTMENT: Electrical and Information Engineering COURSE NAME: Bachelor of Science in Electrical & Electronic Engineering TITLE OF WORK:COMPUTER-BASED FUNCTION GENERATOR 1) I understand what plagiarism is and I am aware of the university policy in this regard. 2) I declare that this final year project report is my original work and has not been submitted elsewhere for examination, award of a degree or publication. Where other peoples work, or my own work has been used, this has properly been acknowledged and referenced in accordance with the University of Nairobi s requirements. 3) I have not sought or used the services of any professional agencies to produce this work. 4) I have not allowed, and shall not allow anyone to copy my work with the intention of passing it off as his/her own work. 5) I understand that any false claim in respect to this work shall result in disciplinary action, in accordance with University anti-plagiarism policy Signature: II

3 Date:. III

4 DEDICATION I dedicate this work to my beloved parents and brother IV

5 ACKNOWLEDGEMENTS I would like to acknowledge the help and support of my parents and my brother. I would also like to acknowledge my friend Anne Wacera for her help. Finally I would like to acknowledge my supervisor Dr. Mwema for the guidance he has shown me during the period of carrying out the project. V

6 ABSTRACT This project aims to generate the various waveforms commonly used in a laboratory.in this project a computer will be used to synthesize the waveforms. It will make use of software to synthesize the waveforms digitally and a USB to parallel converter to transmit the digital version of the waveform to a digital to analog converter where it will be converted to produce an analog waveform. A buffer will be used to display the analog signal on an oscilloscope. The project will succeed in synthesizing these waveforms using software. It will succeed in creating an analog waveform using the computer s sound card but will fail to create an analog signal using the USB to parallel converter due to failure in the USB to parallel converter. VI

7 Table of Contents DECLARATION OF ORIGINALITY... ii DEDICATION..iv ACKNOWLEDGEMENTS... v ABSTRACT..vi LIST OF FIGURES..ix Chapter One: INTRODUCTION Problem Statement Objectives Justification Scope...2 Chapter Two: LITERATURE REVIEW... 3 METHODS OF DISCRETE - TIME WAVEFORM GENERATION Direct Calculation Approach Lookup Table Approach Recurrence Relations DIRECT DIGITAL SYNTHESIS Phase Accumulator Phase to Amplitude Converter Digital-to-Analog Converter Frequency Tuning Equation Spectral Purity Considerations Spurious Free Dynamic Range DDFS with Phase Truncation and Spurious Performance... 8 VII

8 Chapter Three: DESIGN 3.1 Design of the Direct Digital Synthesis computer program Design of the digital to analog converter Design of the computer interface Chapter Four: RESULTS Simulation Results...16 Practical Results...18 Chapter Five: CONCLUSION AND RECOMMENDATIONS Conclusion Recommendations for Further Work APPENDIX A Derivation of the frequency tuning equation APPENDIX B Calculations for the design of the digital to analog converter APPENDIX C : MATLAB code for generating a sine wave APPENDIX D : MATLAB code for generating a square waveform APPENDIX E : MATLAB code for generating a saw-tooth waveform APPENDIX F MATLAB program used for DDS using the sound card APPENDIX G MATLAB program used for simulation..35 VIII

9 LIST OF FIGURES Figure 2. 1 The blocks that constitute a Direct Digital Synthesizer... 5 Chapter 3 Figure 3. 1 Algorithm for the DDS Figure 3. 2 Digital to analog converter Figure 3. 3 The 74HC374 buffer Figure 3. 4 The complete circuit diagram Chapter 4 Figure 4. 1 Simulated sine wave Figure 4. 2 Simulated cosine wave Figure 4. 3 Simulated saw-tooth wave Figure 4. 4 Buffer circuit Figure 4. 5 Practical result from the sound card Figure 4. 6 Practical result from the sound card IX

10 Chapter One: INTRODUCTION 1.1Problem Statement A function generator is a device, which generates various types of waveforms like the sine wave, the triangular wave, the square wave, the saw-tooth wave, the staircase wave, the cosine wave, the ramp wave etc. Normally analog circuitry is employed for the generation and conditioning of waveforms. However the circuitry is usually complex, expensive and at times bulky. In this project a PC is used to emulate a function generator, through the use of software and hardware. A major advantage of a computer based function generator is that its output frequency, phase and amplitude can be precisely and rapidly manipulated under digital processor control. It has the advantage of fine frequency and phase resolution and the ability to rapidly "hop" between frequencies. In place of complex hardware, software is used. The digital circuits used to implement the function generator do not suffer the effects of thermal drift, aging and component variations associated with their analog counterparts. Another important advantage is that the use of software enables us to generate any type of waveform whose mathematical formula is known. This is not possible in the case of a normal function generator. Hence the output waveform of any signal whose trigonometric or algebraic formula can be obtained using a PC based function generator. 1.2 Objectives The objectives of this project are: 1. To understand digital waveform generation and design a waveform synthesizer in software. 2. To design low cost hardware which will convert the synthesized digital waveforms to analog waveforms and to condition the analog waveforms. 1.3 Justification A function generator finds many applications in the laboratory. These include use in modulation, in clock generation, in telecommunications and in many more applications. There is therefore a need for a low cost, large bandwidth, versatile and simple function generator in the laboratory setting. 1

11 1.4 Scope This project covers the analysis and design of a function generator based on a computer. The various methods of digital waveform generation are studied. Direct Digital Synthesis is used to generate these waveforms. MATLAB simulation software will be used to perform the Direct Digital Synthesis and PROTEUS software will be used for circuit design of the digital to analog converter. 1.5 Organization of the report In Chapter two the theory behind digital waveform generation will be covered. The various methods of discrete waveform generation will be studied and in particular the use of Direct Digital Synthesis will be studied in detail. Chapter three will deal with the design of the function generator. It will cover the synthesis of the waveforms in software and the conversion of these synthesized waveforms into analog waveforms. It will deal with the circuit design of all the hardware required. Chapter four covers the results from the simulation of Direct Digital Synthesis in MATLAB and the analysis of practical results from the designed function generator. 2

12 Chapter Two: LITERATURE REVIEW METHODS OF DISCRETE - TIME WAVEFORM GENERATION The synthesis of a digital waveform involves sampling an analog waveform at discrete sample points to create a sequence of sample points. Fourier s theorem states that periodic signals may be composed from a summation of sinusoids, of varying amplitude, phase and frequency. Thus, in this paper the generation of a sine waveform will be given priority since all other waveforms can be derived from it. The paper will focus on the methods used to generate the samples that constitute a sampled sine wave. There are three main methods of digital waveform generation [1] [2]: 1. Direct Calculation Approach 2. Lookup Table Approach 3. Recurrence Relations Direct Calculation Approach This method requires that the waveform to be generated must be representable as a trigonometric function. [1] The computer creates sample points at which it evaluates the amplitude or value of the function. Thus the computer creates a sequence of discrete sample points which are then passed through a digital to analog converter to recreate the function. This method has the disadvantage that it can be very slow if a lot of computations have to be done. That is, if the sampling period is small compared to the period of the function, then the computer has to perform so many computations that it may fail to keep up with the period of the waveform. This means the computer would have a problem generating low frequency waveforms Lookup Table Approach This method works because the waveform is periodic, with only a finite number of samples for each period of the waveform. If the waveform were not periodic, this approach would not be feasible. In this method the computer pre-computes the values corresponding to a sampled waveform and stores them in a table in memory. An index is then created to step through the table. The index sends the value in the current location to a digital to analog converter. When the pointer reaches the end of the table, it is reset to the start of the table again. To generate a 3

13 particular frequency the computer then goes through these values at a constant rate. To generate a high frequency waveform the computer steps through these values a number of samples a time and a smaller number of samples at a time for a low frequency signal. Amplitude scaling can be effected by a multiplying each sample as it is retrieved from the table with a scalar. Phase changes are effected by adding a few samples at the start of the lookup table. With a lookup table, the resolution or granularity of samples (and phase changes) is governed by the number of samples stored in the table. This design is useful in applications such as signal generation for communications systems. An extension of this concept, called direct digital synthesis (DDS), is often used in communication systems. The approach used in DDS extends the method described, but rather than having a single step increment for each sample, a phase register adds a fixed offset to the table address according to the desired frequency so as to step through the table at the required rate (and thus generate the desired frequency). An address accumulator has more bits than is required for the LUT index, and only the higher - order bits of this accumulator are used to address the LUT. This enables finer control over the step size, and hence frequency generated Recurrence Relations This approach makes use of the properties of trigonometric functions to predict the value of a sampled waveform at a particular instant based on its value at the present instant. It pre-stores values just like the look up table approach only that it does not store an entire period. The values at the other instants are then computed using recurrence relations. These computations involve multiplication and addition with no time consuming trigonometric calculations in the main sample generating loop. The computations are thus very fast and do not slow down the computer. 2.2 DIRECT DIGITAL SYNTHESIS Direct Digital Synthesis (DDS) is a way of generating an analog signal (usually a sine wave) by producing a time varying digital signal then performing digital to analog conversion. A DDS system can achieve fast frequency switching in small frequency steps, over a wide band. In addition, it provides linear phase and frequency shifting with good spectral purity. A DDS System is used especially for a precise, high frequency and a phase tunable output. A major advantage of a direct digital synthesizer (DDS) is that its output frequency, phase and amplitude can be precisely and rapidly manipulated under digital processor control [2] Other attributes include the ability to tune with extremely fine frequency and phase resolution, and to rapidly "hop" between frequencies. 4

14 Direct Digital Synthesis is a technique which uses mixed digital-data and analog signal processing blocks as a means to generate signal waveforms that are repetitive in nature. The digital portion of the DDS system is called the numerically controlled oscillator while the analog part consists of a digital to analog converter. The digital synthesis approach employs a stable source frequency as a reference clock to define times at which digital sinusoidal sample values are produced. These samples are converted from digital to analog format to produce analog frequency signals. A DDS System typically consists of a phase accumulator (PA) and a sine lookup table (LUT). The input to the phase accumulator is a frequency control word, which determines the periodicity of the phase accumulator. The phase accumulator is updated to the frequency control word or tuning word, at each clock, the output of the PA is fed to the lookup table. The output of the lookup table is then converted to an analog signal using a digital to analog converter. To generate a fixed frequency sine wave, a constant value, the phase increment that is determined by the frequency control word, is added to the phase accumulator with each clock cycle. If the phase increment is large, the phase accumulator will step quickly through the look-up table and thus generate a high frequency wave. If the phase increment is small, the phase accumulator will take many more steps, accordingly generating a slower waveform. The frequency generated depends on three variables; the reference clock frequency (fclk), length of the n bit accumulator and the binary number in the phase register (frequency control word). The frequency control word is the input to the phase accumulator. Phase Accumulator P Frequency register Phase register Phase to Amplitude converter DAC Filter Out fout Fclk FIGURE 2. 1 THE BLOCKS THAT CONSTITUTE A DIRECT DIGITAL SYNTHESIZER 5

15 Figure 2.1 shows the functional blocks that make up the Direct Digital Synthesizer. These blocks are discussed below. [2] Phase Accumulator A sine wave is generally expressed as a(t)=sin(ωt) 2.1 which is non-linear and not easy to generate except through constructing it from pieces. However, the angular frequency is linear because the phase angle rotates through a fixed angle for each unit of time. The values for angular frequency increase linearly from zero to 2π radians for every period. Therefore a set of phase values in one complete period could be used to compute the amplitudes for a periodic waveform. The phase accumulator is an N bit counter that increments its stored number each times it receives a clock pulse. It is composed of a frequency register, an adder and a phase register. The frequency register is N bits long. It holds a single word that is used to determine the output frequency. This word forms the phase step size between reference-clock updates; it effectively sets how many points to skip around the lookup table. The larger the jump size, the faster the phase accumulator overflows and completes the equivalent of a sine wave cycle. The phase register is an N bit register. At each sampling point, the value in the phase register is added to the control word in the frequency register. Thus the output of the phase accumulator is linearly varying. Since the phase accumulator is N bits long, it overflows every time its value exceeds (2 N -1) and its content is reset to zero. Thus the value of its content increases linearly giving a periodic ramp output Phase to Amplitude Converter The phase to amplitude converter converts digital phase input from the accumulator to output amplitude. The accumulator output represents the phase of the wave as well as an address to a word, which is the corresponding amplitude of the phase in the lookup table. It is an M bit register which contains one cycle of the waveform to be generated. It translates truncated phase information, being in digital form, into quantized numerical waveform samples. Each entry is addressed by a specific value of phase and for thus reason it is also called the look up table. The phase accumulator generates equally spaced 6

16 values that are the inputs to the phase to amplitude converter. The look up table thus converts phase information from the phase accumulator to amplitudes. Depending on the size of the frequency control word; some values in the look up table are skipped before it overflows. The rate at which a complete cycle of a waveform is generated determines the frequency of the waveform and thus the rate at which values are skipped sets the frequency. A large look up table decreases the speed of the synthesizer In order to avoid a very large look up table; it is common to use only a fraction of the most significant bits of the phase accumulator information. The truncation results in spurs in the output spectrum of the Direct Digital Synthesizer. The phase to amplitude converter can be implemented either as memory or as Read Only Memory. Phase quantization occurs when the phase information from the accumulator is truncated. The reason behind this quantization is to keep the memory requirements of the phase to waveform converter quite low. Unfortunately, the phase quantization introduces noise on the phase signal. It leads to phase noise and it produces unwanted spurious spectral components in the DDS output signals, often referred to as spurs Digital-to-Analog Converter The phase accumulator computes a phase (angle) address for the look-up table, which outputs the digital value of amplitude corresponding to the sine of that phase angle to the DAC. The DAC, in turn, converts that number to a corresponding value of analog voltage or current. The DAC and rest of the system run at the same reference clock for synchronization. The DAC adds quantization error at the output to the sine wave Frequency Tuning Equation The equation describing the output of a DDS is; fout = p fclk 2 n 2.2 Where pthe frequency control word, fclk is is the sampling frequency and n is the size of the accumulator. The derivation of this equation can be found in Appendix A. The smallest change in frequency, the frequency resolution f is given by the equation 7

17 f = fclk 2n Spectral Purity Considerations The fidelity of a signal formed by recalling samples of a sinusoid from a Look up Table is affected by both the phase and amplitude quantization of the process. The length and width of the look-up table affect the signal's phase angle resolution and the signal's amplitude resolution respectively. These resolution limits are equivalent to time base jitter and to amplitude quantization of the signal and add spectral modulation lines and a white broadband noise floor to the signal's spectrum. In conjunction with the system clock frequency, PA width determines the frequency resolution of the DDS. The PA must have a sufficient width to span the desired frequency resolution. For most practical applications, a large number of bits are allocated to the phase accumulator in order to satisfy the system frequency resolution requirements Spurious Free Dynamic Range In many DDS applications, the spectral purity of the DAC output is of primary concern. Unfortunately, a number of interacting factors complicate the measurement, prediction, and analysis of this performance. Even an ideal N-bit DAC produces harmonics in a DDS system. The amplitude of these harmonics is highly dependent upon the ratio of the output frequency to the clock frequency. The assumption that the quantization noise appears as white noise and is spread uniformly over the Nyquist bandwidth is simply not true in a DDFS system. For instance, if the DAC output frequency is set to an exact sub multiple of the clock frequency, then the quantization noise is concentrated at multiples of the output frequency, i.e., it is highly signal dependent. If the output frequency is slightly offset, however, the quantization noise becomes more random, thereby giving an improvement in the effective signal to noise ratio. To obtain best signal to noise ratio clock and output frequencies must be carefully chosen DDFS with Phase Truncation and Spurious Performance Phase truncation is an important aspect of DDS architectures. Consider a DDS with a 12- bit phase accumulator. To directly convert 32 bits of phase to corresponding amplitude would require two entries in a lookup table. If each entry were to be stored with 8-bit accuracy, then 4 gigabytes of lookup table memory would be required. It would be impractical to implement such a design. The solution is to use a fraction of the most significant bits of the accumulator output to provide phase information. For example, in a 32-bit DDS design, only the upper most 12 bits might be used for phase information. The lower 20 bits would be ignored (truncated) in this case. Considering a simple DDS 8

18 architecture that uses an 8-bit accumulator of which only the upper 5 bits are used for resolving phase. The phase error introduced by truncating the accumulator will result in errors in amplitude during the phase-to-amplitude conversion process inherent in the DDS. These errors are periodic because, regardless of the tuning word chosen, after a sufficient number of revolutions of the phase wheel, the accumulator phase and truncated phase will coincide. Since these amplitude errors are periodic in the time domain, they appear as spurs in the frequency domain and are known as phase truncation spurs. The magnitude and distribution of phase truncation spurs is dependent on three factors [3]: 1. Phase Accumulator size 2. Phase word size, that is the number of bits of phase after truncation 3. Frequency control word Direct Digital Synthesis has the following advantages [4]; 1) The tuning resolution can be made arbitrarily small to satisfy almost any design specification. 2) The phase and the frequency of the waveform can be controlled in one sample period, making phase modulation feasible. 3) The DDS implementation relies upon integer arithmetic, allowing implementation on virtually any microcontroller. 4) The DDS implementation is always stable, even with finite-length control words. There is no need for an automatic gain control. 5) The phase continuity is preserved whenever the frequency is changed (a valuable tool for tunable waveform generators). 6) The DDS digital architecture eliminates the need for the manual system tuning associated with component aging and temperature drift in analog synthesizer solutions DDS suffers the following restrictions [5]; 1) The output frequency must be lessor equal to half the clocking frequency for proper reconstruction 2) The amplitude of the output waveform is fixed creating the need for extra circuitry to vary the amplitude. 3) Since the waveform is created using sampling techniques the user must accept a certain amount of spectral distortion. 9

19 Chapter Three: DESIGN 3.1 Design of the Direct Digital Synthesis computer program The following algorithm was used to write the DDS program in MATLAB start Start index Calculate the frequency control word Add index to frequency control word Yes Is sum >2^N? No Address look up table Send amplitude to parallel port Figure 3. 1 Algorithm for the DDS From the project specifications the bandwidth required was from zero to 1 megahertz. To satisfy Nyquist s criterion, to sample and reconstruct a 1MHz signal then the minimum sampling frequency would have to be at least twice that of the signal being sampled. A sampling frequency of 4MHz was thus chosen. 10

20 For a maximum frequency of 1MHz a 20 bit accumulator was used. Both the frequency register and the phase register were set to be 20 bit. The size of the look up table was chosen to be eight bit since the output of the look up table was going to an eight bit digital to analog converter and to minimize the effects of phase truncation. The programs written in MATLAB are in appendices C to F. Design of the digital to analog converter There were three possible digital to analog converter configurations to choose from: 1) The weighted resistor digital to analog converter. 2) The R-2R ladder network. 3) A flash DAC The R-2R ladder DAC was chosen because of the following reasons: 1) It requires only two different values of resistances 2) It does not require precision resistors 3) It is cheaper to implement The R-2R ladder network would however perform conversion slower than the other two methods. An eight bit R-2R ladder DAC was designed as shown in figure 3.2. Because the resistors in the DAC were expected to operate at a high frequency of 1MHz, they were chosen to be of the metal film type. Carbon and metal wound resistors would be unable to operate at this frequency. The values of resistances used were 20kΩ and 10kΩ with a power rating of a quarter watt. To buffer a 1 MHz waveform, the minimum slew rate summing amplifier was calculated to be12.566v/μs. For this slew rate and a gain bandwidth product of at least 1MHz the LM 318 operational amplifier was chosen since it has a slew rate of 50 V/μs and a gain bandwidth product of 15 MHz. The summing amplifier was designed to operate as a single supply operational amplifier. Calculations relating to the design of the digital to analog converter can be found in Appendix B. The circuit diagram of the digital to analog converter is shown in figure

21 FIGURE 3. 2 DIGITAL TO ANALOG CONVERTER 3.3 Design of the computer interface A high speed interface between the computer and the digital to analog converter was required. The interface was chosen to be an eight bit USB to parallel converter.this is because of its very high data transfer rate. The parallel port can provide a maximum output current of 25mA. To protect the parallel port from damage a buffer was required to isolate it from the digital to analog converter. The buffer used was the 74HCT374 which is an octal D flip flop. Its truth table is shown below 12

22 FIGURE 3. 3 THE 74HC374 BUFFER. INPUTS OUTPUT OE CLK Dn Qn L H H L L L L L X Qo H X X Z Table 3.1 Truth table for the 74HC374 buffer. Where H = High Level (Steady State) L = Low Level (Steady State) X= Don t Care = Transition from Low to High Level Q0= The level of Q before the indicated steady-state input conditions were established Z = High Impedance State The bits on the input pins of the buffer appear on the output pins after each clock pulse. To clock the buffer, pin 14 of the parallel port is used. It is pulsed every time a data transfer between the parallel port and the digital to analog converter occurs. The pin out of the parallel port is shown below 13

23 DB-25 PIN SIGNAL NAME DIRECTION FUNCTION 1 nstrobe Out Asserted by the computer to indicate the presence of valid data on the data lines 2 Data 0 Out Data line 0 3 Data 1 Out Data line 1 4 Data 2 Out Data line 2 5 Data 3 Out Data line 3 6 Data 4 Out Data line 4 7 Data 5 Out Data line 5 8 Data 6 Out Data line 6 9 Data 7 Out Data line 7 10 nack In Negative pulse that indicates the reception of the last character by the printer 11 Busy In Asserted by the printer when it cannot receive data (buffer is full, error) 12 PError In Indicates end of paper 13 Select In Indicates online status of the printer 14 nautofd Out Asserted by the computer to specify automatic insertion by the printer of the LF character after CR 15 nfault In Indicates an error condition of the printer 16 ninit Out Asserted to initialize the printer 17 nselectin Out Asserted to select the printer 18 Ground Ground for nstrobe signal 19 Ground Ground for D0, D1 signals 20 Ground Ground for D2, D3 signals 21 Ground Ground for D4, D5 signals 22 Ground Ground for D6, D7 signals 23 Ground Ground for Busy, nfault signals 24 Ground Ground for nack, PError, Select signals 25 Ground Ground for nautofd, ninit, nselectin Signals Table 3.2 Pin out for the parallel port The circuit complete that was designed and implemented is shown below 14

24 FIGURE 3. 4 THE COMPLETE CIRCUIT DIAGRAM 15

25 Chapter Four: RESULTS Simulation Results The following are results from the simulation of the Direct Digital Synthesizer in MATLAB. As the DAC being implemented was an 8-bit DAC, the look up table was set to be eight bit long. For the purposes of simulation the program was written to generate only five periods of a sine wave. For an output frequency of 20000Hz the following waveforms were generated Figure 4. 1 Simulated sine wave 16

26 FIGURE 4. 2 SIMULATED COSINE WAVE FIGURE 4. 3 SIMULATED SAW-TOOTH WAVE 17

27 Practical Results To determine whether the circuit would work practically, the generated samples were passed through the sound card of the computer. The sound card is a digital to analog converter with a bandwidth of 48000Hz. It can sample its input at a variable sampling frequency from zero to 48000Hz. For the experiment a sampling frequency of Hz was chosen. This in effect set the frequency range of the sound card to 22000Hz.The sound card is very sensitive to loading. A buffer circuit using the LM 334 operational amplifier was thus constructed to isolate sound card from the oscilloscope. A monophonic audio jack was connected to the earphone port of the computer. Its ground was connected to the ground of the buffer circuit. Its other pin was connected to the noninverting terminal of the operational amplifier. The buffer was designed to operate in its non-inverting mode in order to make use of its high input impedance for the isolation of the sound card. The circuit is shown below. FIGURE 4. 4 BUFFER CIRCUIT 18

28 The waveforms displayed on the oscilloscope are shown below FIGURE 4. 5 PRACTICAL RESULT FROM THE SOUND CARD 19

29 FIGURE 4. 6 PRACTICAL RESULT FROM THE SOUND CARD The circuit designed with the USB to parallel converter was not fully implemented due to a faulty USB to parallel port converter. It failed to transmit bits sent to it and as such the interface between the computer and the digital to analog converter failed to operate 20

30 Chapter Five: CONCLUSION AND RECOMMENDATIONS 5.1Conclusion The circuit designed to perform direct digital synthesis failed to operate due to a faulty USB to parallel converter. However results from the sound card showed that the function generator would have otherwise functioned. 5.2Recommendations for Further Work Instead of the USB to parallel converter a microcontroller with full speed USB communication capabilities such as the atmega 16u2 can be used to perform the data transmission. This would eliminate the need for an expensive USB to parallel converter and the buffer. To make the program faster and more efficient, methods such as the cordic algorithm, which uses the quarter wave symmetry of a sine wave could be used as they reduce the size of the look up table. Use could be made of fabricated Direct Digital Synthesis ICs such as the AD9834 to generate high performance sine, square and triangular outputs. This device for example has a 75MHz bandwidth and the capability for phase and frequency modulation. 21

31 REFERENCES [1] Leis John Wiley, Digital Signal Processsing Using MATLAB for Students and Researchers. New Jersey: John Wiley & Sons, Inc, [2] Jouko Vankka, Direct Digital Synthesizers: Theory, Design and Applications. London : Kluwer Academic Publishers, [3] Eva Murphy, "All About Direct Digital Synthesis," Ask The Application Engineer, vol. Volume 38, August [4] Leis J.W,. New Jersey: John Wiley & Sons, Inc., [5] R. Lyons, "Direct Digital Synthesis," IEEE SIGNAL PROCESSING MAGAZINE, vol. DOI , no. MSP.2004, pp , [6] R. Lyons, "Direct Digital Synthesis," IEEE SIGNAL PROCESSING MAGAZINE, vol. DOI , no. MSP.2004, pp , [7] A. Chenakin, Frequency Synthesizers Concept to Product. Norwood: ARTECH HOUSE INC, [8] B.-G. Goldberg, Digital Frequency Synthesis Demystified. New York: LLH Technology Publishing,

32 23

33 APPENDIX A Derivation of the frequency tuning equation Since for a sine wave ω=2 πf (1) The phase increases linearly from 0 to 2π over one complete cycle of the sine wave. Knowing that the phase of a sine wave is linear and that it depends on a reference clock period, with clock frequency (fclk), the phase rotation (ΔP) for that period can be determined by ΔP = ω Δ t ( 2) Where, ΔP = change in phase of the sine wave, ω= angular frequency of wave, Δ t is a small change in time. Solving for ω gives ω = p =2πf (3) t The overflowing accumulator (phase accumulator) clocked with fclk, generates the phase value sequence, t = 1 fclk (4) Where, t is period. Solving for from Equation 3 and substituting the reference clock frequency for the reference period in Equation 4, specifies the frequency of the output signal: fout = p fclk 2π (5) For an n-bit accumulator the output signal will have the frequency specified as fout = p fclk 2 n (6) Where, p (in degrees) is the phase increment word or frequency control word or frequency tuning word and fclk is the clock frequency, n is the length of accumulator. 24

34 This phase value ( p) is generated using the 2 n overflowing property of an n-bit phase accumulator. The rate of the overflow is the output frequency given by fout = p fclk 2 n (7) ΔP, is an integer, therefore the frequency resolution is found by setting P=1 f = fclk 2 (8) 25

35 APPENDIX B Calculations for the design of the digital to analog converter The summing operational amplifier was designed to operate in single supply mode. Since the non-inverting terminal of the operational amplifier was at 2.5 volts with respect to the system ground and the maximum output of the 74HCT374 buffer is 5 volts, the maximum current flowing through the 20 kilo ohm resistors was calculated as follows =125μA I = Vout = This value is much less than the maximum current per pin of 35mA of the 74HCT374. Therefore the power dissipation of the resistors was calculated to be P = I 2 R = = mW The resistors were selected to have a power rating of a quarter watt. The resistors forming the voltage divider were chosen to be 1 mega ohms each. This was so that they would draw very little current from the voltage regulator. They draw a current of; Thus their power dissipation is: 5 I(voltage divider) = = 2.5μA 26

36 P = ( ) = 12 5μW Thus they were also selected to have a power rating of a quarter watt The summing operational amplifier was designed to operate in single supply mode to eliminate the need for either two power supplies or a dual power supply in the laboratory. It was expected to buffer signals with a bandwidth of 1 MHz at unity gain and it must have at least a gain bandwidth product of 2 MHz. Since the output waveform was expected to have a maximum of approximately 2 volts, the slew rate required for the operational amplifier was calculated to as shown below: dy = 2πf cos( 2πft) dx dy dt max = (2π 2 106) 10 6 = V/μs Lm 318 was chosen as the summing amplifier because it has a slew rate of 50 volts per microsecond and a gain bandwidth product of 15 MHz.It has a maximum power dissipation of 500mW. The maximum current it can draw was thus calculated as: I 2 max = P V = 5 = 0.1A The quiescent current of the74hct374 is 150μA and thus the maximum current drawn from the 5 volt voltage regulator is approximately 0.1 A The voltage regulator chosen to power the circuit is the LM7805. It can supply a maximum of 1A of current at 5 volts. Decoupling capacitors with the values 1µF and 100nF were placed between the output of the voltage regulator and ground to remove any ripples in the dc power supply. 27

37 APPENDIX C : MATLAB code for generating a sine wave %DDS Parameters % N- Accumulator Width % P- Phase Width % fclk- Sampling Frequency N=24; P=20; fclk=2e6; %Initialize the parallel port paraport=digitalio('parallel','lpt1'); line1=addline(paraport,0:7,'out'); %Output Parameters % K - Index Width % J - Output Width K=10; J=9; %System Parameters % ftarget - Target Frequency % dphi - Phase Increment ftarget=input('please input your desired frequency:'); dphi=floor((ftarget*2^n)/fclk); %Generate Output Lookup Table lut=sin(2*pi*(0:2^j-1)/2^j); tmax=1/ftarget; % compute values for only one period t=0:1/fclk:tmax; % set the sampling period 28

38 %Perform DDS acc=0; out=zeros(length(t),1); for i=1:length(t) end index=bitshift(acc,-(n-(k-1))); out(i)=lut(index+1); acc=mod(acc+dphi,2^n); %Normalize the amplitude output to between zero and 255 output1=127.5*out+127.5; output=uint8(output1); h=1:numel(output); % Infinite loop to produce the sine wave while(1) for v=output(h) putvalue(paraport,v) end end 29

39 APPENDIX D : MATLAB code for generating a square waveform N=24; P=20; fclk=2e6; %Initialize the parallel port paraport=digitalio('parallel','lpt1'); line1=addline(paraport,0:7,'out'); %Output Parameters % K - Index Width % J - Output Width K=10; J=9; %System Parameters % ftarget - Target Frequency % dphi - Phase Increment ftarget=input('please input your desired frequency:'); dphi=floor((ftarget*2^n)/fclk); %Generate Output Lookup Table lut=square(2*pi*(0:2^j-1)/2^j); tmax=1/ftarget; % compute values for only one period t=0:1/fclk:tmax; % set the sampling period %Perform DDS 30

40 acc=0; out=zeros(length(t),1); for i=1:length(t) end index=bitshift(acc,-(n-(k-1))); out(i)=lut(index+1); acc=mod(acc+dphi,2^n); %Normalize the amplitude output to between zero and 255 output1=127.5*out+127.5; output=uint8(output1); h=1:numel(output); % Infinite loop to produce the sine wave while(1) for v=output(h) putvalue(paraport,v) end end 31

41 APPENDIX E : MATLAB code for generating a saw-tooth waveform %DDS Parameters % N- Accumulator Width % P- Phase Width % fclk- Sampling Frequency N=24; P=20; fclk=2e6; %Initialize the parallel port paraport=digitalio('parallel','lpt1'); line1=addline(paraport,0:7,'out'); %Output Parameters % K - Index Width % J - Output Width K=10; J=9; %System Parameters % ftarget - Target Frequency % dphi - Phase Increment ftarget=input('please input your desired frequency:'); dphi=floor((ftarget*2^n)/fclk); %Generate Output Lookup Table lut=sin(2*pi*(0:2^j-1)/2^j); tmax=1/ftarget; %compute values for only one period t=0:1/fclk:tmax; 32

42 %Perform DDS acc=0; out=zeros(length(t),1); for i=1:length(t) end index=bitshift(acc,-(n-(k-1))); out(i)=lut(index+1); acc=mod(acc+dphi,2^n); %Normalize the amplitude output to between zero and 255 output1=127.5*out+127.5; output=uint8(output1); h=1:numel(output); % Infinite loop to produce the sine wave while(1) for v=output(h) putvalue(paraport,v) end end 33

43 APPENDIX F MATLAB program used for DDS using the sound card %DDS Parameters % N- Accumulator Width % P- Phase Width % fclk- Sampling Frequency N=24; P=20; fclk=2e6; %Output Parameters % K - Index Width % J - Output Width K=10; J=9; %System Parameters % ftarget - Target Frequency % dphi - Phase Increment ftarget=input('please input your desired frequency:'); dphi=floor((ftarget*2^n)/fclk); %Generate Output Lookup Table lut=sin(2*pi*(0:2^j-1)/2^j); tmax=10000/ftarget; % To obtain 10,000 periods %Perform DDS acc=0; out=zeros(length(t),1); for i=1:length(t) index=bitshift(acc,-(n-(k-1))); out(i)=lut(index+1);acc=mod(acc+dphi,2^n); end sound(out,44000) 34

44 APPENDIX G: MATLAB code used for simulation %DDS Parameters % N- Accumulator Width % P- Phase Width % fclk- Sampling Frequency N=24; P=20; fclk=100000; %Output Parameters % K - Index Width % J - Output Width K=10; J=9; %System Parameters % target - Target Frequency % dphi - Phase Increment ftarget=input('please input your desired frequency:'); dphi=floor((ftarget*2^n)/fclk); %Generate Output Lookup Table lut=sin(2*pi*(0:2^j-1)/2^j); tmax=1/ftarget; %Perform DDS acc=0; out=zeros(length(t),1); for i=1:length(t) end index=bitshift(acc,-(n-(k-1))); out(i)=lut(index+1);acc=mod(acc+dphi,2^n); 35