HIGH-PERFORMANCE direct digital frequency synthesizers

Transcription

1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 3, MARCH A 200 MHz Quadrature Digital Synthesizer/Mixer in 0.8 m CMOS Loke Kun Tan and Henry Samueli, Member, IEEE Abstract A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of dbc. The frequency resolution is Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 m triple level metal N-well CMOS chip has a complexity of transistors with a core area of mm 2. Power dissipation is 2 W at 200 MHz and 5 V. I. INTRODUCTION HIGH-PERFORMANCE direct digital frequency synthesizers (DDFS s) play an extremely important role in modern digital communications. They offer many advantages including fast continuous-phase switching response, fine frequency resolution, large bandwidth, and good spectral purity. This method of frequency synthesis also results in very low phase noise that is limited to be less than or equal to that of the reference clock source. The architecture used in this design was originally introduced by Tierney, Rader, and Gold [1]. It utilizes an overflowing -bit accumulator (or phase accumulator) to generate the phase argument of the sine function generator. Each overflow of the phase accumulator represents one period of a sine wave. The input word (Frequency Control Word) to the phase accumulator controls the frequency of the generated sine waveform. The sine function generator is a ROM look-up table which stores the sine samples. Inherent in this method of frequency synthesis is the high-frequency resolution attainable without the need to increase the size of the ROM look-up table. Frequency resolution is doubled by each addition of 1 b to the phase accumulator wordlength. For a given Frequency Control Word ( ), clocking frequency, and phase accumulator word length, the output frequency of Manuscript received July 15, 1994; revised November 6, This work was supported in part by research grants from the University of California MICRO Program, Hewlett Packard, TRW Electronic Systems Group, Hughes Space and Communications Group, and the Advanced Research Projects Agency. L. K. Tan is with Broadcom Corporation, Los Angeles, CA USA. H. Samueli is with the Integrated Circuits and Systems Laboratory, University of California, Los Angeles, CA USA. IEEE Log Number the synthesizer is given by and the minimum frequency resolution is given by In the design presented in this paper, the phase accumulator word length is 32 b and the maximum clocking frequency is 200 MHz. This gives a minimum frequency resolution of Hz. Another advantage inherent in this architecture is fast switching speeds, with the capability to switch between two frequencies in 1 clock cycle. For 200 MHz operation, the switching speed is 5 ns. This design is also based on the architectural optimizations of Nicholas and Samueli [2]. The same ROM look-up table compression techniques and phase accumulator design were used to simultaneously achieve good spectral purity and large bandwidth. In addition to the features inherent in the design in [2], the synthesizer presented in this paper provides quadrature outputs without increasing the size of the ROM look-up table. It also provides phase modulation, and quadrature amplitude modulation with full-complex multiplications for singlesideband frequency translation. Also, for very high throughput applications, 2 or 4 chips can be parallel to double or quadruple the maximum throughput rate to 400 MHz or 800 MHz. II. APPLICATIONS AND DESIGN REQUIREMENTS Applications for DDFS s range from instrumentation and measurement to modern digital communications. Since the area of instrumentation uses DDFS s as reference sources, the spurious performance requirement of the synthesizer is usually significantly higher than applications in other areas. The frequency, phase, and amplitude modulation capabilities together with the ability to operate at double or quadruple the throughput of a single device makes this design very suitable in the instrumentation field where performance is critical. Two example applications of this chip in the area of digital communications are the implementation of tunable quadrature modulators and demodulators. A tunable quadrature amplitude modulation (QAM) modulator, as shown in Fig. 1, uses square-root Nyquist filters for pulse shaping and interpolation filters for removing in-band images and increasing the sampling rate. The shaded region is the QDDFSM chip which mixes the baseband signal up to IF. The dual of this (1) (2) /95$ IEEE

2 194 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 3, MARCH 1995 Fig. 1. Tunable QAM modulator. Fig. 4. Sine/cosine reconstruction logic. Fig. 2. Tunable QAM modulator. Fig. 5. Digital output spectrum. Fig. 3. Alternative QAM receiver architecture. architecture is the tunable QAM demodulator shown in Fig. 2. The QDDFSM chip here mixes the IF signal back to baseband where it is decimated and passed through matching square-root Nyquist receive filters. Another application of this chip is in a fixed IF QAM receiver [9] where it functions as a digital derotator (Fig. 3) to remove any residual frequency or phase errors in the system. In order to satisfy a wide range of applications, it was required that the worst case digital spurious performance of this synthesizer be better than 80 dbc. Based on the results in [10], a phase resolution of 14 b results in a spurious performance due to phase accumulator truncation of 84.3 dbc. The total phase accumulator wordlength was chosen to be 32 b to achieve a frequency resolution of Hz at a clock rate of 200 MHz and the upper 14 b of the phase accumulator are used by the table look-up circuitry. III. CHIP ARCHITECTURE A. ROM Compression This design uses a generalized algorithm for the compression of arbitrary functions into coarse and fine ROM samples [5], [2]. Let be the total number of bits of the phase address, with being the most significant bits, the next most significant bits, and the least significant bits. Then using this algorithm, the coarse ROM would have samples, and the fine ROM would have samples. Trial and error using the techniques described in [5] resulted in a ROM with 4, 4, and 4. The output wordlength of the coarse ROM is 9 b, and that of the fine ROM is 3 b. Thus, 2 12 sine samples are compressed into 2 9 coarse samples and 2 3 fine samples resulting in a compression ratio of Further compression of the ROM look-up table was obtained by not storing the sine samples, but rather by storing the difference between the sine samples and the phase sin. This results in the need for a final sine/cosine reconstruction stage that adds the coarse and fine ROM samples to the phase argument (Fig. 4). An FFT of the compressed ROM contents gives the worst case digital output spectral purity to be 89 dbc (Fig. 5). However, phase accumulator truncation to 14 b is still the dominant source of spurious noise, and thus the overall spectral purity of the synthesizer is 84.3 dbc. B. Quadrature Outputs A typical DDFS architecture takes advantage of the quarterwave symmetry of a sine wave to reduce ROM storage requirements. Thus, only sine samples from 0 to /2 are stored, and the second MSB of the phase accumulator is used to determine the quadrant, thereby synthesizing a sine wave from 0to. The MSB is then used as a sign bit to synthesize the complete sine wave from 0 to 2. In the case of a cosine

3 TAN AND SAMUELI: A QUADRATURE DIGITAL SYNTHESIZER/MIXER 195 Fig. 6. Sine/cosine storage technique. Fig. 7. Chip modulation capabilities. waveform, its zero crossings are advanced by /2 with respect to that of a sine waveform. To produce the sign bit for this case, the MSB is EXOR ed with the second MSB. For a design where quadrature outputs are desired, a brute force method would be to store both sine and cosine samples from 0 to /2. This would double the size of the ROM lookup table. Instead, one could take advantage of eighth wave symmetry of a sine and cosine waveform, since sine samples from 0 to /4 are the same as cosine samples from /4 to /2. Similarly, cosine samples from 0 to /4 are the same as sine samples from /4 to /2. Hence, one need only store sine and cosine samples from 0 to /4. The third MSB from the phase accumulator can be used to select between these samples. In the actual implementation, the third MSB is EXOR ed with the second MSB to produce this signal. This is necessary so that the select signal is phase aligned with the eighth wave symmetry axis plane of the sine and cosine waveform. Hence, the only additional hardware cost to synthesize quadrature outputs is a 2-to-1 MUX. This architecture is illustrated in Fig. 6. C. Modulation Formats The modulation capabilities of this chip include frequency modulation, phase modulation, quadrature amplitude modulation, and single sideband frequency translation. Frequency modulation is performed by directly modulating the Frequency Control Word, thus no additional hardware is needed to implement this feature. Phase modulation is obtained by adding a phase offset to the phase accumulator output before addressing the ROM look-up table. In hardware, this amounts to incorporating an extra addition stage. This chip accepts a 12 b word for phase modulation. Finally, quadrature amplitude modulation and single sideband frequency translation are obtained by adding a complex multiplier block to the sine and cosine outputs of the quadrature DDFS as shown in Fig. 7. The wordlengths for the and rails for amplitude modulation are 12 b each. The complex multiplier block is made up of four real multipliers. D. Utilizing Parallel Chips for High Throughput The use of parallelism to attain high throughput is very common in VLSI design. Such techniques have been utilized in [3] and [4] for DDFS applications. Our chip has been designed with the capability to double or quadruple the single chip maximum frequency of operation by paralleling 2 or 4 Fig. 8. Paralleling chips for high throughput. chips. In the 2 chip case, this can be done by causing each chip to generate every other output sample. Hence, by using a 2-to-1 MUX and alternately selecting the outputs from the 2 chips, one can attain twice the maximum frequency. To generate every other sample of the output, each chip must use 2 times the Frequency Control Word. In addition, a phase offset must be added to one chip so that the outputs are not duplicated. Fig. 8 illustrates this idea for both the 2 chip case and the 4 chip case. In the actual chip, both the multiplication of the Frequency Control Word and the addition of the phase offset are implemented internally. The user merely sets specific control lines to configure the chips for a certain mode of operation. IV. CIRCUIT DESIGN A. Clock Distribution and Register Design One problem that plagues high-speed CMOS designs is clock skew. Standard two-phase clocking schemes would be difficult to design since small amounts of clock skew would directly limit the speed of operation. To achieve the desired 200 MHz throughput, it was necessary to use a true single-phase clocking (TSPC) scheme. The register chosen for this design is a dynamic positive edge-triggered single-phase register [8] which is shown in Fig. 9. Another problem inherent in high-speed CMOS chips is power supply clock switching noise. This problem exists due to the large number of simultaneously switching register elements, fast switching speeds, and power supply wiring inductance. This makes the design of the clock distribution

4 196 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 3, MARCH 1995 Fig. 9. Single-phase positive edge triggered register. network and its associated capacitive loading critical. Hence, it is important that registers that minimally load the clock distribution line be used. The equivalent clock loading of the register in Fig. 9 is one minimum sized inverter. This resulted in the lowest possible loading of the clock distribution lines. To further reduce power/ground switching noise, and to ensure that power supply levels never collapse during clock transitions, on-chip thin-oxide decoupling capacitors were placed directly across the power/ground lines connected to the clock buffer. Although on-chip decoupling capacitors reduce noise generated by on-chip circuitry, they do not reduce noise generated by simultaneously switching off-chip drivers. This is due to the fact that the off-chip ground plane is not common to the on-chip ground plane, but rather they are connected through inductive bonding wires and package pins. To reduce off-chip noise from coupling back to on-chip circuitry, on-chip power supplies were isolated from power supplies for off-chip drivers. This is accomplished by partitioning the chip power supplies into two unconnected ring halves one-half for on-chip circuitry and the other half for off-chip drivers. To reduce the effective inductance of the off-chip drivers, one pair of power/ground pins were used for every 4 output pins. Double bonds were also used for all power/ground supply pins, further reducing effective inductance. Another issue in high-speed designs is data race. To alleviate this problem, one large localized clock buffer was used to drive all the registers on the chip. This reduces clock skew and provides more reliable operation. In addition, exceptional care was taken to ensure that all clocks are distributed opposite to the flow of data, hence eliminating the possibility of data race. One disadvantage of the single-phase register in Fig. 9 is that it requires clock edges with fast rise and fall times. To ensure that the time constant along the clock lines is minimal, all main clock lines were routed using third-level metal. The use of third-level metal also resolved the conflicting need for wide clock lines to reduce electromigration effects since its current carrying capability was greater than secondor first-level metal. Simulations were performed across model, temperature, and power supply variations to ensure that, under all conditions, the time constant on the clock distribution lines would not limit the speed of operation. B. Multiplier Architecture The multipliers are parallel array multipliers that use radix-4 modified Booth encoding [6] and a carrysave partial product reduction scheme. To attain greater than Fig. 10. Fig. 11. Multiplier architecture. Inverting transmission gate full adder. 200 MHz throughput, two pipeline stages were inserted into the multiplier array. An 8 8 multiplier that is representative of this architecture is shown in Fig. 10. The full adder cell used in this multiplier is an inverting transmission gate full adder (Fig. 11). This circuit has the advantage of being fast and compact. It is compact since all 24 transistors can be laid out without any breaks in the diffusion regions. Another important aspect of this adder is that both the sum and carry outputs have partial propagation delays. This is important since the cumulative speed of the partial product reduction array depends equally on both the propagation delay of the sum and carry outputs. SPICE simulations with nominal models, 5 V power supplies, and at 25 C predict the full adder propagation delay to be 1.2 ns. The circuit diagrams of the Booth encoder and Booth selector are shown in Fig. 12. The Booth encoder implements 2 b scanning with 1 overlap bit. It maps these 3 b to a signed-digit set represented by the signals Comp, Comp, Shift, Shift, and Zero. Comp and Comp determine if the partial product should be complemented, Shift and Shift determine if it should be shifted left by 1 b, and Zero determines if it should be nulled. The Booth selector circuit implements a 5-to-1 MUX using only 14 transistors. This circuit has been designed to operate with the Booth encoder by processing data with as much parallelism as possible. SPICE simulations estimate that the propagation delay of the outputs of the Booth encoder are approximately 0.7, 0.8, and 1.0 ns, respectively, for the signals Comp/Comp, Shift/Shift, and

5 TAN AND SAMUELI: A QUADRATURE DIGITAL SYNTHESIZER/MIXER 197 Fig. 14. The 3-to-8 decoder. Fig. 12. Booth encoder and Booth selector. Fig. 15. Domino ROM circuit. Fig. 13. The 8 b conditional sum adder. Zero. The important point here is that these signals complete their transitions in that sequence, hence the Booth selector has been designed to operate on data in that same sequence by placing the Comp/Comp MUX, first, the Shift/Shift MUX second, and the Zero logic last. C. Carry Propagate Adder One of the speed critical paths in this design exists in the phase accumulator. A carry propagate adder with a wordlength of 32 b is necessary to produce the final address for the ROM look-up table. To achieve the 200 MHz throughput, a sophisticated carry propagate adder had to be used. One possible candidate for this design is a pipelined carry ripple adder. Due to the large wordlength needed, this adder would have to be extensively pipelined. This would result in the use of many registers and would impact the loading of the clock distribution network. Instead, a conditional sum adder [7] was chosen. An example 8 b version of such a carry propagate adder is shown in Fig. 13. The 32 b version of this carry propagate adder was simulated in SPICE using nominal models, 5 V power supplies, and at 25 C to have a speed of 3.1 ns. D. ROM Block Design The decoders for the word and bit lines use pseudo-nmos logic. A representative 3-to-8 decoder is shown in Fig. 14. This design has the advantage of being small and fast at the expense of some dc power dissipation. The ROM basic cell uses dynamic Domino logic. Fig. 15 shows a simplified diagram of the ROM cell together with its associated word and bit lines. On the rising edge of CLK, the output of the ROM cell Dout is precharged high. The evaluate phase occurs when CLK goes low hence conditionally discharging Dout. Dout is pulled low during this phase if any of the transistors M1, M2, or M3 exist. The high-to-low transition of this node has to be completed within the remaining half a clock cycle. Due to the large loading along this path, it is with difficulty that this transition meets the specification of 200 MHz operation. This problem was solved by routing the clock input of the output register Outreg through two inverter delays Invclk1 and Invclk2. This essentially delays the clock to the output register, therefore buying more time for this transition to complete. This modification was simulated using SPICE over temperature, power supply, and model variations to ensure that a data race condition does not exist. The price paid for delaying the clock signal to Outreg is that the next pipeline stage would have less than 1 clock period to complete all transitions. The critical path through the entire ROM block has been simulated to be 4 ns inclusive of setup and hold times of pipeline registers using nominal models, 5 V power supplies, and at 25 C. V. FABRICATION AND TEST RESULTS The Quadrature Digital Synthesizer/Mixer chip was fabricated in a 0.8 m triple-level metal N-well CMOS process. The core of the chip contains transistors occupying an area of mm. Power dissipation is 2 W at a clock rate of 200 MHz. The maximum operating frequency of the chip was measured to be 210 MHz.

6 198 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 3, MARCH 1995 Fig. 16. Spectrum of 1.95 MHz sine wave. Fig. 19. Spectrum of 25.0 MHz sine wave. Fig. 17. Spectrum of 12.0 MHz sine wave. Fig. 20. Frequency modulation. Fig. 18. Spectrum of MHz sine wave. All functional vector tests were performed with the Tektronix LV500 ASIC tester. High-speed testing was accomplished by building a breadboard containing two 10 b D/A con- verters. The converter used was the Analog Devices AD9720 which has a maximum operating frequency of 400 MHz. Figs. 16 and 17 show spectrum plots of a 1.95 MHz and a 12MHz output sinewave, respectively. These spectrum plots span a large frequency range to show the spurious and harmonic components resulting from using a 10 b DAC. In Fig. 16, the worst case spurious component is at db, and in Fig. 17 it is at db. Figs. 18 and 19 show spectrum plots of a MHz and a 25 MHz output sinewave, respectively. These plots have very narrow frequency spans and fine resolution bandwidths for viewing spurs near the fundamental. The DDFS produces a 84.3 dbc spectrally pure signal over its entire tuning range, thus the spurious response in the analog outputs is primarily due to the D/A conversion

7 TAN AND SAMUELI: A QUADRATURE DIGITAL SYNTHESIZER/MIXER 199 TABLE I QDDFSM CHIP SPECIFICATIONS Fig. 21. Phase modulation. Fig. 22. Amplitude modulation. process; however, it is quite good considering that only a 10 b D/A converter was used. The reference clock frequency for all four cases is 200 MHz. The modulation capabilities of the QDDFSM chip were also tested. Fig. 20 shows an example of frequency modulation. The modulating signal is displayed above and the modulated signal below it. The modulating signal is a square wave at 323 khz. Fig. 21 illustrates the phase modulation capability of the chip. The modulating signal is a square wave at a frequency of 94 khz, and therefore this is an example of Binary Phase Shift Keying (BPSK). Fig. 22 illustrates the amplitude modulation capability of the chip where the modulating signal is a sine wave at 200 khz. For all three cases, the clock frequency of the chip was 200 MHz. Table I summarizes the performance of the QDDFSM chip. VI. CONCLUSIONS A Quadrature Digital Synthesizer/Mixer chip has been designed that operates at 200 MHz and synthesizes 84.3 dbc spectrally pure sine and cosine digitized waveforms. This chip exhibits large bandwidth (dc to 100 MHz), high spectral purity, fast switching speed, and fine frequency resolution (0.047 Hz). Fig. 23 shows a photomicrograph of this chip. By taking advantage of sine and cosine symmetries, the size of the ROM look-up table is no larger than that of a DDFS which only generates sine outputs. The chip also incorporates modulation

8 200 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 3, MARCH 1995 [5] H. T. Nicholas, III, H. Samueli, and B. Kim, The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects, in Proc. 42nd Annu. Frequency Cont. Symp. USER-ACOM, May 1988, pp [6] A. D. Booth, A signed binary multiplication technique, Quart. J. Mech. Appl. Math., vol. IV, pt. 2, pp , Aug [7] J. Sklansky, Conditional sum additional logic, IRE Trans. Electron. Comput., vol. EC-9, no. 2, pp , June [8] J. Yuan and C. Svensson, High speed CMOS circuit technique, IEEE J. Solid-State Circuits, vol. 24, pp , Feb [9] B. C. Wong and H. Samueli, A 200 MHz all-digital QAM modulator and demodulator in 1.2m CMOS for digital radio applications, IEEE J. Solid-State Circuits, vol. 26, pp , Dec [10] H. T. Nicholas, III, and H. Samueli, An analysis of the output spectrum of direct digital frquency synthesizers in the presence of phaseaccumulator truncation, in Proc. 41st Annu. Frequency Cont. Symp. USERACOM, May 1987, pp Fig. 23. Photomicrograph of QDDFSM. capabilities. The modulation formats include frequency modulation, phase modulation, quadrature amplitude modulation, and single sideband frequency translation. Hence, this chip encompasses and provides many basic features required in digital communication systems. For very high throughput applications, the quadrature DDFS can be paralleled to provide twice or four times the maximum throughput. Hence, 400 MHz or 800 MHz clocking speeds are possible by paralleling two or four chips. ACKNOWLEDGMENT The authors wish to thank F. Lu for the design of the Booth encoder, G. Yee and S. Olafson for work on the ROM, and also S. Liu and E. Roth for assistance in testing the chip. REFERENCES [1] C. Tierney, M. Rader, and B. Gold, A digital frequency synthesizer, IEEE Trans. Audio Electroacoust., vol. AU-19, pp , [2] H. T. Nicholas, III and H. Samueli, A 150 MHz direct digital frequency synthesizer in 1.25-m CMOS with 090 dbc spurious performance, IEEE J. Solid-State Circuits, vol. 26, pp , Dec [3] M. Thompson, Low latency, high-speed numerically controlled oscillator using progression-of-states technique, IEEE J. Solid-State Circuits, vol. 27, pp , Jan [4] R. Hassun and A. W. Kovalick, Waveform synthesis using multiplexed parallel synthesizers, U.S. Patent , June 12, Loke Kun Tan was born in Kuala Lumpur, Malaysia, on April 2, He received the B.S. degree in electrical engineering from the University of Houston, Houston, TX, in 1987, and the M.S degree in electrical engineering from the University of California, Los Angeles, in Since 1993 he has been at Broadcom Corporation where he works in the communications IC design group. He is currently pursuing the Ph.D. degree in electrical engineering at the University of California, Los Angeles. He also serves as a Research and Teaching Associate in the Department of Electrical Engineering. His research interests include digital communications systems design and communications ASIC design. Henry Samueli (S 75 M 79) was born in Buffalo, NY, on September 20, He received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of California, Los Angeles, in 1975, 1976, and 1980, respectively. From 1980 to 1985, he was with TRW, Inc., Redondo Beach, CA, where he was a Section Manager in the Digital Processing Laboratory of the Electronics and Technology Division. His group was involved in the hardware design and development of military satellite and digital radio communication systems. From 1980 to 1985, he was also a part-time Instructor in the Electrical Engineering Department at UCLA. In 1985 he joined UCLA fulltime where he is currently an Associate Professor in the Electrical Engineering Department. His research interests are in the areas of digital signal processing, digital filter design, analysis of finite wordlength effects in DSP systems, highspeed CMOS integrated circuit design, VLSI architectures for realizing DSP algorithms, and applications of VLSI technology to digital communication systems. Dr. Samueli is the recipient of the 1988/1989 TRW Excellence in Teaching Award of the UCLA School of Engineering and Applied Science and the Meritorious Paper Award of the 1991 Government Microcircuit Applications Conference for the paper CMOS integrated circuits for high bit-rate digital modems, adaptive equalizers and frequency synthesizers.