On-Chip Automatic Analog Functional Testing and Measurements
|
|
- Barry Davis
- 5 years ago
- Views:
Transcription
1 On-Chip Automatic Analog Functional Testing and Measurements Chuck Stroud, Foster Dai, and Dayu Yang Electrical & Computer Engineering Auburn University from presentation to Select Universities Technology, Inc. (SUTI) May 26, 2005
2 The testing problem Outline Manufacture & system testing and cost Built-In Self-Test How does it work and how well Digital vs. analog testing Analog functional testing Measurements vs. fault detection BIST-based functional measurements Our approach vs. others Products & applications 5/26/05 Auburn University SUTI Presentation 2
3 The Testing Problem 2000 International Technology Roadmap for Semiconductors (by the Semiconductor Industry Association - SEMATECH) predicted by 2014: Test machines will cost more than $20M each! Many people say we are already there It will cost more to test a transistor than to manufacture it! Many people say we are already there Testing cost > 50% of product cost 5M-100M transistors on a chip 1 faulty transistor faulty chip Built-In Self-Test (BIST) is the most likely solution Analog BIST is needed for mixed-signal systems Fault diagnosis is needed with BIST Methods needed for automatic implementation of BIST 5/26/05 Auburn University SUTI Presentation 3
4 Manufacture Testing Where are the $20M testers? ¾ Wafer testing Ink dot defective chips Typically not done for RF analog devices 9 Too costly in time & equipment Package only good chips Eliminates packaging defective parts 9 Packaging costs can be high ¾ Package testing & handling defects Burn-in testing for infant mortality Packaging ¾ Board testing Assembly 5/26/05 & handling defects Auburn University SUTI Presentation 4
5 System Testing Manufacture system-level test Unit & system testing Defects due to assembly More customized testers specific to system System-level testing in the field Typically done periodically for High reliability systems High availability systems Done nightly for telephone switching systems Special system hardware/software needed Cost is in system design & development effort 5/26/05 Auburn University SUTI Presentation 5
6 The Testing Problem (continued) Automatic Test Equipment (ATE) cost is increasing High-speed testing needs more expensive ATE Chips are operating at higher speeds Longer test sequences for more complex chips Product testing goes on long after design is done Cumulative testing cost must be considered Cost of fault location/identification and repair Factor of 10 increase in cost Generally accepted Sun Microsystems says multiplier is greater than 10 for complex systems Cost per Fault $ $1000 $100 IC Test Board Test System Test Field Test 5/26/05 Auburn University SUTI Presentation 6 $10 $1
7 Digital vs. Analog Testing Digital testing is defect oriented Test development based on fault models that Attempt Attempt to accurately reflect behavior of defects Are Are computationally efficient for fault simulation Analog testing is specification oriented Functional test based on specifications Linearity, frequency response, signal-to to-noise ratio Recent attempts made in defect oriented testing Difficult Difficult to determine if a circuit is faulty or just outside of nominal operation range Chance of throwing away good product Functional testing is needed to compensate for analog circuit operational variation 5/26/05 Auburn University SUTI Presentation 7
8 Other Mixed-Signal BIST LFSR/accumulator (Stroud, 1987) LFSR/SAR (Ohletz( Ohletz,, 1991) Oscillation (Kaminska( Kaminska,, 1996) OPMAX later bought out by Fluence Multi-waveform/accumulator (Stroud, 1996) Histogram (Frisch, 1997) Tektronix Later Later offered by Logic Vision? Multi-waveform/accumulator (Stroud, 2001) FFT (Emmert( Emmert,, 2004) 5/26/05 Auburn University SUTI Presentation 8
9 Digital System Inputs Digital System Outputs BIST for Mixed-Signal Systems Digital circuitry tests analog circuitry Minimize area & performance penalty to analog circuitry Parameterized models (VHDL or Verilog) Automatic synthesis into any mixed-signal system BIST Start BIST Done Pass/Fail Digital Circuitry System Function Mux DAC TPG ORA Test Control System ADC Function Analog Circuitry Analog Circuit Analog Circuit Analog MUX Analog System Outputs Analog System Inputs 5/26/05 Auburn University SUTI Presentation 9
10 BIST for Mixed-Signal Systems Multiple BIST sequences with analog loopbacks Pass/fail results indicate location of faulty analog circuitry Location & number of analog loopback MUXs Determine analog diagnostic resolution & fault coverage Designer can trade-off analog area overhead & performance penalties TPG DAC Analog Cktry ORA ADC Analog Cktry 5/26/05 Auburn University SUTI Presentation 10
11 Application to RF Tranceiver Functionality of various components measured and compensated Reduce power consumption (extend battery life) Improve quality of communications 5/26/05 Auburn University SUTI Presentation 11
12 Important Analog Functional Tests Linearity 3 rd -order intermodulation (IP3) Quality of system Frequency Response Gain Phase Signal-to to-noise Ratio (SNR) Noise Figure S-parameters Input impedance Output impedance 5/26/05 Auburn University SUTI Presentation 12
13 f 1 f 2 Intermodulation f 1 f 2 f 2 - f 1 f 1 +f 2 2f 1 - f 2 2f 2 - f 1 2f 1 2f 2 3f 1 3f freq IM3 Two signals with different frequencies are applied to a nonlinear system Output exhibits components that are not harmonics of input fundamental frequencies 3 rd -order intermodulation (IM3) is critical Very close to fundamental frequencies 5/26/05 Auburn University SUTI Presentation 13 freq
14 Input 2-tone: 2 Mathematical Foundation x(t)=a 1 cos ω 1 t + A 2 cos ω 2 t Output of non-linear device: y(t)=α 0 +α 1 x(t)+α 2 x 2 (t)+α 3 x 3 (t)+ Substituting x(t) ) into y(t): y(t) ) = ½α 2 (A 12 +A 22 ) + [α 1 A 1 +¾α 3 A 1 (A 12 +2A 22 )]cosω 1 t + [α 1 A 2 +¾α 3 A 2 (2A 12 +A 22 )]cosω 2 t + ½α 2 (A 12 cos2ω 1 t+a 22 cos2ω 2 t ) + α 2 A 1 A 2 [cos(ω 1 +ω 2 )t+cos( +cos(ω 1 -ω 2 )t] P + ¼α 3 [A 13 cos3ω 1 t+a 22 cos3ω 2 t] + ¾α 3 {A 12 A 2 [cos(2ω 1 +ω 2 )t+cos(2ω 1 -ω 2 )t] +A 1 A 22 [cos(2ω 2 +ω 1 )t+cos(2ω 2 -ω 1 )t]} 2ω 1 -ω 2 α 1 A ω 1 ω 2 2ω 2 -ω 1 ¾ α 3 A 2 freq 5/26/05 Auburn University SUTI Presentation 14
15 Output Power (OIP3) P 3rd-order Intercept Point (IP3) IP3 is theoretical input power point where 3 rd -order distortion and fundamental output lines intercept P[dB] IIP 3 [dbm]= +P in [dbm] IM3 IP3 P/2 2 20log(¾α 3 A 3 ) 20log(α 1 A) fundamental Input Power (IIP3) Practical measurement with spectrum analyzer 2ω 1 -ω 2 α 1 A ω 1 ω 2 2ω 2 -ω 1 ¾ α 3 A 2 freq 5/26/05 Auburn University SUTI Presentation 15 P
16 Direct Digital Synthesis (DDS) DDS generating deterministic communication carrier/reference signals in discrete time using digital hardware converted into analog signals using a DAC Advantages Capable of generating a variety of waveforms High precision sub Hz Digital circuitry Small Small size fraction of analog synthesizer size Low Low cost Easy Easy implementation 5/26/05 Auburn University SUTI Presentation 16
17 Typical DDS Architecture Frequency Word N F r clk Accum -ulator Digital Circuits W Sine Lookup Table R D-to-A Conv. Low Pass Filter f out clk F r 2 N out = f clk Sine Wave 1/f out 1/f out 1/f out 1/f out 1/f clk 1/f clk 1/f clk 5/26/05 Auburn University SUTI Presentation 17
18 2-Tone Test Pattern Generator Two DDS circuits generate two fundamental tones F r 1 & F r 2 control frequencies tones DDS outputs are superimposed using adder to generate 2-tone 2 waveform for IP3 measurement DAC & LPF convert to actual analog test waveform F r 1 Accum -ulator #1 F r 2 Accum -ulator #2 Sine Lookup Table 1 Sine Lookup Table 2 Σ D-to-A Conv. Low Pass Filter 2-tone Waveform 5/26/05 Auburn University SUTI Presentation 18
19 Actual 2-Tone 2 IP3 Measurement Outputs of DAC and DUT taken with scope from our experimental hardware implementation Typical P measurement requires expensive, external spectrum analyzer For BIST we need an efficient output response analyzer DAC output x(t): DUT output y(t): P 5/26/05 Auburn University SUTI Presentation 19
20 Output Response Analyzer Multiplier/accumulator-based ORA Multiply the output response by a frequency N-bit multiplier, N = number of ADC bits Accumulate the multiplication result N+M-bit accumulator for < 2 M clock cycle samples Average by # of accumulation clock cycles Gives DC value proportional to power of signal at freq Advantages Easy to implement Low area overhead Exact frequency control More efficient than FFT y(t) f x multiplier X Σ accumulator DC 5/26/05 Auburn University SUTI Presentation 20
21 DC 1 Accumulator y(t) ) x f 2 DC 1 ½A 2 2 α 1 Ripple in slope due to low frequency components Longer accumulation reduces effect MATLAB Simulation Results slope = DC slope = DC 1 ½A 22 α 1 5/26/05 Auburn University SUTI Presentation Clock cycles (x50) y(t) f 2 X DC Σ 1 α 1 A P ¾ α 3 A 2 freq f 2 2f 2 -f 1 Actual Hardware Results
22 DC 2 Accumulator y(t) ) x 2f2 2 -f 1 DC 2 3 / 8 A 2 1 A 2 2 α 3 Ripple is bigger for DC 2 MATLAB Simulation Results 20 y(t) Signal is smaller Test controller obtains DC 2 at integral multiple of 2f 2 -f 1 2f 2 -f 1 X DC Σ 2 α 1 A P ¾ α 3 A 2 freq f 2 2f 2 -f 1 Actual Hardware Results slope = DC 2 3 / 8 A 12 A 22 α /26/05 Auburn University SUTI Presentation 22-5 Clock cycles (x50)
23 BIST-based P Measruement DC 1 & DC 2 are proportional to power at f 2 & 2f2 2 -f 1 Only need DC 1 & DC 2 from accumulators to calculate P = 20 log (DC 1 ) 20 log (DC 2 ) MATLAB Simulation Results 60 Actual Hardware Results Clock cycles (x50) 5/26/05 Auburn University SUTI Presentation 23
24 BIST Architecture BIST-based IP3 measurement Reduce circuit by repeating test sequence for DC 2 BIST-based frequency response needs subset f 1 Test Pattern Generator f 2 x(t)=cos( )=cos(f 1 )+cos(f 2 ) Accum Accum LUT1 LUT2 Σ DAC DUT X ADC y(t) Output Response Analyzer Accum DC1 DC2 2f 2 -f 1 Accum LUT3 X Accum DC2 5/26/05 Auburn University SUTI Presentation 24
25 Delta_P(dB) Hardware Results BIST measures P 14 Spectrum analyzer P Clock Cycles (x100) P P distribution for 1000 BIST measurements mean=13.97 db, σ =0.082 Measured Delta_P(dB) 5/26/05 Auburn University SUTI Presentation 25 Percentage(%)
26 Measurements in Noisy Test Set-up db P BIST measurement in noisy test set-up db P measurement in less noisy test set-up /26/05 Auburn University SUTI Presentation 26
27 Frequency (x0.001) Results for 1000 BIST measurements Better accuracy than spectrum analyzer More Measurements Spectrum Analyzer 14.3 db 24.5 db delta P delta P 5/26/05 Auburn University SUTI Presentation 27 Frequency (x0.001) BIST Measurement mean σ σ
28 BIST IP3 Measurement Results Good agreement with actual values for P < 30dB For measured P > 30dB, the actual P is greater 30dB limit due to 8-bit 8 DAC/ADC with 6-bit 6 resolution Good threshold since P < 30dB is of most interest 50 BIST measured delta P actual delta P 5/26/05 Auburn University SUTI Presentation 28
29 Frequency Response Gain and phase as a function of frequency Important analog function measruement Sweep through frequencies adjusting DDS f input Measure gain at output using BIST circuit Phase delay produces incorrect gain measurement results in ORA Gain Phase 5/26/05 Auburn University SUTI Presentation 29
30 Phase Delay ORA Multiplication unity gain sine wave sine X sine cosine wave (270 phase delay) cosine X sine /26/05 Auburn University SUTI Presentation 30
31 Phase Delay ORA Accumulation sine X sine accumulation sine X sine cosine X sine accumulation cosine X sine /26/05 Auburn University SUTI Presentation 31
32 Phase Delay Measruement y(t) x cos f DC 3 ½A 2 α cos φ y(t) x sin f DC 4 ½A 2 α sin φ Hence, we measure phase delay φ = tan -1 (DC 4 /DC 3 ) y(t) cos f y(t) sin f MATLAB simulation results for output φ = 135 X X Σ DC 3 Σ DC 4 5/26/05 Auburn University SUTI Presentation 32
33 BIST-Based Based Measurement Sweep through frequencies Measure phase delay Measure gain with correction for phase delay Gain Gain = DC3/cos φ = DC4/sin φ Subset of BIST circuit for IP3 measurement Gain Can time-share ORA f Test Pattern Generator f f Accum Accum x(t)= )=cos( cos(f) Cos LUT Sin LUT cos(f) sin(f) DAC DUT 5/26/05 Auburn University SUTI Presentation 33 X X ADC y(t) Output Response Analyzer Accum Accum DC3 DC4 DC4
34 Phase Delay Measurement Results Millions DC3 and DC4 measured for φ 79 Accumulator Value DC4 DC Accumulation Cycles Thousands 5/26/05 Auburn University SUTI Presentation 34
35 Phase Measurement P hase D elay degrees actualm easurem ent BIS T m easurem ent -100 Frequency K H z 5/26/05 Auburn University SUTI Presentation 35
36 Gain Measurement A m plitude db BIS T m easurem ent actualm easurem ent Frequency K H z 5/26/05 Auburn University SUTI Presentation 36
37 Experimental Implementation of BIST TPG, ORA, test controller, & PC interface circuits Three 8-bit 8 DDSs, two 17-bit ORAs,, serial interface Implementation in Verilog Synthesized into Xilinx Spartan 2S50 FPGA Amplifier device under test implemented in FPAA 1600 DAC-ADC ADC PCB PC FPAA DUT FPGA TPG/ORA DAC & ADC Total in FPGA Double ORA Single ORA Slices LUTs FFs 5/26/05 Auburn University SUTI Presentation 37
38 Comparison to Other Approaches FFT-based approach report for 2-tone 2 test Basis for IP3 measurement But this approach did not measure IP3 Required largest Xilinx FPGA 5,062 flip-flops flops & 106,553 combinational logic gates Ours fits in smallest Xilinx FPGA with 160 flip-flops flops & 1200 combinational logic gates FFT looks at all frequencies simultaneously Requires sufficient resolution for accurate test and measurements therefore, very large Ours looks at one frequency at a time which can be easily controlled therefore, no resolution issues Other approaches are based off-chip Including this FFT-based approach since it is too big for on-chip implementation 5/26/05 Auburn University SUTI Presentation 38
Outline. Background of Analog Functional Testing. Phase Delay in Multiplier/Accumulator (MAC)-based ORA
Phase Delay Measurement and Calibration in Built-In Analog Functional Testing Jie Qin, Charles Stroud, and Foster Dai Dept. of Electrical & Computer Engineering Auburn University Outline Background of
More informationA Built-In Self-Test Approach for Analog Circuits in Mixed-Signal Systems. Chuck Stroud Dept. of Electrical & Computer Engineering Auburn University
A Built-In Self-Test Approach for Analog Circuits in Mixed-Signal Systems Chuck Stroud Dept. of Electrical & Computer Engineering Auburn University Outline of Presentation Need for Test & Overview of BIST
More informationAutomated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems
Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems George J. Starr, Jie Qin, Bradley F. Dutton, Charles E. Stroud, F. Foster Dai and Victor P. Nelson
More informationEvaluating the Digital Fault Coverage for a Mixed-Signal Built-In Self-Test. Michael Alexander Lusco
Evaluating the Digital Fault Coverage for a Mixed-Signal Built-In Self-Test by Michael Alexander Lusco A thesis submitted to the Graduate Faculty of Auburn University in partial fulfillment of the requirements
More informationHardware/Software Co-Simulation of BPSK Modulator and Demodulator using Xilinx System Generator
www.semargroups.org, www.ijsetr.com ISSN 2319-8885 Vol.02,Issue.10, September-2013, Pages:984-988 Hardware/Software Co-Simulation of BPSK Modulator and Demodulator using Xilinx System Generator MISS ANGEL
More informationf o Fig ECE 6440 Frequency Synthesizers P.E. Allen Frequency Magnitude Spectral impurity Frequency Fig010-03
Lecture 010 Introduction to Synthesizers (5/5/03) Page 010-1 LECTURE 010 INTRODUCTION TO FREQUENCY SYNTHESIZERS (References: [1,5,9,10]) What is a Synthesizer? A frequency synthesizer is the means by which
More informationTest Synthesis for Mixed-Signal SOC Paths Λ
Test Synthesis for Mixed-Signal SOC Paths Λ Sule Ozev, Ismet Bayraktaroglu, and Alex Orailoglu Computer Science and Engineering Department University of California, San Diego La Jolla, CA 993 fsozev, ibayrakt,
More informationTSEK02: Radio Electronics Lecture 8: RX Nonlinearity Issues, Demodulation. Ted Johansson, EKS, ISY
TSEK02: Radio Electronics Lecture 8: RX Nonlinearity Issues, Demodulation Ted Johansson, EKS, ISY RX Nonlinearity Issues: 2.2, 2.4 Demodulation: not in the book 2 RX nonlinearities System Nonlinearity
More informationVLSI Implementation of Digital Down Converter (DDC)
Volume-7, Issue-1, January-February 2017 International Journal of Engineering and Management Research Page Number: 218-222 VLSI Implementation of Digital Down Converter (DDC) Shaik Afrojanasima 1, K Vijaya
More informationEECS 579 Fall What is Testing?
EECS 579 Fall 2001 Recap Text (new): Essentials of Electronic Testing by M. Bushnell & V. Agrawal, Kluwer, Boston, 2000. Class Home Page: http://www.eecs.umich.edu/courses/eecs579 Lecture notes and other
More informationCHAPTER IV DESIGN AND ANALYSIS OF VARIOUS PWM TECHNIQUES FOR BUCK BOOST CONVERTER
59 CHAPTER IV DESIGN AND ANALYSIS OF VARIOUS PWM TECHNIQUES FOR BUCK BOOST CONVERTER 4.1 Conventional Method A buck-boost converter circuit is a combination of the buck converter topology and a boost converter
More informationBPSK_DEMOD. Binary-PSK Demodulator Rev Key Design Features. Block Diagram. Applications. General Description. Generic Parameters
Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core reset 16-bit signed input data samples Automatic carrier acquisition with no complex setup required User specified design
More informationSection 1. Fundamentals of DDS Technology
Section 1. Fundamentals of DDS Technology Overview Direct digital synthesis (DDS) is a technique for using digital data processing blocks as a means to generate a frequency- and phase-tunable output signal
More informationDATA INTEGRATION MULTICARRIER REFLECTOMETRY SENSORS
Report for ECE 4910 Senior Project Design DATA INTEGRATION IN MULTICARRIER REFLECTOMETRY SENSORS Prepared by Afshin Edrissi Date: Apr 7, 2006 1-1 ABSTRACT Afshin Edrissi (Cynthia Furse), Department of
More informationDirect Digital Synthesis Primer
Direct Digital Synthesis Primer Ken Gentile, Systems Engineer ken.gentile@analog.com David Brandon, Applications Engineer David.Brandon@analog.com Ted Harris, Applications Engineer Ted.Harris@analog.com
More informationTSEK02: Radio Electronics Lecture 8: RX Nonlinearity Issues, Demodulation. Ted Johansson, EKS, ISY
TSEK02: Radio Electronics Lecture 8: RX Nonlinearity Issues, Demodulation Ted Johansson, EKS, ISY 2 RX Nonlinearity Issues, Demodulation RX nonlinearities (parts of 2.2) System Nonlinearity Sensitivity
More informationBlock Diagram. i_in. q_in (optional) clk. 0 < seed < use both ports i_in and q_in
Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core -bit signed input samples gain seed 32 dithering use_complex Accepts either complex (I/Q) or real input samples Programmable
More informationApplication Note #5 Direct Digital Synthesis Impact on Function Generator Design
Impact on Function Generator Design Introduction Function generators have been around for a long while. Over time, these instruments have accumulated a long list of features. Starting with just a few knobs
More informationHardware/Software Co-Simulation of BPSK Modulator Using Xilinx System Generator
IOSR Journal of Engineering (IOSRJEN) e-issn: 2250-3021, p-issn: 2278-8719, Volume 2, Issue 10 (October 2012), PP 54-58 Hardware/Software Co-Simulation of BPSK Modulator Using Xilinx System Generator Thotamsetty
More informationSimple Sigma-Delta ADC Reference Design
FPGA-RD-02047 Version 1.5 September 2018 Contents 1. Introduction... 3 1.1. Features... 3 2. Overview... 3 2.1. Block Diagram... 3 3. Parameter Descriptions... 4 4. Signal Descriptions... 4 5. Sigma-Delta
More informationDesign & Implementation of an Adaptive Delta Sigma Modulator
Design & Implementation of an Adaptive Delta Sigma Modulator Shahrukh Athar MS CmpE 7 27-6-8 Project Supervisor: Dr Shahid Masud Presentation Outline Introduction Adaptive Modulator Design Simulation Implementation
More informationRadio Receiver Architectures and Analysis
Radio Receiver Architectures and Analysis Robert Wilson December 6, 01 Abstract This article discusses some common receiver architectures and analyzes some of the impairments that apply to each. 1 Contents
More informationBPSK System on Spartan 3E FPGA
INTERNATIONAL JOURNAL OF INNOVATIVE TECHNOLOGIES, VOL. 02, ISSUE 02, FEB 2014 ISSN 2321 8665 BPSK System on Spartan 3E FPGA MICHAL JON 1 M.S. California university, Email:santhoshini33@gmail.com. ABSTRACT-
More informationThe Fundamentals of Mixed Signal Testing
The Fundamentals of Mixed Signal Testing Course Information The Fundamentals of Mixed Signal Testing course is designed to provide the foundation of knowledge that is required for testing modern mixed
More informationCHAPTER 5 NOVEL CARRIER FUNCTION FOR FUNDAMENTAL FORTIFICATION IN VSI
98 CHAPTER 5 NOVEL CARRIER FUNCTION FOR FUNDAMENTAL FORTIFICATION IN VSI 5.1 INTRODUCTION This chapter deals with the design and development of FPGA based PWM generation with the focus on to improve the
More informationBPSK Modulation and Demodulation Scheme on Spartan-3 FPGA
BPSK Modulation and Demodulation Scheme on Spartan-3 FPGA Mr. Pratik A. Bhore 1, Miss. Mamta Sarde 2 pbhore3@gmail.com1, mmsarde@gmail.com2 Department of Electronics & Communication Engineering Abha Gaikwad-Patil
More informationIssues and Challenges of Analog Circuit Testing in Mixed-Signal SOC
VDEC D2T Symposium Dec. 11 2009 Issues and Challenges of Analog Circuit Testing in Mixed-Signal SOC Haruo Kobayashi Gunma University k_haruo@el.gunma-u.ac.jp 1 Contents 1. Introduction 2. Review of Analog
More informationDigitalFrequencySynthesisusingMultiPhaseNCOforDielectricCharacterizationofMaterialsonXilinxZynqFPGA
Global Journal of Researches in Engineering: F Electrical and Electronics Engineering Volume 14 Issue 7 Version 1.0 Type: Double Blind Peer Reviewed International Research Journal Publisher: Global Journals
More informationIntegrated Circuit Design for High-Speed Frequency Synthesis
Integrated Circuit Design for High-Speed Frequency Synthesis John Rogers Calvin Plett Foster Dai ARTECH H O US E BOSTON LONDON artechhouse.com Preface XI CHAPTER 1 Introduction 1 1.1 Introduction to Frequency
More informationCHAPTER. delta-sigma modulators 1.0
CHAPTER 1 CHAPTER Conventional delta-sigma modulators 1.0 This Chapter presents the traditional first- and second-order DSM. The main sources for non-ideal operation are described together with some commonly
More informationFourier Analysis. Chapter Introduction Distortion Harmonic Distortion
Chapter 5 Fourier Analysis 5.1 Introduction The theory, practice, and application of Fourier analysis are presented in the three major sections of this chapter. The theory includes a discussion of Fourier
More informationFPGA Implementation of Digital Modulation Techniques BPSK and QPSK using HDL Verilog
FPGA Implementation of Digital Techniques BPSK and QPSK using HDL Verilog Neeta Tanawade P. G. Department M.B.E.S. College of Engineering, Ambajogai, India Sagun Sudhansu P. G. Department M.B.E.S. College
More informationMULTIRATE IIR LINEAR DIGITAL FILTER DESIGN FOR POWER SYSTEM SUBSTATION
MULTIRATE IIR LINEAR DIGITAL FILTER DESIGN FOR POWER SYSTEM SUBSTATION Riyaz Khan 1, Mohammed Zakir Hussain 2 1 Department of Electronics and Communication Engineering, AHTCE, Hyderabad (India) 2 Department
More information10 W, GaN Power Amplifier, 2.7 GHz to 3.8 GHz HMC1114
9 13 16 FEATURES High saturated output power (PSAT): 41.5 dbm typical High small signal gain: db typical High power gain for saturated output power:.5 db typical Bandwidth: 2.7 GHz to 3.8 GHz High power
More informationRF, Microwave & Wireless. All rights reserved
RF, Microwave & Wireless All rights reserved 1 Non-Linearity Phenomenon All rights reserved 2 Physical causes of nonlinearity Operation under finite power-supply voltages Essential non-linear characteristics
More informationEECS 427 Lecture 21: Design for Test (DFT) Reminders
EECS 427 Lecture 21: Design for Test (DFT) Readings: Insert H.3, CBF Ch 25 EECS 427 F09 Lecture 21 1 Reminders One more deadline Finish your project by Dec. 14 Schematic, layout, simulations, and final
More informationEECS 452 Midterm Exam Winter 2012
EECS 452 Midterm Exam Winter 2012 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Points Section I /40 Section II
More informationA new method of spur reduction in phase truncation for DDS
A new method of spur reduction in phase truncation for DDS Zhou Jianming a) School of Information Science and Technology, Beijing Institute of Technology, Beijing, 100081, China a) zhoujm@bit.edu.cn Abstract:
More informationSPIRO SOLUTIONS PVT LTD
VLSI S.NO PROJECT CODE TITLE YEAR ANALOG AMS(TANNER EDA) 01 ITVL01 20-Mb/s GFSK Modulator Based on 3.6-GHz Hybrid PLL With 3-b DCO Nonlinearity Calibration and Independent Delay Mismatch Control 02 ITVL02
More informationIntegrated Microsystems Laboratory. Franco Maloberti
University of Pavia Integrated Microsystems Laboratory Power Efficient Data Convertes Franco Maloberti franco.maloberti@unipv.it OUTLINE Introduction Managing the noise power budget Challenges of State-of-the-art
More informationRecent Advances in Analog, Mixed-Signal, and RF Testing
IPSJ Transactions on System LSI Design Methodology Vol. 3 19 46 (Feb. 2010) Invited Paper Recent Advances in Analog, Mixed-Signal, and RF Testing Kwang-Ting (Tim) Cheng 1 and Hsiu-Ming (Sherman) Chang
More informationKeywords: GPS, receiver, GPS receiver, MAX2769, 2769, 1575MHz, Integrated GPS Receiver, Global Positioning System
Maxim > Design Support > Technical Documents > User Guides > APP 3910 Keywords: GPS, receiver, GPS receiver, MAX2769, 2769, 1575MHz, Integrated GPS Receiver, Global Positioning System USER GUIDE 3910 User's
More informationHigh Speed & High Frequency based Digital Up/Down Converter for WCDMA System
High Speed & High Frequency based Digital Up/Down Converter for WCDMA System Arun Raj S.R Department of Electronics & Communication Engineering University B.D.T College of Engineering Davangere-Karnataka,
More informationA Novel Low-Power High-Resolution ROM-less DDFS Architecture
A Novel Low-Power High-Resolution ROM-less DDFS Architecture M. NourEldin M., Ahmed Yahya Abstract- A low-power high-resolution ROM-less Direct Digital frequency synthesizer architecture based on FPGA
More informationLow-Power Pipelined ADC Design for Wireless LANs
Low-Power Pipelined ADC Design for Wireless LANs J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación,
More informationCHAPTER 6 IMPLEMENTATION OF FPGA BASED CASCADED MULTILEVEL INVERTER
8 CHAPTER 6 IMPLEMENTATION OF FPGA BASED CASCADED MULTILEVEL INVERTER 6.1 INTRODUCTION In this part of research, a proto type model of FPGA based nine level cascaded inverter has been fabricated to improve
More informationFUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART I.1
FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART I.1 Many of these slides were provided by Dr. Sebastian Hoyos January 2019 Texas A&M University 1 Spring, 2019 Outline Fundamentals of Analog-to-Digital
More informationThe Application of System Generator in Digital Quadrature Direct Up-Conversion
Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP. 192-19 The Application of System Generator in Digital Quadrature Direct Up-Conversion Zhi Chai 1, Jun Shen
More informationTesting Digital Systems II
Lecture : Introduction Instructor: M. Tahoori Copyright 206, M. Tahoori TDS II: Lecture Today s Lecture Logistics Course Outline Review from TDS I Copyright 206, M. Tahoori TDS II: Lecture 2 Lecture Logistics
More informationFPGA based generalized architecture for Modulation and Demodulation Techniques
FPGA based generalized architecture for Modulation and Demodulation Techniques Swapan K Samaddar #1, Atri Sanyal #2, Somali Sanyal #3 #1Genpact India, Kolkata, West Bengal, India, swapansamaddar@gmail.com
More informationTIMA Lab. Research Reports
ISSN 292-862 TIMA Lab. Research Reports TIMA Laboratory, 46 avenue Félix Viallet, 38 Grenoble France ON-CHIP TESTING OF LINEAR TIME INVARIANT SYSTEMS USING MAXIMUM-LENGTH SEQUENCES Libor Rufer, Emmanuel
More informationDIRECT UP-CONVERSION USING AN FPGA-BASED POLYPHASE MODEM
DIRECT UP-CONVERSION USING AN FPGA-BASED POLYPHASE MODEM Rob Pelt Altera Corporation 101 Innovation Drive San Jose, California, USA 95134 rpelt@altera.com 1. ABSTRACT Performance requirements for broadband
More informationEE-4022 Experiment 3 Frequency Modulation (FM)
EE-4022 MILWAUKEE SCHOOL OF ENGINEERING 2015 Page 3-1 Student Objectives: EE-4022 Experiment 3 Frequency Modulation (FM) In this experiment the student will use laboratory modules including a Voltage-Controlled
More informationIntroduction to Surface Acoustic Wave (SAW) Devices
May 31, 2018 Introduction to Surface Acoustic Wave (SAW) Devices Part 7: Basics of RF Circuits Ken-ya Hashimoto Chiba University k.hashimoto@ieee.org http://www.te.chiba-u.jp/~ken Contents Noise Figure
More informationFPGA IMPLEMENTATION OF POWER EFFICIENT ALL DIGITAL PHASE LOCKED LOOP
INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14) ISSN 0976
More informationImplementation of a BPSK Transceiver for use with KUAR
Implementation of a BPSK Transceiver for use with KUAR Ryan Reed M.S. Candidate Information and Telecommunication Technology Center Electrical Engineering and Computer Science The University of Kansas
More informationHigh Dynamic Range Receiver Parameters
High Dynamic Range Receiver Parameters The concept of a high-dynamic-range receiver implies more than an ability to detect, with low distortion, desired signals differing, in amplitude by as much as 90
More informationB.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics
B.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics Sr. No. Date TITLE To From Marks Sign 1 To verify the application of op-amp as an Inverting Amplifier 2 To
More informationUMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency
UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency Jamie E. Reinhold December 15, 2011 Abstract The design, simulation and layout of a UMAINE ECE Morse code Read Only Memory and transmitter
More informationA high-level VHDL-AMS model design methodology for analog RF LNA and Mixer
A high-level VHDL-AMS model design methodology for analog RF LNA and Mixer Wei Yang, Hal. Carter, Jianping Yan University of Cincinnati Outline Introduction Design Approach Model Validation In The Case
More informationReconfigurable 6 GHz Vector Signal Transceiver with I/Q Interface
SPECIFICATIONS PXIe-5645 Reconfigurable 6 GHz Vector Signal Transceiver with I/Q Interface Contents Definitions...2 Conditions... 3 Frequency...4 Frequency Settling Time... 4 Internal Frequency Reference...
More informationCHAPTER III THE FPGA IMPLEMENTATION OF PULSE WIDTH MODULATION
34 CHAPTER III THE FPGA IMPLEMENTATION OF PULSE WIDTH MODULATION 3.1 Introduction A number of PWM schemes are used to obtain variable voltage and frequency supply. The Pulse width of PWM pulsevaries with
More informationHigh-Frequency Low-Distortion Signal Generation Algorithm with AWG
High-Frequency Low-Distortion Signal Generation Algorithm with AWG Shohei Shibuya, Yutaro Kobayashi Haruo Kobayashi Gunma University 1/31 Research Objective 2/31 Objective Low-distortion sine wave generation
More informationLinearity Enhancement Algorithms for I-Q Signal Generation
B6-1 10:15-10:45 Nov. 6, 2015 (Fri) 1 /55 Invited paper Linearity Enhancement Algorithms for I-Q Signal Generation - DWA and Self-Calibration Techniques - M. Murakami H. Kobayashi S. N. B. Mohyar T. Miki
More informationLaboratory Assignment 5 Amplitude Modulation
Laboratory Assignment 5 Amplitude Modulation PURPOSE In this assignment, you will explore the use of digital computers for the analysis, design, synthesis, and simulation of an amplitude modulation (AM)
More informationMeasuring 3rd order Intercept Point (IP3 / TOI) of an amplifier
Measuring 3rd order Intercept Point (IP3 / TOI) of an amplifier Why measuring IP3 / TOI? IP3 is an important parameter for nonlinear systems like mixers or amplifiers which helps to verify the quality
More informationMODELLING AN EQUATION
MODELLING AN EQUATION PREPARATION...1 an equation to model...1 the ADDER...2 conditions for a null...3 more insight into the null...4 TIMS experiment procedures...5 EXPERIMENT...6 signal-to-noise ratio...11
More informationfor amateur radio applications and beyond...
for amateur radio applications and beyond... Table of contents Numerically Controlled Oscillator (NCO) Basic implementation Optimization for reduced ROM table sizes Achievable performance with FPGA implementations
More informationReceiver Architecture
Receiver Architecture Receiver basics Channel selection why not at RF? BPF first or LNA first? Direct digitization of RF signal Receiver architectures Sub-sampling receiver noise problem Heterodyne receiver
More informationPhase Noise Measurement Techniques Using Delta-Sigma TDC
19 th IEEE IMS3TW, Porto Alegre, Brazil Sept. 17, 2014 Phase Noise Measurement Techniques Using Delta-Sigma TDC Yusuke Osawa Daiki Hirabayashi Naohiro Harigai Haruo Kobayashi Kiichi Niitsu Osamu Kobayashi
More informationELT Receiver Architectures and Signal Processing Fall Mandatory homework exercises
ELT-44006 Receiver Architectures and Signal Processing Fall 2014 1 Mandatory homework exercises - Individual solutions to be returned to Markku Renfors by email or in paper format. - Solutions are expected
More informationSingle Chip FPGA Based Realization of Arbitrary Waveform Generator using Rademacher and Walsh Functions
IEEE ICET 26 2 nd International Conference on Emerging Technologies Peshawar, Pakistan 3-4 November 26 Single Chip FPGA Based Realization of Arbitrary Waveform Generator using Rademacher and Walsh Functions
More informationComputer Architecture Laboratory
304-487 Computer rchitecture Laboratory ssignment #2: Harmonic Frequency ynthesizer and FK Modulator Introduction In this assignment, you are going to implement two designs in VHDL. The first design involves
More informationFPGA Based Mixed-Signal Circuit Novel Testing Techniques
FPGA Based Mixed-Signal Circuit Novel Testing Techniques Sotirios Pouros *, Vassilios Vassios *, Dimitrios Papakostas *, Valentin Hristov ** *1 Alexander Technological & Educational Institute of Thessaloniki,
More informationElectronics A/D and D/A converters
Electronics A/D and D/A converters Prof. Márta Rencz, Gábor Takács, Dr. György Bognár, Dr. Péter G. Szabó BME DED December 1, 2014 1 / 26 Introduction The world is analog, signal processing nowadays is
More informationADI 2006 RF Seminar. Chapter II RF/IF Components and Specifications for Receivers
ADI 2006 RF Seminar Chapter II RF/IF Components and Specifications for Receivers 1 RF/IF Components and Specifications for Receivers Fixed Gain and Variable Gain Amplifiers IQ Demodulators Analog-to-Digital
More informationDriver Amplifier for 7 Tesla MRI Smart Power Amplifier
Driver Amplifier for 7 Tesla MRI Smart Power Amplifier presented by Kevin Kolpatzeck supervised by Prof. Dr.-Ing. Klaus Solbach Institute of Microwave and RF Technology University of Duisburg Essen Contents
More informationComputer Aided Design of Electronics
Computer Aided Design of Electronics [Datorstödd Elektronikkonstruktion] Zebo Peng, Petru Eles, and Nima Aghaee Embedded Systems Laboratory IDA, Linköping University www.ida.liu.se/~tdts01 Electronic Systems
More informationVLSI IMPLEMENTATION OF MODIFIED DISTRIBUTED ARITHMETIC BASED LOW POWER AND HIGH PERFORMANCE DIGITAL FIR FILTER Dr. S.Satheeskumaran 1 K.
VLSI IMPLEMENTATION OF MODIFIED DISTRIBUTED ARITHMETIC BASED LOW POWER AND HIGH PERFORMANCE DIGITAL FIR FILTER Dr. S.Satheeskumaran 1 K. Sasikala 2 1 Professor, Department of Electronics and Communication
More informationHigh Group Hz Hz. 697 Hz A. 770 Hz B. 852 Hz C. 941 Hz * 0 # D. Table 1. DTMF Frequencies
AN-1204 DTMF Tone Generator Dual-tone multi-frequency signaling (DTMF) was first developed by Bell Labs in the 1950 s as a method to support the then revolutionary push button phone. This signaling system
More informationIn the previous chapters, efficient and new methods and. algorithms have been presented in analog fault diagnosis. Also a
118 CHAPTER 6 Mixed Signal Integrated Circuits Testing - A Study 6.0 Introduction In the previous chapters, efficient and new methods and algorithms have been presented in analog fault diagnosis. Also
More informationPE713 FPGA Based System Design
PE713 FPGA Based System Design Why VLSI? Dept. of EEE, Amrita School of Engineering Why ICs? Dept. of EEE, Amrita School of Engineering IC Classification ANALOG (OR LINEAR) ICs produce, amplify, or respond
More informationLow Power Design of Successive Approximation Registers
Low Power Design of Successive Approximation Registers Rabeeh Majidi ECE Department, Worcester Polytechnic Institute, Worcester MA USA rabeehm@ece.wpi.edu Abstract: This paper presents low power design
More informationAudio Visualiser using Field Programmable Gate Array(FPGA)
Audio Visualiser using Field Programmable Gate Array(FPGA) June 21, 2014 Aditya Agarwal Computer Science and Engineering,IIT Kanpur Bhushan Laxman Sahare Department of Electrical Engineering,IIT Kanpur
More informationA Signature Test Framework for Rapid Production Testing of RF Circuits
A Signature Test Framework for Rapid Production Testing of RF Circuits Ram Voorakaranam, Sasikumar Cherubal and Abhijit Chatterjee Ardext Technologies, Atlanta, GA, 30318 Abstract Production test costs
More informationTermination Insensitive Mixers By Howard Hausman President/CEO, MITEQ, Inc. 100 Davids Drive Hauppauge, NY
Termination Insensitive Mixers By Howard Hausman President/CEO, MITEQ, Inc. 100 Davids Drive Hauppauge, NY 11788 hhausman@miteq.com Abstract Microwave mixers are non-linear devices that are used to translate
More informationChannel Characteristics and Impairments
ELEX 3525 : Data Communications 2013 Winter Session Channel Characteristics and Impairments is lecture describes some of the most common channel characteristics and impairments. A er this lecture you should
More informationSynthesized Function Generators DS MHz function and arbitrary waveform generator
Synthesized Function Generators DS345 30 MHz function and arbitrary waveform generator DS345 Function/Arb Generator 1 µhz to 30.2 MHz frequency range 1 µhz frequency resolution Sine, square, ramp, triangle
More informationPre-distortion. General Principles & Implementation in Xilinx FPGAs
Pre-distortion General Principles & Implementation in Xilinx FPGAs Issues in Transmitter Design 3G systems place much greater requirements on linearity and efficiency of RF transmission stage Linearity
More information354 Facta Universitatis ser.: Elec. and Energ. vol. 13, No.3, December 2000 in the audio frequency band. There are many reasons for moving towards a c
FACTA UNIVERSITATIS (NI» S) Series: Electronics and Energetics vol. 13, No. 3, December 2000, 353-364 GENERATING DRIVING SIGNALS FOR THREE PHASES INVERTER BY DIGITAL TIMING FUNCTIONS Miroslav Lazić, Miodrag
More informationHigh Speed Direct Digital Frequency Synthesizer Using a New Phase accumulator
Australian Journal of Basic and Applied Sciences, 5(11): 393-397, 2011 ISSN 1991-8178 High Speed Direct Digital Frequency Synthesizer Using a New Phase accumulator 1 Salah Hasan Ibrahim, 1 Sawal Hamid
More informationADVANCES in VLSI technology result in manufacturing
INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2013, VOL. 59, NO. 1, PP. 99 104 Manuscript received January 8, 2013; revised March, 2013. DOI: 10.2478/eletel-2013-0012 Rapid Prototyping of Third-Order
More informationAnalog and RF circuit techniques in nanometer CMOS
Analog and RF circuit techniques in nanometer CMOS Bram Nauta University of Twente The Netherlands http://icd.ewi.utwente.nl b.nauta@utwente.nl UNIVERSITY OF TWENTE. Outline Introduction Balun-LNA-Mixer
More informationLow-IMD Two-Tone Signal Generation for ADC Testing
18 th International Mixed-Signals, Sensors, and Systems Test Workshop May 15 2012 @ Taipei, Taiwan Low-IMD Two-Tone Signal Generation for ADC Testing K. Kato, F. Abe, K. Wakabayashi, T. Yamada, H. Kobayashi,
More informationVLSI Testing. Yield Analysis & Fault Modeling. Virendra Singh Indian Institute of Science Bangalore
VLSI Testing Yield Analysis & Fault Modeling Virendra Singh Indian Institute of Science Bangalore virendra@computer.org E0 286: Test & Verification of SoC Design Lecture - 2 VLSI Chip Yield A manufacturing
More informationDigital Design Laboratory Lecture 7. A/D and D/A
ECE 280 / CSE 280 Digital Design Laboratory Lecture 7 A/D and D/A Analog/Digital Conversion A/D conversion is the process of sampling a continuous signal Two significant implications 1. The information
More informationUnprecedented wealth of signals for virtually any requirement
Dual-Channel Arbitrary / Function Generator R&S AM300 Unprecedented wealth of signals for virtually any requirement The new Dual-Channel Arbitrary / Function Generator R&S AM300 ideally complements the
More informationCommon RF Test On ATE
Common RF Test On ATE ICTEST8 the 10 th test symposium COE Expert Engineer (ADVANTEST) Kevin.Yan 2017/12/15 All Rights Reserved - ADVANTEST CORPORATION 1 Agenda RF Typical test items Introduction Test
More informationSome Aspects Regarding the Measurement of the Adjacent Channel Interference for Frequency Hopping Radio Systems
Some Aspects Regarding the Measurement of the Adjacent Channel Interference for Frequency Hopping Radio Systems PAUL BECHET, RADU MITRAN, IULIAN BOULEANU, MIRCEA BORA Communications and Information Systems
More informationSignal Integrity Design of TSV-Based 3D IC
Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues
More information