Implementation of a BPSK Transceiver for use with KUAR

Transcription

1 Implementation of a BPSK Transceiver for use with KUAR Ryan Reed M.S. Candidate Information and Telecommunication Technology Center Electrical Engineering and Computer Science The University of Kansas reed@ittc.ku.edu

2 Outline Motivation KUAR Overview Thesis Objectives Proposed Transceiver Design Simulink, Xilinx, Modelsim Results Conclusion Future Work 2

3 Motivation Development of the KUAR Experimental radio Radiates between 5-6 GHz Bank of modulation schemes Media access protocols Adaptation mechanisms Policy development JTRS Test bed [1] 3

4 KUAR Overview Several Components Battery Digital board FPGA, DAC, ADC CPH RF Front End Antennas Ethernet SDRAM 32MB PPC IBM405EP FLASH 32 MB 32 SRAM 4MB 32 Vertix-II Pro XC2VP ADC AD Msps DAC AD Msps To/From RF Board Rx_I Rx_Q Tx_I Tx_Q Digital Board CPH [1] Images of the KUAR 4

5 Thesis Objectives Design and construct 1 Mbaud BPSK Transceiver 5 MHz Carrier, 80 Msps Synchronize the carrier Synchronize the symbol Use minimal resources 5

6 Method of Carrier Synchronization Rice s digital Costas loop [2] 6

7 Method of Symbol Synchronization z +1 + Integrate sign - Decision z -1 Georghiades Early-Late Algorithm [3] 7

8 Proposed Transceiver Addr Ph Direct Digital Synthesizer s 5n π 80 [] n = cos 2 + φ[] n Block diagram of transmitter 8

9 Proposed Transceiver Block diagram of receiver 9

10 Simulink Simulation Proposed Transceiver Design (Simulink) Transmitter Expected outputs Receiver modules Carrier synchronization Symbol synchronization SNR vs. BER 10

11 Simulink Simulation Int_Carrier_Freq Constant 2*pi Gain Product cos cosine 1 cos Clock 1 Bit 1/z Rate Transition pi Gain1 Simulink model of transmitter 11

12 Simulink Simulation Ideal constellation of the transmitter 12

13 Simulink Simulation Ideal waveform of the transmitter 13

14 Simulink Simulation Tx Error Rate Calculation Rx Error Rate Calculation -125 Z Integer Delay Rate Transition Scope5 Samples Sy mbols Correction Scope6 DSP Add Early/Late Bit Recovery Sine Wave2 Abs u Sign Lookup Table round Uniform RandomRounding Number Function Phase sin Transmitter DSP AWGN AWGN Channel Product Product1 num(z) 80 Discrete Filter num(z) 80 Discrete Filter1 In1 Out1 Dump In1 Out1 Dump1 I_Rx Q_Rx cos_adj sin_adj Rotate si n Trigonometric Function1 I_out Q_out Scope1 Loop Filter I_In Ph_adj Q_In Sine Wave3 cos Trigonometric Function Top level of the simulation of the receiver 14

15 Simulink Simulation Correction Pulse Sample Timer Repeating Sequence num(z) 80 Discrete Filter 1 z Unit Delay Early Early Sample Current Current Sample Sign Product u y fcn Embedded MATLAB Function Scope6 1 z Unit Delay1 1 z Unit Delay2 Late Late Sample Sampler Product1 Early-late algorithm simulation 15

16 Simulink Simulation Example of the early-late algorithm synchronizing to a signal 16

17 Simulink Simulation Sign I_Rx Q_Rx cos_adj sin_adj I_out Q_out Rotate sin Loop Filter Trigonometric Function1 Ph_adj I_In Q_In cos Trigonometric Function The loop filter section 17

18 Simulink Simulation Transmitted Estimated Correction The loop filter synchronizing under constant phase error 18

19 Simulink Simulation Transmitted Estimated Correction The loop filter synchronizing under constant frequency error 19

20 Simulink Simulation SNR vs. BER Results Simulated Gevargiz BER SNR (db) Simulation of the proposed receiver compared to Gevargiz s receiver 20

21 Xilinx Implementation System overview Boxcar filter implementation Loop filter implementation Synthesis sizing 21

22 Xilinx Implementation Top level of the Xilinx schematic of the receiver 22

23 Xilinx Implementation x(n) x(79), x(78),,x(1),x(0) x(n) Xilinx schematic of the boxcar filter 23

24 Xilinx Implementation Xilinx schematic of the loop filter 24

25 Xilinx Synthesis Table of resource usage Receiver Transmitter Total Slices 1481/ / /9280 Multipliers 10/88 0/88 10/88 BRAMs 5/88 4/88 9/88 Maximum Freq MHz MHz MHz 25

26 Modelsim Results Transmitter output Loop filter response Early-late gate loop response 26

27 Modelsim Results Output Amplitude Time Output waveform of the transmitter 27

28 Modelsim Results Loop Filter Results Value 400, , , , , , , Time sample Predicted Calculated Output of the loop filter compared to expected results 28

29 Modelsim Results Simulated output of the symbol synchronizer with flat input 29

30 Modelsim Results Simulated output of the symbol synchronizer with increasing input 30

31 Modelsim Results Simulated output of the symbol synchronizer with decreasing input 31

32 Concluding Remarks Communicated 1 Mbaud of information with carrier of 5 MHz Synchronized with the transmitted carrier Synchronized the symbol Minimized resources Provided a tool for researching SDR and communications 32

33 Future Work This was stepping stone M-PSK, SSB-AM Channel sounding, equalization, fading, multipath, pulse shaping Library of modulation schemes 33

34 References [1] G. J. Minden, KU Agile Radio Overview, University of Kansas, Lawrence, Kansas, [2] M. Rice, Introduction to Digital Communication Theory, 2004, e485.fall.04/. (Will be a book soon) [3] C. Georghiades, Synchronization, The Communications Handbook, 2nd ed., Ed. J. Gibson, Boca Raton: CRC Press,

35 Questions?