Towards an IEEE SDR Transceiver

Transcription

1 Towards an IEEE SDR Transceiver Rapid prototyping of an all-digital implementation Josep Sabater ( jsabaterm@el.ub.es) Departament d'electrònica Universitat de Barcelona

2 Index Topics of the presentation 1) Introduction: IEEE SDR. 2) The system: An all-digital transceiver. 2a) The transmitter. 2b) The receiver. 3) Results. 4) Conclusion and future work. 2

3 Introduction Overview of the IEEE standard ( ) Specifies Physical (PHY) and Medium Access Control (MAC) layers for Low-Rate Wireless Personal Area Networks (LR-WPAN). Four PHYs that use three ISM bands: (3) 868/915 MHz and (1) 2.4 GHz. Europe Four over-the-air data rates: 20 Kb/s 40 Kb/s 100 Kb/s 250 Kb/s USA Worldwide ( ) ( ) ( ) ( / / ) Lower power and lower cost than other WPAN (e.g. Bluetooth). (1) Optional PHY 3

4 Introduction Overview of PHY 868 MHz Protection against phase inversion PPDU Differential Encoder Pulse Shaping Chip to Symbol DSSS 20 Kb/s 300 KChip/s Bit To Chip Two 15-chip PN seq. En = Bn xor En - 1 '0' : '1' : MHz BPSK Modulator 600 KHz - 1 symbol (phase) / chip : (0 - π) - Raised cosine (roll-off = 1) PPDU (PHY Protocol Data Unit) Format SFD (0x00) (16710) Frame Length r PHY Payload 4B 1B 7b 1b variable Preamble DSSS: Direct Sequence Spread Spectrum PN: Pseudo Noise BPSK: Binary Phase Shift Keying 4

5 Introduction Cognitive Radio and Software Radio A Cognitive Radio (CR) terminal is: Aware of (sense) its environment. Capable of altering its PHY behaviour to adapt to the environment. DSS + QoS Software Radio (SR) was first coined by Joseph Mitola (1995) to designate a single device: Whose behaviour is determined by software (upgradable). Can operate in different bands. Can use several modulations, coding schemes and bandwidths. reconfigurability + programmability DSS QoS: Dynamic Spectrum Sharing. Quality of Service. 5

6 Introduction Software Radio vs Software Defined Radio The ideal SR architecture has been inspired by Joseph Mitola's view (1995): DSP LNA LNA ADC ADC Rx PA PA DAC DAC Tx SR is a radio that employs wideband ADC / DAC and a processor to service an entire spectrum allocation in a single integrated module. Software Defined Radio (SDR) is a radio where some functions (including PHY) are defined in software. SDR is a compromising and practical version of SR. 6

7 The designed system An overview - An oversampled second order tunable 1-bit Bandpass Delta Sigma Modulator (BPDSM) transmitter with digital RF upconversion. - A subsampling receiver. Normal / Test FPGA 8 bits PA Transmitter 8 bits μp Test Unit 8 bits Receiver 32 MHz CMP <0 Normal / Test LNA PA: Power Amplifier. LNA: Low-Noise Amplifier. CMP: Comparator. 7

8 The designed system The transmitter and receiver submodules Transmitter Data Stream 8 bits Tx In fx s9.6 8 bits Tx PHY Framer IF Upconv. Baseband Modulator fx s18.11 BP-ΔΣ Modulator RF Upconv. Tx Out Data Clk α = MHz Rx 8 bits Out Fc = 4.3 MHz BW = 300 Khz BW = 600 Khz Chip Stream Correlation Sum (0-15) 4 bits DPLL Correlator Deframer Bit Clk Fc = 4.3 MHz BW = 600 Khz Fc = MHz BW = 600 Khz I (fx s32.5) Rx PHY Byte Clk Fc = 0 Hz Baseband Demod. Digital Downconv Q (fx s32.5) Chip Clk Receiver Sin = 4.3 MHz Rx In 32 MHz 8

9 Design methodology Transceiver design flow & test constraints Matlab + Simulink Behavioral Behavioral Model Model It has been tested in a Virtex 5 FPGA using Test submodule. - Xilinx ML501 evaluation board. VHDL files Modelsim Testbenches (VHDL) With an operating freq. of 32 MHz. For rapid validation of the system an RF of 128 MHz is selected. - Virtex 5 Digital Clock Manager (DCM). Recoding '.m' and sim files. HDL HDL Simulation Simulation (VHDL) VHDL files User constraints (UCF) Synth. Mod. Xilinx ISE Synthesize Synthesize + Flip-Flop & time Mod. (VHDL) bit file Xilinx Impact + ML 501 Clk 32 MHz FPGA FPGA 9

10 Results Logic analyzer plots [1/2]: txstream vs rxstream 10

11 Results Logic analyzer plots [2/2]: BPSK wave 11

12 Conclusion and future work An all-digital FPGA implementation of a transceiver inspired on the 868 band of the IEEE standard has been designed and tested. Independent modules for implementation in any FPGA device. Efficient multiplication algorithm is fundamental for a good performance. Delay time: limits max. clock frequency of the whole system. A final RF-Upconversion stage in the range of 868 MHz. K. A Shehata, M A Abdoul-Dahab, S. H. El Ramly and K.A. Hamouda An FPGA based 1-bit all digital transmitter Employing Delta-Sigma modulation with RF output for SDR, Signals, Circuits and Systems, SCS nd International Conference on, pp.1-6, 7-9 Nov Improvement and additional filtering will be needed for higher freqs. A better quality study and measurements (SNR, BER...) 12

13 Questions? Thank you very much for your attention Xilinx ML 501 board + Agilent Logic Analyzer 13

14 Digital to digital modulation 2nd order tunable Band-Pass Delta Sigma Modulator (BPDSM) [1/2] A Delta Sigma Modulator (DSM) is composed of a linear filter, a quantizer and a feedback loop. The quantification error (superimposed noise) can be shaped out from the desired frequency band modifying the transfer function of the filter. H(f) Low-Pass LPDSM (integrator) H(f) Band-Pass BPDSM (resonator) OSR BPDSM = f s/ 2 BW signal OSR = 25 SQNR BPDSM 10 log L OSR L 1 2 Tunable central freq (α) α =

15 Digital to digital modulation 2nd order tunable Band-Pass Delta Sigma Modulator (BPDSM) [2/2] The tunable resonator (2 in the design) is its basic function block. S z TBPDSM z 1 z 2 = 1 2 z 1 z 2 Configurable central frequency according to the α factor applied. As a result of real-time computation an efficient multiplier has been implemented Even comp Odd comp x * y = (xe + xo)(ye + yo) = xe ye+ xeyo + xo ye+ xoyo P = x * y = Pee + Peo + Poe + Poo Two step process: Partial products Final addition 15

16 Sampling + mixing operation Subsampling Bandpass sampling Undersampling It is the act of sampling a signal at a lower rate than Nyquist 2 x fmax fs > 2 x BW It achieves frequency translation via intentional aliasing fcarrier fif ϵ [0, fs/2] BW fif fif 2 fs 3 fs n fs f (Hz) - fcarrier = n fs + fif fcarrier = 864 MHz MHz = MHz (for n = 27 and fs = 32 MHz) 16

17 Digital downconv. + Symbol detection LUT-based mixing + arc tangent LUT CIC: LPF: LUT: Q f0 = 4.3 MHz 7 sin(w0t) -sin(w0t) cos(w0t) -cos(w0t) Cascaded Integrator-Comb Low-Pass Filter Look-Up Table I 3 sin (w0t) / -sin(w0t) (fx s32.5) I Phase Drift Compensator CIC Filter (LPF + Decimation) o 0 arctan 90o PDC symbol CIC Filter Q (LPF + Decimation) (fx s32.5) cos(w0t) / -cos(w0t) Digital Downconv. Baseband Demod. 17

18 IF Upconversion LUT based carrier generation at 4.3 MHz Mixing operation (fixed point arithmetic multiplication) of a 4.3 MHz carrier with the baseband signal. x * y = (xe + xo)(ye + yo) = xe ye+ xeyo + xo ye+ xoyo P = x * y = Pee + Peo + Poe + Poo A.A. Khatibzadeh, K. Raahemifar and M. Ahmadi, "A 1.8 V 1.1 Ghz novel digital multiplier," Electrical and Computer Engineering, Canadian Conference on, pp , 1-4 May

19 Baseband modulator Differential Encoding, DSSS, Pulse Shaping and Tchip generation Q rcos LUT Sinc amp signal Tchip entries -3 Chip Stream D qclk signal Tchip Q Clk + D 1 nq rcos iclk Q Pulse shaped signal Clk I rcos ni rcos - f clock = 32 Mhz - T Chip = 106 * Tclock = us us 19

20 Digital Downconversion Moving information to baseband - Filtering Mixes input with a local 4.3 MHz sin generated in the same way characteristics that the one present in the IF upconversion stage of the transmitter. Low-pass filtering and decimation (sample-rate reduction) via a Cascaded Integrator-Comb (CIC) filter. - It only uses addition and substraction arithmetics (multiplication) embedded. - Its frequency response envelope is like sin (x) / x FIR compensation. I I fs R C C fs / R a) N = 5 (stages), M = 2 (delay) and R = 16 Integrator Comb b) fcut-off = 300 Khz - Nulls placed at multiples of (f s/r) / M = 1 MHz 20

21 DPLL (Digital Phase Lock Loop) Generating the chip sampling clock (Ts_chip) When DPLL is synchronized with data stream, the received signal is sampled in the centre point of chip cell (Ts_chip). Using a sampling rates (fs) of 8 MHz, we obtain that: Ts_chip 27 x Ts Ts_chip + 1 = Ts_chip Sampling is delayed Ts_chip Ts_chip + 1 = Ts_chip Sampling is advanced T chip 21