VLSI IMPLEMENTATION OF MODIFIED DISTRIBUTED ARITHMETIC BASED LOW POWER AND HIGH PERFORMANCE DIGITAL FIR FILTER Dr. S.Satheeskumaran 1 K.
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1 VLSI IMPLEMENTATION OF MODIFIED DISTRIBUTED ARITHMETIC BASED LOW POWER AND HIGH PERFORMANCE DIGITAL FIR FILTER Dr. S.Satheeskumaran 1 K. Sasikala 2 1 Professor, Department of Electronics and Communication Engineering, Anurag Group of Institutions, Hyderabad, India 2 Assistant Professor, Department of Electrical and Electronics Engineering, VELS University, Chennai, India Abstract Digital FIR filter is popularly used in Signal Processing for noise removal and related applications. In this paper, we present Modified Distributed Arithmetic (DA) Based Digital FIR filter that consumes less power than the existing digital filters. Modified DA architecture is proposed using register reuse technique. We designed an 8 tap 16 bit programmable coefficient digital finite impulse response (FIR) filter for solving the high power consumption issues. The filter output is realized through a series of delays, multipliers and adders. To realize in hardware, the design was implemented in Cadence Design Tools such as NCLaunch, RTL compiler, SoC Encounter. SoC encounter generates a GDSII file which gives detailed specification for manufacturing the semi-custom design. Our design has been simulated using Verilog hardware descriptive language. The measured maximum clock speed is 70 MHz and the total die area is 0.66 mm 2. The total power consumed is 23mW which is low compared to the existing designs. Keywords: FIR filter, SoC Encounter, Verilog HDL, multipliers, adders. 1. INTRODUCTION Signal processing and filtering are the two most frequent operation in many biomedical applications, instrumentation, speech and audio processing, data communication and robotics. FIR digital filters are widely used in digital signal processing by virtue of stability and easy implementation. Though Commonly digital FIR filter is implemented using digital signal processor, DSP designs are more expensive when large bandwidth signals are involved. Sufficient resolution for wide bandwidth DSP applications are not supported because of either much expensive or non-availability of fast analog-to-digital converters / digital-to-analog converters [1]. Digital-signal processing (DSP) chips, although immensely popular, tend to be large and power-hungry; thus applications that require both high throughput and low power employ special-purpose digital VLSI circuitry [2]. To realize the fully customized Digital FIR filter, the design is implemented using Cadence Design Tools FIR filters are said to be finite because they do not have any feedback. For an N-tap FIR filter with coefficients h(k), output y(n) is described as: y(n)=h(0)x(n) + h(1)x(n-1) + h(2)x(n-2) +... h(n-1)x(n-n-1), (1) y(n) =k=0σ M h (k) x (n-k) (2) From the above equation we can see that the impulse response becomes zero after time M=N-1. The filter's Z Transform: H(z)=h(0)z -0 + h(1)z -1 + h(2)z h(n-1)z -(N-1) (3) FIR filter is a linear filter whose output is a linear function of the input. Any output value 59
2 of a linear filter is the weighted mean of input values [3]. In other words, to form one element y(t) of the output at time t, it is necessary to multiply the input values for time moments adjacent to t by coefficients and to sum up the products. Since FIR filters do not use feedback, only those outputs which are actually going to be used have to be calculated. In contrast, since IIR filters use feedback, every input must be used, and every input must be calculated because all inputs and outputs contribute to the feedback in the filter [4]. Thus here we have designed a usual FIR filter using Verilog HDL and realized in hardware by implementing it in Cadence using Cadence Design Tools. The Cadence benefits the user with less time for realizing any complex design in hardware. It helps us optimizing the design even before it is physically realized, i.e. the tools help the user know whether the design will meet its target or not in beforehand and hence the user can revisit the designing steps to make the design meet its target [5]. The Cadence implemented designs consumes less power with larger clock frequency within a small die area. The next chapter discusses the system description. In this paper, we present Modified Distributed Arithmetic (DA) Based Digital FIR filter that consumes less power than the existing digital filters. Modified DA architecture is proposed using register reuse technique. We designed an 8 tap 16 bit programmable coefficient digital finite impulse response (FIR) filter for solving the high power consumption issues. 2. LITERATURE REVIEW FIR filter is a linear filter usually implemented with low power dissipation and small area. In the year 2013, Garrido presented few Techniques for Magnetic Hard Disk Drive Read Channel Equalization. In the design Sample and hold amplifiers were incorporated for analog delay line. The fabricated design consumed a power of 200 mw [6]. Since the analog implemented filters were not successful due to the problems such as offset, error accumulation, and noise sensitivity which limit the filter s scalability and resolution. And hence digital FIR filters are preferred over analog. The most common limitation of a digital FIR filter is finite word length. This can be minimized by a technique named compensating zeroes, where the filter is divided into smaller, cascaded sections such that the finite word-length effects in one section are guaranteed to compensate for the finite word-length effects in the other section. Zhang et al (2015) proposed a continuous-time delta-sigma modulator for biomedical ultrasound beamformer using digital ELD compensation and FIR feedback [7]. When implemented in digital signal processor for higher order coefficients hardware requirements, arithmetic operations, area usage, and power consumption increases drastically [8]. To minimize these factors an algorithm by which FIR filter frequency and phase response can be represented with a minimum number of non-zero coefficients [9]. Adaptive digital FIR filter has been implemented using novel least mean square (LMS) algorithms for noise removal applications [10]. DSP algorithm has been developed for adaptive FIR filter using VHDL and Verilog HDL for implementing in VLSI circuits [2]. The developed program generated behavioral description of the FIR filter. They also made comparison between the two hardware descriptive languages and their program implementations [11]. The FIR filter was implemented in FPGA as the next step of advancement. For optimizing the filter function they adopted certain algorithms or techniques. [12]. Later optimization was made in FPGA implementations such as reducing the number of slices and number of LUTs and also reducing the power consumption [13]. Another innovative approach, implementing FIR in FPGA with embedded RAM for loading the coefficients value. 3. PROPOSED TECHNIQUE DA based FIR filter design has been used in many VLSI architectures for the power consumption reduction. In this paper, we present Modified Distributed Arithmetic (DA) Based Digital FIR filter that consumes less power than the existing digital filters. Modified DA architecture is proposed using register reuse technique. We designed an 8 tap 16 bit programmable coefficient digital finite impulse response (FIR) filter for solving the high power consumption issues. Figure 1 shows the block diagram realization the proposed filter for the backend implementation. The algorithm for designing and simulating the FIR filter using Verilog HDL is as follows. 60
3 STEP 1: A module is created, the control signals variables such as configure and reset and the input, output and the coefficient variables each of 16 bits, and are declared. STEP 2: A memory array for storing the 8 tap coefficients each of 16 bits is created. STEP 3: Internal registers for multiplier and adder blocks are declared. STEP 4: The input data is shifted to cause delay using D flip-flop. STEP 5: When the reset control signal is active, the memory, multiplier and adder blocks are initiated. STEP 6: The coefficients are configured and stored in the memory array, when configure control signal is active. STEP 7: When the configure signal is passive, the delayed inputs are multiplied with the coefficients and the resulting products are added to generate the filter output. STEP 8: The above design is checked for various coefficients representing low pass, band pass, high pass and band stop filters using a test bench. Figure 1: Detailed filter function realization First the input data is passed thro the shift registers, there by causing delay. C0, C1, C2, C3, C4, C5, C6, C7 are the coefficients which are configured during the configuration cycle in the beginning. The delayed input is multiplied with the corresponding coefficient by the multiplier. The resulting products are added to form the filter output. The adders are implemented in two stages. All the adders together can be referred as accumulator. The output of the adder and the multiplier is registered. 61
4 4. RESULTS Firstly the filter is realized using Xilinx ISE software. The above FIR filter design was coded and simulated using Verilog HDL. The output obtained after simulating the Verilog code using Xilinx is shown in Figure 2 Figure 2 Simulation output in Xilinx The synthesis report generated after synthesizing the design in Xilinx is provided below: Device utilization summary: Selected Device: 3s400pq208-4 Number of Slices: 9 out of % Number of bonded IOBs: 34 out of % IOB Flip Flops: 16 Number of GCLKs: 1 out of 8 12% Timing Summary: Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: 3.084ns Maximum output required time after clock: 7.165ns Maximum combinational path delay: No path found Timing Detail: Total number of paths / destination ports: 32 / 32 Offset: 3.084ns (Levels of Logic = 1) Source: reset (PAD) Destination: d16/q (FF) Destination Clock: clk rising Data Path: reset to d16/q Total Gate Delay: 3.084ns (1.847ns logic, 1.237ns route) (59.9% logic, 40.1% route) 62
5 Figure 3 show the result obtained using Cadence simvision which is the ouput generated earlier in the xilinx Table 1 Synthesis report Cell: in- >out fanout Gate Delay Net Delay Logical Name (Net Name) FDR:C- >Q OBUF:I- >O d16/q (d16/q) o_15_obuf (o<15>) DELAYED INPUT DATA FILTER OUT Figure 3: Simvision - waveform window Thus the FIR filter design is implemented using the NCLaunch tool in the Cadence. Steps: 1. Prepare the Verilog: A text file is opened and the verilog code of the design is written. And saved in the HDL directory of the newly created directory. 2. Invoke Cadence RTL Compiler: Make sure that you have sourced the right.cshrc file so the PATH settings are correct. At your top-level directory for the project, invoke Cadence RTL Compiler from the UNIX prompt: 3. Read and Elaborate RTL: Design can be read using read_hdl. It reads in your VHDL/Verilog files and creates HDL independent objects in HDL-intermediate format and stores it in design library. The elaborate command elaborates the top-level design to bind all the packages and the designs. 63
6 4. Synthesize: To synthesize the design, following commands are typed at the unix command prompt: rc:/>synthesize -to_generic rc:/>synthesize -to_map These scripts will map and optimize the design with high mapping degree. 5. Analyze timing and power: There are many commands and tools in RTL Compiler to aid you in analyzing the timing, power and other performance. 6. Define clock and Set the constraints: After analyzing the timing report, define the clock with a positive slack using the following command. 7. Writing files: To have the output as SDC and HDL file, the following commands are used: rc:/designs>write_hdl<modulename>>/hom e/...path /net_filename.v rc:/designs>write_sdc> /home/ path /net_filename.sdc The 8 tap 16 bit coefficient fir filter in schematic is provided in figure 4 Figure 4 RTL Schematic View 64
7 The final layout generated is shown in figure 5. Interconnections Cell Instances Figure 5: Layout view of FIR filter design The GDSII file gives detailed specification of the entire design so that any vendor can manufacture the semi custom design. Thus the 8-tap 16 bit coefficient FIR filter design is implemented in Cadence. Thus the implementation of FIR filter design in Cadence using Cadence Design Tools is explained in detail with the design flow and the instructions employed. The next chapter yields the conclusion of our project. 5. CONCLUSION AND FUTURE SCOPE We have successfully built an 8 tap 16 bit programmable coefficient digital finite impulse response (FIR) filter using modified DA architecture and successfully implemented in Cadence using Cadence Design Tools such as NCLaunch, RTL Compiler and SoC Encounter. This implementation results in high speed and low power design. The design, when implemented in FPGA consumes 56mW which is reduced to 23mW when implemented in Cadence. And the clock frequency is measured as 70MHz. The slack is decreased to +70ps in cadence from +765ps when implemented in FPGA. The total die area is found to be 0.66mm 2.. The development of analog and mixed-signal circuits around these devices enables small high-throughput low-power VLSI systems. Thus the mixed signal approach to design high performance and low power Finite Impulse Response (FIR) filter employs digital delay lines, synapse transistors for weight storage and updates, and mixed-signal hardware for compact low-power four-quadrant arithmetic. In brief, p-channel synapse transistors used as analog memory cells, and mixed-signal circuits for fast low-power arithmetic. REFERENCES [1]Mohanty, B. K., Meher, P. K., Singhal, S. K., & Swamy, M. N. S. (2016). A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic. Integration, the VLSI Journal, 54, [2]Satheeskumaran, S., & Sabrigiriraj, M. (2015). VLSI implementation of a new LMS- 65
8 based algorithm for noise removal in ECG signal. International Journal of Electronics, 103(6), doi: / [3]Mohanty, B. K., & Meher, P. K. (2016). A high-performance FIR filter architecture for fixed and reconfigurable applications. IEEE transactions on very large scale integration (vlsi) systems, 24(2), [4]Sharma, P. K., Khan, M. T., & Ahamed, S. R. (2016, September). An alternative approach to design reconfigurable mixed signal VLSI DA based FIR filter. In Technology Symposium (TechSym), 2016 IEEE Students (pp ). IEEE. [5] Pan, Y., & Meher, P. K. (2014). Bit-level optimization of adder-trees for multiple constant multiplications for efficient FIR filter implementation. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(2), [6] Garrido, N. (2013). Available Techniques for Magnetic Hard Disk Drive Read Channel Equalization. [7] Zhang, Y., Chen, C. H., He, T., & Temes, G. C. (2015). A continuous-time delta-sigma modulator for biomedical ultrasound beamformer using digital ELD compensation and FIR feedback. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(7), [8] Park, S. Y., & Meher, P. K. (2014). Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter. IEEE Transactions on Circuits and Systems II: Express Briefs, 61(7), [9] Park, S. Y., & Meher, P. K. (2013). Lowpower, high-throughput, and low-area adaptive FIR filter based on distributed arithmetic. IEEE Transactions on Circuits and Systems II: Express Briefs, 60(6), [10]Satheeskumaran, S., & Sabrigiriraj, M. (2014). A New LMS Based Noise Removal and DWT Based R-peak Detection in ECG Signal for Biotelemetry Applications. National Academy Science Letters, 37(4), doi: /s [11] Hsiao, S. F., Jian, J. H. Z., & Chen, M. C. (2013). Low-cost FIR filter designs based on faithfully rounded truncated multiple constant multiplication/accumulation. IEEE Transactions on Circuits and Systems II: Express Briefs, 60(5), [12] Reddy, K. S., & Sahoo, S. K. (2015). An approach for FIR filter coefficient optimization using differential evolution algorithm. AEU- International Journal of Electronics and Communications, 69(1), [13] Gao, Z., Reviriego, P., Pan, W., Xu, Z., Zhao, M., Wang, J., & Maestro, J. A. (2015). Fault tolerant parallel filters based on error correction codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(2),
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