Global Design Analysis for Highly Repeatable Solid-state Klystron Modulators

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1 CERN-ACC-2-8 Global Design Analysis or Highly Repeatable Solid-state Klystron Modulators Anthony Dal Gobbo and Davide Aguglia, Member, IEEE CERN, Geneva, Switzerland Keywords: Power conversion, power semiconductor switches, stochastic systems Abstract CERN-ACC /1/2 This paper presents an analysis o the repeatability issue in the electrical-to-radio requency conversion chains using pulsed klystrons. The ocus is on the power electronics used in klystron modulators. Repeatability deinition is presented and simulation results allow deriving important conclusions regarding the voltage repeatability harmonic content versus power electronics design directions. The trade-o between klystron modulator and low level RF controls is a key point or optimizing the global system repeatability perormance. Presented at: IEEE IPMHVC, 1- June 214, Santa Fe, US Geneva, Switzerland January, 2

2 Global Design Analysis or Highly Repeatable Solid-state Klystron Modulators Anthony Dal Gobbo and Davide Aguglia, Member, IEEE CERN-European Organization or Nuclear Research, Technology Department, Electrical Power Converter Group, 1211 Geneva 23, Switzerland ; ABSTRACT This paper presents an analysis o the repeatability issue in the electrical-to-radio requency conversion chains using pulsed klystrons. The ocus is on the power electronics used in klystron modulators. Repeatability deinition is presented and simulation results allow deriving important conclusions regarding the voltage repeatability harmonic content versus power electronics design directions. The trade-o between klystron modulator and low level RF controls is a key point or optimizing the global system repeatability perormance. Index Terms Power conversion, power semiconductor switches, stochastic systems 1 INTRODUCTION A new accelerator, the Compact Linear Collider (CLIC), is under study at CERN [1]. This accelerator requires a very tight speciication in terms o Radio Frequency (RF) repeatability rom the klystrons used to accelerate the drive beam. RF perormances are directly linked to the quality o the High Voltage (HV) pulse produced by the klystron modulators as well as the Low Level RF (LLRF) control. Feed-back control loops are used to stabilise the modulator output pulsed voltage and to control the RF phase and amplitude. Figure 1 illustrates a simpliied principle schematic o the power lows and the main control loops. The modulator output voltage is typically characterised by a given harmonic content (ripple) and by some voltage stability. This can be translated into RF phase and amplitude undesired deviations. This issue has been analysed in [2]. HV re. Modulator Power electronic components HV reg. HV meas. Pulsed HV RF reg. Klystron loop delay RF power RF phase meas. acc. cavity beam RF drive (phase) Figure 1. General schematic o the conversion chain and main control loops. A 1ppm to ppm HV pulse repeatability is preliminarily required rom CLIC modulators. Being an extremely tight speciication, one has to evaluate the trade-o between modulator voltage repeatability and LLRF control capabilities. LLRF eedback control can be used to attenuate the statistical eects o not perectly repeatable voltage pulses (LLRF eedorward compensation being unable to comply with random perturbations). The LLRF control repeatability attenuation capability (in db) is deined over a range o requencies (Bode representation). This LLRF control characteristic shall be known in order to take important modulator design decisions, where the voltage repeatability harmonic content can be deined. Beore entering in a phase o global design optimisation, this paper aims to clearly deine the pulsed voltage repeatability, identiy the main sources o non-repeatability, and give a lavour o the expected voltage repeatability and its harmonic content or typical power electronics topologies used in a modern klystron modulator. 2 SOURCE OF NON-REPEATABILITY IN MODERN KLYSTRON MODULATORS Modern klystron modulators are composed o power electronics sub-components (switch mode power converters). They oer the possibility o easily changing the voltage level, the pulse length, and to operate in eedback. The main power conversion concept based on power electronics is important or the ollowing analyses and is illustrated in Figure 2, where a constant DC voltage can be eiciently converted into a variable, and controllable, one. DC Voltage Switch control O Switch Filter V out Figure 2. Pulsed power converter principle diagram.

3 A constant DC voltage is chopped by one or several controlled switches operating either in their "on" (conducting) or "o" (non-conducting) states at medium requencies (typically 1kHz to khz, depending on the modulator topology). The output voltage is obtained using power ilters, which design must consider the trade-o between residual output ripple and bandwidth to produce a pulsed voltage [3]. When operating a switch mode power converter, switches are aected by a random turn-on and turn-o time jitter. At nano-scale, quantum physics and statistical physics drive the behaviour o charge carriers within switch semiconductor layers, and the jitter has a stochastic behaviour which can be described by a Gaussian distribution. As a consequence the output voltage o such power converters presents a stochastic behaviour with respect to the switch control signal. The nonrepeatability o a power converter may be aected by other phenomena such as temperature variations or electro-magnetic perturbations; however, it is assumed here that the major contributor is the switches jitter. Figure 3 illustrates a simpliied visualization o the switch jitter impact on turn-on and turn-o time lags with respect to the switch control (rom a driver). The hypothesis assumed in this work lies in the consideration o an instantaneous switch transition (μs or turn on and o). Switch Control Switch State Switch Jitter O Average turn-on lag Average turn-o lag time Figure 3. Schematic o the switch jitter: the dashed line represents the switch control signal and the red line the switch most probable actual state. Figure 4 shows the eect o switch jitter on the output voltage considering an arbitrary common switch control pattern (PWM). O Switch control V 1 V 2 time Figure 4. Inluence o switch jitter on output voltage. For the very same switch control signal, an example o two possible switch states (dotted lines) and the resulting iltered output voltages (ull lines) are represented. 3 PULSE REPEATABILITY DEFINITION In order to deine the Pulse Repeatability (PR), the matrix V in equation (1) represents the voltage o a set o N pulses o length t : V1 1) V1 2 )... V1 ) V2 1) V2 2 )... V2 ) V = (1) VN 1) VN 2 )... VN ) V i (t j ) is the voltage o the pulse i at the time t j. Since switch jitter, and consequently the converter repeatability, is a stochastic phenomenon, there is no correlation between any pulses o a given set. Thereore, a set o N voltage samples or a given time t j (one column o the V matrix) can be seen as the realization o the random variable X tj o standard deviation σ Xtj. In practice, one can calculate the standard deviation σ tj o N voltage samples and approach σ Xtj by increasing the number o samples N. The higher the considered number o pulses and time samples, the higher the accuracy in estimating the repeatability. 3.1 REPEATABILITY TOLERANCE INTERVAL The switch jitter induces Gaussian distributed voltage dispersion at each time t j (rom t 1 to t ) within the pulses as shown in Figure. A tolerance interval α which deines the probability or pulses to meet the repeatability speciication such that the pulse repeatability at the time t j is PR tj =α.σ tj must be introduced. Table 1 shows the percentage o pulses which meet the speciication or dierent values o α. voltage α Table 1. Probability to meet the spec. vs. tolerance interval probability to meet the spec. at time t j ~ 68.2% ~ 9.4% ~ 99.7% Repeatability = α.σ 2σ 68.2% 4σ 13.6% 13.6% -3σ -2σ -1σ μ 1σ 2σ 3σ time Figure. Pulse voltage Gaussian dispersion. 3.2 REPEATABILITY CALCULATION At each time t j, the standard deviation σ tj o a set o X tj realization is derived rom the columns o matrix V. Finally, the PR is obtained by multiplying the greatest σ tj obtained (worst case) by the tolerance interval α: PR = max( α. σ ) (2) tj This quantity is the maximum accepted voltage dierence between any two pulses but it might be exceeded a certain percentage o time, deined by the tolerance interval.

4 4 REPEATABILITY EVALUATION EXAMPLES 4.1 TYPICAL POWER ELECTRONICS TOPOLOGIES IN KLYSTRON MODULATORS Klystron modulator design requires an eort in inding the best compromises between voltage bandwidth (pulse rise/all times) and ripple. To decrease the ripple amplitude, one can: 1) Reduce the ilter band-pass: which also increases the pulse rise/all times. 2) Increase the switching requency: action limited by the switches technology and associated losses. Figure 6(a) shows the topology (buck) o a basic DC/DC, one quadrant converter (positive output voltage and current). A way o increasing the resulting output switching requency o a power electronic converter consists in placing several parallel switching circuits (as illustrated in Figure 6(b)), operated in a phase shited way (interleaved). With this solution the converter bandwidth (thus the rise/all time) is conserved whereas the ripple is reduced. The equivalent switching requency is given by eq =n pc. single where n pc is the number o parallel circuits, eq and single are the equivalent and the single circuit switching requencies respectively). Topologies in Figure 6 are typically used in modulator subcomponents (e.g. the so-called active bouncer []) SIMULATION RESULTS AND DISCUSSION For the sake o simpliication, suppose that topologies in Figure 6 are representing a very simpliied klystron modulator, where R kly emulates the klystron equivalent resistance (or a given voltage) seen rom the primary o the necessary high voltage pulse transormer. Illustrative simulations have been carried out or these two topologies operated with two dierent switching requencies: 1) Single switch buck topology (Figure 6(a)) operated with single =khz and single =khz. 2) -phase interleaved buck topology (Figure 6(b)) operated with single =1kHz and single =1kHz. For comparison purposes the output ilter (L-C) is kept unchanged in all simulations which also allow keeping the same converter dynamics (voltage bandwidth). The considered main simulation parameters are listed in table 2. (a) (b) S 1 S 2 S 3 S 4 S I 1 D 1 S D L D 2 D 3 D 4 D Figure 6. (a) Single phase and (b) ive-phase interleaved buck converter schematic. I 2 I 3 I 4 A magniication o the lat-top voltages produced by the two topologies or an equivalent switching requency o khz and khz are presented in Figure 7(a) and 7(d) respectively. It is clear that keeping the equivalent, output, switching requency but decreasing the single switching requency using multiphase inerleaved topologies, improves the repeatability (PR on Figure 7(b) and 7(e)). However, it can be observed that or very high switching requencies (khz), high requency repeatability amplitudes decreases, as illustrated in Figure 7(d), 7(e) and 7(). To analyse the requency content o the PR, FFTs were perormed and results are depicted in Figure 7(c) and 7(). Finally, one can notice the ollowing general tendencies; selecting lower switching requencies, implies a wider spectrum o the repeatability unction, whereas higher switching requencies produce worse repeatability at lower requency regions. Table 2. Base parameters o multiphase buck converters under study DC-Bus Voltage Vin 4 V Duty cycle D.7 - Equivalent switching requency eq - khz Number o phases n 1- - Switching requency single eq /n khz Output ilter inductance(s) L 6.4.n μh Output ilter capacitance C F 2 μf Resistive load (klystron) R Kly.37 Ω Switch jitter J sw 1 ns The design decision o the klystron modulator highly depends upon the klystron s LLRF control. Likely, the LLRF eed-back control would be able to better compensate or lower requency voltage repeatability phenomena, driving the design o the power electronics sub-modules toward the selection o higher switching requencies. I I Tot C F L 1 L 2 L 3 L 4 L R Kly I Tot C F V Kly R Kly V Kly

5 Voltage(V) PR (ppm) (a) eq =khz Time(ms) (b) eq =khz Voltage(V) PR (ppm) Time(ms) 4 (e) eq =khz (d) eq =khz Amplitude (ppm) Time (ms) 3 2 (c) eq =khz 2 Zoom Single phase topolgy Frequency (khz) Amplitude (ppm) Time (ms) 3 () eq =khz Frequency (khz) Figure 7. Comparison o output voltage rom single phase (grey) and multiphase (black) power converter or a switching requency o khz (a)(b) and (c) and khz (d)(e) and ().Example o pulse lat tops (a) and (d). PR vs. time (b) and (e). Frequency spectrum (c) and (). CONCLUSION The RF repeatability issue in the modulator-klystron conversion chain should be approached considering an integrated design o the power electronics systems and the LLRF controls. Depending on the LLRF controls capabilities, important design decisions can be taken or the modulator, such as the switching requency and the power-electronics subcomponents topology. With higher equivalent switching requencies o modulator sub-components, the repeatability harmonic spectrum shows important amplitudes in the low requency region. This case seems to be preerable since the LLRF control could easily compensate the voltage repeatability phenomena in this requency range. REFERENCES [1] CERN - European Organization or Nuclear Research. The CLIC Programme towards a staged e + e - Linear Collider exploring the Terascale, CLIC Conceptual Design Report, 212. [2] R. Zeng, D. McGinnis and S. Molloy, Investigation o Feedback control or klystron ripple, Proceedings o IPAC212, New Orleans, Louisiana, USA, pp [3] F. Cabaleiro Magallanes, D. Aguglia, C. A. Martins, and P. Viarouge Active Damping Filter or High Bandwidth - Low Ripple Pulsed Converters, th EPE-PEMC 212 ECCE Europe, Novi Sad, Serbia, pp. DS2b.-1 - DS2b.-7. [4] R. H. Soares, D. Aguglia, Pulse-to-pulse voltage reproducibility eicient prediction method or high precision klystron modulator design, in IEEE proceedings, IPMHVC 212, San Diego, USA, pp [] D. Aguglia, 2 MW active bouncer converter design or long pulse klystron modulators, in Proc. 14 th Power Electronics and Applications conerence (EPE 211), Birmingham (UK), 211, pp. 1-1.