Optimization and implementation of a multi-level buck converter for standard CMOS on-chip integration

Transcription

1 International Workshop on Power Supply On Chip September 22nd - 24th, 2008, Cork, Ireland Optimization and implementation o a multi-level buck converter or standard CMOS on-chip integration Vahid Yousezadeh, Toru Takayama Dragan Maksimović Colorado Power Electronics Center ECE Department, 425 UCB University o Colorado Boulder, CO maksimov@colorado.edu Gerard Villar Eduard Alarcón Dept. o Electronic Engineering Technical University o Catalunya Campus Nord UPC Building C Barcelona, Spain ealarcon@eel.upc.edu

2 Outline Introduction and motivation Series-connected multiphase multilevel buck converter Ideal topology. Ampliier and regulator operation Sel-driven low-loating-capacitor PFM-operated 3-level converter Design-space optimization Mixed-signal implementation in 0.25µm TSMC CMOS Air-core bondingwire-based inductor, tapered buer and transistor design Inductor current zero-crossing detection circuit Conclusions

3 Outline Introduction and motivation Series-connected multiphase multilevel buck converter Ideal topology. Ampliier and regulator operation Sel-driven low-loating-capacitor PFM-operated 3-level converter Design-space optimization Mixed-signal implementation in 0.25µm TSMC CMOS Air-core bondingwire-based inductor, tapered buer and transistor design Inductor current zero-crossing detection circuit Conclusions

4 3-Level (2-cell) Buck Converter 3-level (2-cell) converter has been proposed or high voltage inverters [Meynard et al., 1992] g 1 -g 2 & g 3 -g 4 are complementary switches g 1 and g 3 have the same duty cycle V C = ½ V in g 1 g 3 V SW V C (D > 0.5) V in V in -V CV in V C T s V in V in /2 0 T s /2 t Objective: Investigate potential or lower ripple/ higher eiciency / lower reactive component size / higher bandwidth realization o DC-DC converter

5 Ripple comparison o 3-level and buck converter with same s, L, C Inductor current ripple i Switching Ripple in the 3-Level Buck Converter Duty cycle D 4 times smaller peak inductor current ripple 1 imax_ n = i 2 n 1 i 2 i 3 ( ) max_ 2 Output voltage ripple v (mv) times smaller peak capacitor voltage ripple 1 vmax_ n = v 3 max_ 2 n 1 ( ) Ripple results similar to two-phase converter, but with a single, smaller inductor

6 3-Level (2-cell) Buck Converter Comparison o 3-level and buck converter For v max = 12 mv, s_3 = 200 khz, s_2 = 560 khz η 2 = 0.83 and η 3 = 0.92 improved eiciency Same s, v o i L L 3 = 0.25L 2, C 3 = 0.5C 2 reduced area Example application to switching power ampliier

7 Two-Tone Signal Generation Using a 3-Level and a Buck Converter A two-tone signal generated with a three-level and a buck converter. Switching requency, s = 1MHz, sig = 100kHz, o = 550kHz, Q = 1

8 Experimental Envelope Tracking Waveorms V out Frequency spectrum V out o V out Frequency spectrum o V out Harmonic components o rectiied sinusoid Switching harmonics Harmonic components o rectiied sinusoid Switching harmonics Standard buck converter 3-level buck converter Standard buck and 3-level buck compared or the same open-loop bandwidth and the same switching requency Modulation: rectiied sine-wave at m = 20 khz 30dB lower switching-requency harmonic in the 3-level converter

9 Flying capacitor voltage control sample sample V SW g 1 g 3 g 1 C x g 3 g 4 + V C - V SW V in -V C V C V in -V C V C V in V in /2 V in g 2 0 T s /2 t Digital (verilog) controller implementation using FPGA T s x and y are sampled at V sw = V C or V sw = V in - V C g 1 =d(t) g 3 =d(t)+ d y x + _ + _ V in /2 - V q /2 V SW V in /2 + V q /2

10 Experimental waveorms or lying capacitor voltage control V in -V c V c V sw g 1 V in -V c V c Uncontrolled capacitor C x voltage g 3 D > 0.5 D < 0.5 V sw g 1 V in -V c V c Controlled capacitor C x voltage V in -V c V c g 3 D > 0.5 D < 0.5

11 Outline Introduction and motivation Series-connected multiphase multilevel buck converter Ideal topology. Ampliier and regulator operation Sel-driven low-loating-capacitor PFM-operated 3-level converter Design-space optimization Mixed-signal implementation in 0.25µm TSMC CMOS Air-core bondingwire-based inductor, tapered buer and transistor design Inductor current zero-crossing detection circuit Conclusions

12 3-level sel-driving PFM low-cx buck converter Low-C x resonant 3-level buck converter in DCM. Sel-driving transistor-level topology Sel-driving scheme to interconnect power transistors and drivers, which reduces the voltage across the power MOSFETs gate dielectric.

13 3-level sel-driving PFM low-cx buck converter Use o core transistors to implement the power MOSFETs Use o core transistors to implement power drivers o P 2 & N 2 Reduces the power consumption o the power drivers 37 MHz switching requency 26 nh inductance Driver supply voltage and vgs or all power MOSFETs, Cadence transistor-level simulations.

14 3-level sel-driving PFM low-cx buck converter Output voltage ripple as a unction o V o, or the 3-level (C x sweep) and the classical (dotted line) Buck converters. L=35nH C o =30nF s =25MHz V bat =3.6V V o =1V I o =100mA Control signal-to-output voltage transer unction comparison between the 3-level (C x sweep) and the classical (dotted line) Buck converters. Representative waveorms corresponding to a DCM operated 3-level Buck converter, duty cycle below 50%

15 Outline Introduction and motivation Series-connected multiphase multilevel buck converter Ideal topology. Ampliier and regulator operation Sel-driven low-loating-capacitor PFM-operated 3-level converter Design-space optimization Mixed-signal implementation in 0.25µm TSMC CMOS Air-core bondingwire-based inductor, tapered buer and transistor design Inductor current zero-crossing detection circuit Conclusions

16 Circuit topology considerations Optimized design space exploration (II) 1) Model each perormance index (ripple, eiciency and area) as a unction o design parameters: inductor, capacitor and switching requency + i in + V in - R W +R C T s =1/ s T on il L Q 1 Q 2 d(t) C i out + V out - R A priori parameters and assumptions are application-oriented: topology, V in, V out, and the target IC technology parameters. D=T on /T s Output voltage ripple v o = VoDT RC s = VoD RC s = v o ( L, C, s ) Eiciency Occupied area Vin I L PL DC PL core PQ all η = = V I in L Area = AC + AL + 2AQ = area ( L, C, s ) η ( L, C, s )

17 = Γ j n j j i n i i n x x x x x x j i ) ( ) ( ) ( 1,..., 1,...,,..., 1 γ γ β β ),, ( ),, ( ),, ( ),, ( 2 s v s A s s C L C L C L C L o = Γ η L L L L L L L L C C C C C C C C η v o A Γ s ={1MHz,100MHz}, L={10nH,1uH}, C={10pF,10nF} Optimized design space exploration (III) Circuit topology considerations 2) Deine a merit igure encompassing the perormance indexes to be maximized or minimized generic merit igure Boost converter case example merit igure Occupied area Eiciency Output voltage ripple Merit igure Note that the area dependence is square-weighted so as to solve the ill-conditioned solution o vo when A 0.

18 Circuit topology considerations Optimized design space exploration (IV) Design example or a standard 0.35 µm CMOS technology 3) Obtain optimum point within design space (L,C, s ) as regards eiciency, occupied area, unctionality V out (V) I L (A) Specs: vo =0.1 V i out =0.4 A Optimization result: L= 30 nh, C=, s = 50 MHz + i L i in 0.82 Ω 30 nh 2.5 V W=3352 µm L=0.35 µm k core= δ L=0.04 H/m 2 W=3352 µm L=0.35 µm W=2500 µm L=2500 µm i out V Ω

19 Optimized design space exploration 3-level converter design example or a standard 0.25 µm CMOS technology Design space exploration o a CMOS-compatible 3-level converter: 70% eiciency, 5mm 2 silicon and s =37 MHz

20 Outline Introduction and motivation Series-connected multiphase multilevel buck converter Ideal topology. Ampliier and regulator operation Sel-driven low-loating-capacitor PFM-operated 3-level converter Design-space optimization Mixed-signal implementation in 0.25µm TSMC CMOS Air-core bondingwire-based inductor, tapered buer and transistor design Inductor current zero-crossing detection circuit Conclusions

21 Bondwire triangular spiral inductors in standard CMOS Area underneath inductor is usable or capacitors and power MOSFETs

22 Power MOSFETs Complete loss optimization o on-chip CMOS synchronous rectiier W P = 3092µm W N = 2913µm power drivers with 7.59 and 7.48 tapering actors Overall losses 37.1mW Breakdown o loss distribution, corresponding the optimized design o power MOSFETs and their associated drivers.

23 Power MOSFET gate drive design Additional degree o reedom: impact o W p upon eiciency and delay Q i and Q e1 variation as a unction o the PMOS channel width o the minimum inverter (W n = 0.3µm) t ri and t re1 parameter variation Total energy losses as a unction o the number o inverters n and the minimum inverter PMOS channel width W p. The area includes all the designs constrainted to a propagation delay lower than 1.15 ns.

24 il=0 detection circuit. Event detection i L >0 i L <0 The body diode o the NMOS power switch turns-on as a consequence o a premature cut o o the power transistor Inductor current charges the x-node parasitic capacitor and a positive voltage pulse appears in Vx voltage, due to late cut o o the power transistor 7.7

25 il=0 detection circuit. Circuit or time adjustment. Inductor current observer

26 il=0 detection circuit Mixed-signal implementation in 0.25µm CMOS i L >0 N 1 N 2 i L <0 7.9

27 Time-domain perormance o il=0 detection circuit Beore adjustment Ater il=0 adjustment 7.10

28 Complete integrated 3-level CMOS switching power converter 2630 µm 2370 µm P 1 P 2 N 1 N2 7.17

29 Full-transistor-level circuit results (I) 7.19

30 Full-transistor-level circuit results (II) 7.20

31 Full-transistor-level circuit results (III) 7.21

32 Experimental results

33 Outline Introduction and motivation Series-connected multiphase multilevel buck converter Ideal topology. Ampliier and regulator operation Sel-driven low-loating-capacitor PFM-operated 3-level converter Design-space optimization Mixed-signal implementation in 0.25µm TSMC CMOS Air-core bondingwire-based inductor, tapered buer and transistor design Inductor current zero-crossing detection circuit Conclusions

34 Conclusions Three-level converter results in avorable trade-os in terms o decreasing the switching ripples, decreasing the switching requency, reducing the size o the ilter elements, increasing the converter open-loop bandwidth, or increasing the converter eiciency. The 3-level converter with low-cx, sel-biased drivers and operating in DCM/PFM has been presented as a candidate or DC-DC converter integration The use o the sel-driving scheme to supply the drivers allows the use o thin-oxide transistors which increases the perormance o the switches. Design optimization results in the 3-level converter outperorming the Buck converter. Future research lines Linear-assisted scheme or multilevel converters Explore extending the approach to more intermediate levels Use dierent modulations (e.g. asynchronous sigma delta) Applying time optimal control