Study On Two-stage Architecture For Synchronous Buck Converter In High-power-density Power Supplies title

Transcription

1 Study On Two-stage Architecture For Synchronous Buck Converter In High-power-density Computing Click to add presentation Power Supplies title Click to edit Master subtitle Tirthajyoti Sarkar, Bhargava C.V., Mona Click to Ritu add date Joshi, Sodhi, Steve Sapp Presenter: Art Black, Fairchild Semiconductor 11/14/2012

2 Outline Background Overview of the architecture Device models and simulation framework Key representative results efficiency and loss Filter inductor sizing Summary and conclusions 2

3 Background 3 Next-generation computing power supplies (for desktops, servers, and notebooks) aspire to have higher power density. Higher switching frequency is an obviously attractive option towards that goal. Synchronous buck converter, most widely used circuit topology for computing applications, faces some problems in this regard with respect to extremely narrow duty cycles on the highside (HS) device compared to the low-side (LS) device. Further, their breakdown voltage rating is governed by the input voltage whereas the major loss comes from high conduction current, governed by the output power and low output voltage. Increased duty-cycle would be a potential solution this issue. Also, by decreasing the input voltage and using low-voltage-rating devices, efficiency and power density can be enhanced. However, because common voltage-regulator module (VRM) specifications fix the input and output voltage bounds, arbitrary choice of duty cycle or input voltage is not possible with the conventional single-stage topology. In this regard, a two-stage cascaded approach can be adopted. In this study, we illustrate some results which may yield insights on (a) advantage of the twostage approach with regard to increasing switching frequency of the stage delivering power to the load, (b) distribution of loss between the two stages, (c) switching frequency partition which separates the two-stage solution from conventional single-stage approach from power loss standpoint, and (d) simplified power density comparison among different architectures based on filter inductor size.

4 Overview of architecture First Stage Intermediate bus 5V Second Stage 12V 5V Filter Filter Load Frequency = 300 khz Frequency = 1 MHz Low-frequency first-stage with higher breakdown rated devices. 300 khz is assumed from standard VRM practice but this can go up also. Higher frequency second-stage with lower breakdown rated devices. Again, 1 MHz is assumed just for illustration. Separate or combined control loops for two stages: not simulated in this study which focuses primarily on the device and loss optimization. Choice of intermediate bus at 5 V is also for particular case illustration. This may also need detailed optimization study depending on the device architecture. 4

5 Possible flavors Case 1 and 2 12V 5V 12V 5V 12V 5V 12V 5V 12V 5V 12V 5V Simple extension of the existing 12 V 1 V multi-phase topology by breaking down the converter in two stages and inserting bus caps at each phase. Case 1. 5 One higher power primary stage followed by paralleled multi-phase second stages. Case 2.

6 Simulation platform circuit schematic Logic bias supply High side transistor Input supply Analysis done in Cadence PSpice platform (Allegro Design Entry and Allegro AMS simulator). Similar schematic used for both first and second stage. Gate driver Low side transistor Filter inductor/ capacitor Dual-output gate driver is used along with P-I controller (not shown in the schematic) to drive FETs and regulate output. Filter sizes are scaled differently for stages according to switching frequency. Complete range of bias supply, driver, and trace parasitics have been modeled in the simulation framework. Load Automated routines extract individual devices losses and overall system efficiency. 6

7 Simulation platform device models The choice of devices for these two stages is extremely critical as they determine the majority of losses in the overall system. Extensive tuning of the model parameters was done to match the DC and AC characteristics of the Pspice models to those generated from the more accurate finite-element based device physics simulations and experimental characterizations. First stage Fairchild Semiconductor s proprietary, shielded-gate, PowerTrench device of 25V breakdown rating has been chosen for the first stage. This device features very low specific on-resistance which results in ultra-small chip size for a targeted on-resistance. Because the input/output voltage ratio for the first stage is 12:5, a ratio of 1.5:1 has been chosen for the onresistances of the HS and LS devices, respectively. Also, the same device is used for benchmark study of the single-stage converter. However, in that case, the on-resistance ratio between HS and LS is changed to 4:1 owing to the fact that input/output voltage ratio would be 12:1. Second stage Lower input voltage and higher frequency operation of the second stage warrants a different type of device architecture from that of the first stage. A high-frequency 12V rated device with optimized channel length and threshold voltage has been designed and modeled for this purpose. The gate charge and parasitic capacitances have been optimized to reduce switching losses at 1 MHz. 7

8 Key results efficiency plots of first stage 98 Efficiency of First stage under low load (Case-1) 98 Efficiency of First stage under high load (Case-2) Percentage efficiency Percentage efficiency Output current in Amps Output current in Amps The low-load condition for the first-stage will occur for Case-1 where parallel stages are sharing the input power. The efficiency plot suggest switching loss dominated behavior even at 300 khz. The high-load condition for the first-stage will occur for Case-2 where single stage is processing the input power. The efficiency plot suggest conduction loss dominated behavior. However, overall the efficiency ~ 94% - 97%. 8

9 Key results efficiency plots of second stage Percentage Efficiency Percentage Efficiency Larger parasitics Reduced package parasitics Load current in Amps Load current in Amps Majority of the losses occur in the second stage for this two-stage architecture. A combination of conduction and switching loss. The distribution of loss in the second stage is expected to vary with switching frequency. When the package parasitics (e.g. source/gate loop inductances, inter-die trace inductance) are reduced, the efficiency improved because of lower switching loss. Points towards integrated/copackaged device solutions for the second stage at MHz switching regime. 9

10 Key results efficiency of combined system Percentage Efficiency Two-stage Case 1 Two-stage Case 2 Single-stage at 1 MHz Single-stage at 300kHz Output power (Watts) 10 Single-stage solution (12V 1V direct conversion) at low frequency is highest efficiency low power density. Single-stage solution at MHz frequency is worst efficiency simple scaling up frequency to achieve higher power density may lead to this performance degradation. Two-stage solutions are lying somewhere middle good balance of efficiency and power density. Also, for this particular choice of frequency and intermediate bus voltage, both Case-1 and Case-2 of the two-stage approach exhibit almost similar performance. However, this observation is most likely to change with different choice of operating frequency and bus voltage.

11 Key results is there a threshold frequency? Percentage Efficiency Light load (5 A) Two-stage Case-2 starts showing better efficiency than single-stage Frequency (khz) Percentage Efficiency Max load (25 A) Two-stage Case-1 starts showing better efficiency than single-stage Frequency (khz) Because the efficiency values of a single-stage solution at two extreme frequencies (300 khz and 1 MHz) lie on the outskirts, we calculated efficiencies at intermediate frequencies at 5 A and 25 A load currents. For this set of devices and intermediate bus voltage, simulation illustrates that only after khz, the two-stage approach starts exhibiting higher efficiency and starts becoming an attractive solution. However, this threshold frequency is expected to vary widely for different technologies of power devices used in the solution. 11

12 Filter inductor sizing comparing solutions Filter inductor value (µh) Architectures Analytical estimation of the filter inductor was done for each case. One key assumption in this estimation that the inductor must ensure a ripple current bound which is a fixed percentage (30% for current analysis) of the maximum load current through that stage In the two-stage, Case 1, increase from the single-stage case comes primarily from 5X lower maximum load current and increased duty-cycle. Difference between Case-1 and Case-2 is due to the difference in maximum load current. Also, for Case-2 there is only one first-stage phase as compared to 5 phases for Case-1. 12

13 Filter inductor sizing - phase threshold Filter inductor value (µh) 2.5 Case-2 2 Single-stage Number of parallel phases in the second stage As we saw the Case-2 yields similar filter inductor value to single-stage solution, we compare these architectures as the number of phases in Case-2 varies. We assume the final delivered power to the CPU load to be constant. So, with increasing phase number, the power handled per phase, decreases. For the singlestage case, it is equivalent to increasing the number of parallel phases. Calculations showed that for a given frequency and intermediate bus voltage, overall reduction in filter inductor value (compared to a single-stage approach) shows up only when the number of secondary phases exceeds a certain threshold. However, this is only a first-pass analysis and other factors such as maximum DC and ripple current magnitude, type and technology of the magnetic core material, and switching frequency influence the final physical size of the inductor. For a more detailed analysis of power density, these factors must be taken into account. 13

14 Summary and Conclusions Two-stage architecture may help in pushing the operating frequency in the MHz range of the final stage which will deliver power into the microprocessor, without degrading the efficiency as severely as in the case of single-stage architecture. However, advantage of two-stage over a single-stage topology starts showing up only above a certain frequency threshold. Major loss in the two-stage architecture concentrates around the high-frequency, high-current second stage which needs maximum emphasis from device and circuit optimization point of view. However, this stage contributes far less volume (from filter standpoint) as compared to the first stage. While adopting two-stage architecture, a simple parallelization of the single-stage architecture may not be beneficial from power density point of view. A single high-power first-stage followed by multiple parallel-connected second-stages may be the preferred architecture from the standpoint of filter inductor value. However, actual physical size of the inductor may depend upon other factors and the technology and type of the magnetic core material. Further, the power density benefit may show up only after the number of parallel secondary stages exceeds a certain threshold. But increasing the parallel phases may affect the power conversion efficiency. Therefore, the power density optimization must be coupled with overall loss estimation for a better system design. 14

15 Extension possibilities Intermediate bus voltage may have an optimized value for a given choice of device technology. This study assumed one fixed voltage, but the choice is wide open Non-traditional structures for the second stage high-frequency power device LDMOS? Advanced material? Fully integrated MOSFET and gate driver? Choice of switching frequencies on the two stages may be separately optimized depending on the device technology and level of integration. Filter technology for the high-frequency stage need to be carefully selected (high-density thin-film/integrated magnetics? Can these technologies cope with high current density?). Thereafter, coupled analysis of power density and loss will lead to better system optimization. 15

16 Thank You!! For questions and clarifications please contact Tirthajyoti Sarkar at 16