Fast Transient Power Converter Using Switched Current Conversion

Transcription

1 Fast Transient Power Converter Using Switched Current Conversion Laurence McGarry Advanced Engineering Technology Manager Hong Kong & China Astec Power A Division of Emerson Network Power.

2 Abstract: Next generation microprocessors continue to require power supplies capable of supporting fast transient loading. Conventional approaches to solving the fast transient issue focus on the use of interleaved buck converters. This approach is fundamentally limited due to the presence of the output inductance, limiting the converter response to a load transient. This paper introduces a novel switched current converter. The converter will switch current to the load or to ground depending on the load transient requirement, providing a theoretically infinite transient response. The research investigates the practical limitations of the converter topology, using simulation to evaluate and optimize the system design. Finally, simulation models and results are presented and suggestions for further design improvements are discussed.

3 Common Industry Trends Intel CPU requirement for VRM Intel CPU voltage and Current Roadmap Processor trends well documented : Higher Current Requirements Lower Voltage Processors, tighter regulation range Higher Frequencies Faster Transient Response

4 Conventional Industry Approaches Standard approach to resolving the challenge is to use interleaved Buck converters Response time inherently limited by the presence of the output inductor Problem compounded by interconnect and PCB parasitics Continued silicon integration, drive to higher frequencies and possibly an increased number of phases will continue to be a trend regardless of the architecture utilized Switched Current Techniques offer an alternative approach An infinite transient response possible, in theory at least 2 Conventional Buck Converter Volterra 300A/uS Module 369mm 2

5 Switched Current Concepts Currents are switched to the load or to the return path Parallel switching Current Paths are utilized Transient can be supported in the time that it takes to turn the FET On/Off When output current follows processor demand current, significant reduction in output capacitance can be observed The constant current source is derived from a Buck Converter driving a matrix Transformer configuration 2

6 Constant Current Source Front end Buck converter provides the constant current source Push Pull Converter operating at 100% duty using a Matrix transformer provides the input to the current switches at the load side Matrix Transformer: series (primary), parallel (secondary) ferrite cells forming individual isolation for each phase LHS source is constant current and could be remote from the end application. RHS Switches could be colocated with the processor to reduce interconnect parasitics and enhance transient response 2

7 System Overview and Simulation Model Front End Buck Converter providing constant current source Push-Pull Converter with Matrix Transformer provides constant current parallel paths Output Current switches; switching current to the load in response to transients or to ground Simulation model: 3 Stage Conversion -12V input to 1V, 100A output - 10 parallel switching paths

8 Constant Current Source Buck Converter Buck Constant Current Converter Simple Hysteretic Control Implemented Q3 irf V15 DRV1s irf 7822 Q4 1 E3 1 E4 5.6u IC=10.5 U17 HC74D L2 Q SET D QN RST Iout Ireturn 10m R15 10k R2 10k R1 +5Vcc 10k R8 +5Vcc U19 max961 U18 max961 Vcc NQ Q Vcc NQ Q GND X1 MAX473 1K R14 GND IN+ SHDN LE 3.3k R13 IN+ IN- Vref Low IN- SHDN LE Vref High No Output Capacitance 2 level Threshold Control 10A-11A Synch Rectification is used to reduce power loss Switching Frequency Varies according to the Buck Output voltage, reaching maximum while Voutput Buck=0.5Vin Voltage on the output of the Buck is n X Vo - Where n is the number of switches turned to the load

9 Constant Current Source Buck Converter(cont) Simulation Results light load Simulation Results Light load Buck output voltage=0.5v Output current =10.87A Switching Duty cycle=5.55% Switching Frequency=110kHz Current ripple =694mA Simulation Results Full load Simulation Results Full load Buck output voltage=11v Output current =10.69A Switching Duty cycle=93% Switching Frequency=133kHz Current ripple =760mA

10 Constant Current Source Buck Converter(cont) Simulation Results Dynamic load Output voltage slew rate=46v/us Output current =10.8A Current ripple =828mA Simulation result on dynamic load fs vs Vo Curve L=5.6uH, I=1A fs ( Vo ) Input Buck Frequency Variation The highest frequency =518kHz (output voltage =5.5V) All components are ideal Vo

11 Push Pull Converter 2n L5 2n TX1 L2 Q1 irf6603 Branch 1 Fixed Duty Cycle of 50% 10.5 I1 irf540ns Q3 4.7n C1 D1 IDE A L 2k R1 irf540ns Q4 2n L4 4.7n C3 D3 IDE A L 2k R7 2n L3 Q2 irf6603 Leakage Inductance causes increased voltage stress on Primary FETs Gate Drive Timing for Primary FETs and secondary Synchronous Rectification FETs is critical

12 Push Pull Converter Matrix Transformer Matrix Transformer Structure: Core Size 11.8 X 6 X 4 mm Coupling Coefficients: Pri-Sec 0.996, Pri-Pri 0.994, Sec-Sec Important for the Matrix Transformer cells and SRs to be in close proximity Staggered placement of the Matrix Cells on either side of the PCB facilitates optimum layout

13 Matrix Transformer Modeling Standalone With Primary Termination In The Middle 0.5mm 4.5mm Magnetising Inductance 2.07uH 2.07uH Leakage S-P 2.72nH 3.27nH 8.04nH Leakage S-S 7.11nH 7.79nH Leakage P-P 10.94nH 11.61nH Equivalent R 1.38mOhm 1.41mOhm 2.08mOhm Primary R 0.476mOhm Secondary R 0.934mOhm Magnetising Current 1.063A Core Loss 0.375W

14 Push Pull Converter Drive Signal Timing G1 G2 Primary Gate Drive Overlapping First, overlapping drive is considered to avoid breaking current source path Two primary windings are shorted during the period of overlapping and a current gap occurs Spike across the drain source is caused by the energy stored in leakage inductor Primary Gate Drive Non-Overlapping Non-overlapping avoids shorting the primary winding Spike on drain is caused by the current transient Current gap occurs during this period as the two primary FETs are off Non-overlapping gate drive is used. Adjusting dead time optimizes the current gap Device capacitance is sufficient to provide current continuity during commutation

15 Push Pull Converter Drive Signal Timing (cont) Reverse Recovery of Synch Rect. for non-overlapping Simulation waveform under 100mOhm Load. 100nS primary deadtime, 150nS leading SR delay. 60nS SR trailing edge delay. Note reverse recover current during SR off time The spike due to reverse recover current depends on the parasitic inductance of trace on PCB

16 Switched Current Converter 1m I1 irf 6601_1 Q1 irf 6601_1 4.7u C1 Vo Q2 10 R2 D3 IDEAL 10 R3 OUT ARB1 N1 D2 IDEAL OUT ARB2 N1 U1 max962 VSp Qout_p VINp Qout_n VINn VSn Gnd Vref 1 Vcc Output Capacitance is necessary but smaller Voltage feedback Current supplied to the load is determined by voltage drop on the capacitor Delay of control loop requires a larger capacitance ESR and ESL of Output Capacitance is critical to the step control Gate drive timing stops current to load before short current to ground

17 Switched Current Converter(cont) Simulation on dynamic load = 400A/us Simulation condition: Load current is changed from 5A to 95A (blue) Load current slew rate = 400A/us Simulation result: Load voltage is varied from 1.022V to 0.975V (light green) The red line Ic is the current waveform before output capacitance The light green line is the buck output current waveform

18 Switched Current Converter(cont) Simulation on dynamic load = 1000A/us Simulation condition: Load current is changed from 5A to 95A (blue) Load current slew rate = 1000A/us Simulation result: Load voltage is varied from 1.022V to 0.975V (light green)

19 Switched Current Converter(cont) Simulation on dynamic load = 2000A/us Simulation condition: Load current is changed from 5A to 95A (blue) Load current slew rate = 2000A/us Simulation result: Load voltage is varied from 1.022V to 0.975V (light green) The Slew Rate has no obvious effect on the Output Voltage Deviation

20 Switched Current Converter(cont) Modeling The Interconnect: All the previous simulations include the parasitics associated with the a representative system interconnect The simulations do not include PCB parasitics and depend on component simulation accuracy 100p 40u VRM current output 180u C1 300u R3 L1 R5 560u C5 300u R6 Future Processor Model VRM output cap inter-connection decoupling capacitors

21 System Measurements Actual results Load changed from 0-50%, 5 phases switching Early results indicate that the 927A/uS can be achieved on rise time Optimisation continues..

22 System Power Budget Buck Converter full load 100A 1V light load 10A 1V item components power losses(w) power losses(w) output choke EE Mosfet High side IRF Mosfet low side IRF sense Resistance 0.01OHM 1 1 Driver IC ISL total power losses output power Efficiency 96.70% 86.04% Push Pull and Switch Current Total RCD transformer Martrix PP Mosfet STP75NF SYN Mosfet IRF Switch current Mosfe IRF total power losses power loss load power total input power Efficiency 84.27% 37.16% System Power Budget indicates that the overall efficiency ~ 84% ~2-3% Lower than a conventional VRM due to the 3-Stage Topology

23 System Assembly 6 layer PCB 75mm X 25 mm Assembly height 13.6mm Matrix transformer divided between the top and bottom sides Rectifier FETs close to Matrix Transformer

24 Summary and Conclusions: This paper introduces the concepts of switched current conversion as a possible alternative to common industry approaches to Fast transient requirements The converter consists of 3 Stages: Buck Current source, Push Pull converter employing a matrix transformer and the switched current output Simulation results indicate that the topology can meet very fast transient requirements limited only by parasitics and sensing delays Reduces overall system capacitance Transient response could be further enhanced by moving the switched current section to the load application Silicon integration to reduce complexity and component count Advent of flexible Digital control systems to reduce the number of phases, reduce complexity and improve efficiency

25 Reference Material 1) Edward Herbert, Switched-current Power Converter, ) Edward Herbert, Voltage Control for Switched-current Power Converter, 3) Edward Herbert, Fast Transition Power Control for Processors Using Switched Current and Switched Charge 4) Edward Herbert, Input Characteristics and Waveforms for Switched-Current Power Converters