Deliverable 2.3 Analysis and optimisation of selected architectures

Transcription

1 PowerSWIPE (Project no ) POWER SoC With Integrated PassivEs Deliverable 2.3 Analysis and optimisation of selected architectures Dissemination level: PU Responsible Beneficiary Universidad Politécnica de Madrid Due Date 31 st March 214 Submission Date 3 th April 214 FP7-ICT Collaborative Project (STREP) PowerSWIPE (Grant agreement ) Objective ICT Very advanced nanoelectronic components: design, engineering, technology and manufacturability

2 Summary No and name D2.3 Analysis and optimisation of selected architectures 1 Status Due April 31 st 214 Date April 11 th 214 Author(s) Vladimir Svikovic, Jorge Cortes, Florian Neveu, Gerhard Maderbacher, Joachim.Pichler Editor Jesus A. Oliver DoW Report on Detailed analysis and optimisation of individual blocks of the selected architectures Dissemination PU Level Nature Report Document history V Date Author Description Draft 11th-April-214 J.O Draft Final 2 th April 214 J.O Final Version 1 Disclaimer - The information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability. 2/23

3 Table of Contents 1. Introduction Low Voltage DC-DC Converter System (LVDC-DC) Low-frequency LVDC-DC System design Static behaviour Dynamic behaviour High-frequency LVDC-DC Switch Capacitor High Voltage DC-DC Converter System (HVDC-DC) Conclusions References /23

4 4/23

5 1. Introduction This document provides detailed the optimization results and the analysis of the selected architectures. The optimization and analysis are based on the CAD analysis and optimization tool described in D2.1 developed within this project. The analysis and optimization tool is continuously updated along the project to both increase its accuracy and improve the models and optimization algorithms. The complete PowerSwipe System Level Architecture is shown in Figure 1, this document will cover the individual optimization results of all the converters selected for this architecture: The HV DC-DC converter that reduces the battery input voltage that can vary from 16V to 6V to an output voltage of either 5V or 3.3V. The PMIC will be implemented in BCD-CMOS technology. The LV DC-DC converter will supply the µcontroller Core (1.2V) from the intermediate voltage generated by the HV DC-DC. The SC DC-DC converter will generate a controllable output voltage of 1.3V from the intermediate input voltage (5V or 3.3V). The HF DC-DC converter will scale down an intermediate voltage of 3.3V to 1.2V using high switching frequency techniques (1MHz-2MHz). The system level specification were generated by INFINEON and BOSCH in cooperation with all the partners in a previous deliverable D1.1. The results of this document are the consequence of a tight cooperation among all the partners. In this document the design results for all the converters to be developed within this project will be described with the expected results. μc PMIC IFAT System IC IFAT 16V-6V CHVin HV DC-DC L1 CHVout VINT= 5V-3.3V CLVin LV DC-DC SC DC-DC Dummy Load 1 L2 CLVout Vcore=1.2V 4nm Flash CMOS 13nm BCD-CMOS HF DC-DC Ampere C3out Load 2 Vdd2=1.2V 4nm Flash CMOS Figure 1 PowerSwipe System Level Architecture 5/23

6 2. Low Voltage DC-DC Converter System (LVDC-DC) In this section design details regarding Low voltage converter system (LVDC-DC) are presented. The first part is dedicated to the low-frequency LVDC-DC, followed by the High-frequency LVDC- DC. Finally, the Switched-Capacitor converter is presented. 2.1 Low-frequency LVDC-DC The low-frequency LVDC-DC converter, presented in Fig. 1, is implemented as a single phase synchronous buck converter with peak current mode control (PCMC). The design details, presented in this chapter are obtained using CAD tool developed within this project and presented in D2.1. PCMC REGULATION S 1 C IN S 2 L i L C OUT + v OUT - Figure 2 Low Voltage Low-frequency DC-DC converter System design The system, optimized using the CAD tool, is composed of the 27 nh output inductor, 2 nf output capacitor and 3 nf input capacitor while switching at 12 MHz. LVDC-DC is converting 5 V to 1.2 V. As mentioned, the PCMC control of the converter is employed and the system is operating in continuous conduction mode (CCM), while discontinuous conduction mode (DCM), frequency modulation (FM) or Burst mode can be used for light load operation. In this sub-chapter, the implementation details of all components are presented. A. Inductor design The output inductor has been optimized by the CAD tool D2.2, while its design is validated using Finite element analysis (FEA) tool. The inductance of the output filter inductor is 27 nh. The geometry parameters as well as electrical are presented in Table I, while the geometry of the inductor is shown in Fig. 2. 6/23

7 Figure 3 The inductor geometry: 3D view (left), footprint (right) Table I- Output Inductor geometry and electrical parameters Geometry Parameters Name Value Total area A T 3.2 mm 2 Number of turns N 4 Core thickness T core 5.15 μm Core width W core μm Core height H core 75.3 μm Core length L core μm Copper width W cu μm Copper thickness T cu 35 µm Vertical spacing H air 15 µm Horizontal spacing W air 2 µm Distance between cores D core.35 mm Electrical Parameters L (analytical) L (FEA tool) B. Capacitor design Value 27 nh 268 nh The output and input capacitors are designed using cell based approach presented in D2.1. A targeted value of the capacitance is obtained by combining basic cells (12 nf, 3.6 nf and 1.6 nf). The optimal values and implementation of both the input and output capacitor are presented in Table II. 7/23

8 Table II- Input and output capacitor parameters Cap ESR N12n N3n6 N1n6 area C IN 3 nf 17.5 mω mm 2 C OUT 2 nf 11.7 mω mm 2 C. Semiconductor design Semiconductors design details are presented in Table III, where it can be seen that optimal widths for PMOS and NMOS are 12 mm and 14 mm, respectively, while using minimal length of the channels for rated input voltage of 65 nm for PMOS and 56 nm for NMOS. The driving voltages for both MOSFETs are 5 V, defining on-resistances of 46.7 and 98.5 mω for PMOS and NMOS respectively. As it can be noted, the on-resistance of the PMOS is around 4 times bigger than the NMOS, which is consistent with big conversion ratio (duty cycle is 24%), balancing conduction losses between the switches. Table III - Semiconductors parameters Width Length R ON V GS I Drive PMOS 12 mm 65 nm 46.7 mω 5 V 8 ma NMOS 14 mm 56 nm 98.5 mω 5 V 8 ma Static behaviour Proposed optimal design has been tested in order to validate that the specification has been met. In order to obtain more realistic results, additional parasitic impedances are added to the passives, degrading the performance. The added impedances are representing interconnections and through-silicon via parasitics and they are modelled as series resistance of 1 mω and series inductance of 1 ph (values taken from IPDIA parasitic extraction). System variables waveforms for typical load operation (I OUT = 28 ma) are presented in Fig. 3 where it can be seen that both input and output voltage deviations are inside the specified range: the maximal output voltage peak-to-peak ripple is 2 mv and the input voltage peak-to-peak ripple is 26 mv, while the specification is imposing 6 mv and 25 mv respectively for the output and input voltage peak-to-peak ripple. The inductor current peak-to-peak ripple is ma. Operating under maximal load operation (I OUT = 5 ma) the maximal output voltage peak-to-peak ripple is 21 mv and the input voltage peak-to-peak ripple is 54 mv, while the inductor current peak-to-peak ripple is ma. 8/23

9 1 Duty v OUT [mv] i L [ma] 2 1 i Cout [ma] i Pmos [ma] v Cin [mv] i Nmos [ma] 4 2 i Cin [ma] t [ns] t [ns] Figure 4 Waveforms of the state variables at typical load (28 ma) Optimum efficiency results and total power losses are shown in Table IV. Additionally, in 9/23

10 Table V the absolute and relative breakdown of the losses are presented for typical load current. The system has been optimized for operation at the typical load, thus it can be seen that the losses for that case (Fig. 4) are balanced between the passives (62%) and the semiconductors (38%), while achieving efficiency of %. Table IV Total losses and expected efficiency at typical load (28 ma) f SW MHz Efficiency 75.52% P Total mw 1/23

11 Semiconductor losses: NMOS Losses PMOS Losses Capacitor Losses Passive losses Inductor Losses Table V Losses Breakdown at typical Load current at ypical load (28 ma) P LoutCuDC mw (23.12%) P LoutCuAC 4.83 mw (4.44%) P LoutFeHyst 8.9 mw (8.17%) P LoutFeEddy mw (21.23%) P LTotalCu 3.1 mw (27.56%) P LTotalFe 32.2 mw (29.4%) P Lpar.86 mw (.79%) P LTotal 62.3 mw (56.96%) C OUTESR.12 mw (.11%) C OUTpar.7 mw (.6%) C INESR.21 mw (.19%) C INpar.18 mw (.16%) P PMOScond mw (1.53%) P PMOSturn-on 1.13 mw (1.4%) P PMOSturn-off 5.23 mw (4.8%) P PMOSgate-drive 6.49 mw (5.95%) P NMOScond 7.22 mw (6.63%) P NMOSrev-rec 2.48 mw (2.27%) P NMOSgate-drive 6.93 mw (6.36%) P DT:PMOS NMOS 3.6 mw (3.31%) P DT:NMOS PMOS.91 mw (.84%) Dynamic behaviour The optimal design, as mentioned, is controlled using PCMC. Desired inductor current reference is defined by the linear regulator whose amplitude and phase characteristic are shown in Fig. 7a, achieving the closed loop bandwidth (BW) of the system of 1.71 MHz. Open-loop transfer function is presented in Fig. 7b, where it can be seen that the phase margin is 6, while the gain phase is 8.53 db. Comparisons between open-loop and closed-loop transfer functions are presented in Fig. 8. The input voltage to output voltage transfer function comparison is presented in Fig. 8a. Since PCMC control is employed, high rejection has been obtained having the maximum of -66 db at the cross-over frequency, while improving low frequency behaviour. Furthermore, in Fig. 8b the output impedance comparison is presented. The maximal value of the closed-loop output impedance is -6 db at the cross-over frequency, while the DC impedance of the open-loop of system of 2 db is cancelled. Finally, the output voltage reference to output voltage transfer function is presented in Fig. 8c where it can be seen that the amplitude characteristic has unity gain up to the BW frequency, while -3 db pass- band frequency is at 4 MHz. 11/23

12 Regulator and and Loop Transfer Functiones Gviref2vout OL OL [db] [db] R(jw) R(jw) [db] [db] L(jw) L(jw) [db] [db] ang(gviref2vout OL ) OL [deg] ) [deg] ang(r(jw)) [deg] [deg] a) b) PM(L(jw)) [deg] [deg] Figure 5 Regulator transfer function (a) and open-loop gain (b) Input Input Voltage to to to Output Output voltage voltage (left), (left), Output Output Impedance (center) (center) and and Reference to to Output to Output Voltage(right) OL OL OL CL CL CL OL OL OL CL CL CL CL CL CL OL OL OL CL CL CL OL OL OL CL CL CL a) b) c) CL CL CL Figure 6 Closed-loop transfer functions (blue) Vs. Open-loop transfer functions (green): a) Input voltage to output voltage, b) output impedance and c) Output voltage reference to output voltage The system behaviour has been validated in time domain as well. The system has been tested under specified load steps of 5 ma with settling time of 2 ns and load step of 3 ma with 2 μs settling time. The simulations are presented in Fig.9 and Fig. 1, respectively. In the case of the first load step, the maximal deviation of the output voltage, considering the voltage ripple, is 32 mv which is far below the specified value of 12 mv, presented in dashed black lines. In the second case, due to the big settling time of the load step and big BW of the system, the output voltage deviation is only 15 mv although the amplitude of the step is 6% of the maximal output current. 12/23

13 28 27 I OUT [ma] i L [ma] i REF [ma] i REF -ramp [ma] v OUT [mv] t [ns] Figure 7 Load-step waveforms: ΔI OUT = 5 ma, 2 ns 13/23

14 4 35 I OUT [ma] x i L [ma] i REF [ma] i REF -ramp [ma] x v OUT [mv] t [ns] x High-frequency LVDC-DC Figure 8 Load-step waveforms: ΔI OUT = 3 ma, 2 μs For the high frequency converter (1 2 MHz), the main effort has been first focused on the power stage. Two main configurations were intensively investigated: the standard power stage and the cascoded power stage, depicted in the figures below. 14/23

15 Figure 9 Standard power stage Figure 1 Cascoded power stage The standard power stage uses only 3.3 V devices. It consists of 2 power transistors, referred as the HS (High Side) and LS (Low Side) power transistors. The HS transistor is a PMOS, driven by tapered buffers. The LS transistor is a NMOS, also driven by tapered buffers. The optimization of this power stage was made by varying the sizes of the HS and LS transistors, and the drive strength of each buffer rail. The cascoded power stage, on the other hand, uses only 1.2 V devices. It consists of 3 PMOS transistors, acting as the HS transistor of the standard power stage. Three NMOS transistors act as the LS transistor of the standard power stage. To enable these transistors to work together, it is necessary to add other transistors to keep the right polarization on each power transistor. This power stage is driven by 3 buffers rails, switching 1.1 V each, with shifted DC bias: the low rail is switching from V to 1.1 V, the middle rail is switching from 1.1 V to 2.2 V and the high rail from 2.2 V to 3.3 V. During the optimization, all the sizes of the MOSFETs were allowed to vary independently, except for the 3 power PMOS that had the same size, and the 3 power NMOS also had the same size. A primary optimization was carried out for various configurations (1 and 2 MHz switching frequency, and 336 and 168 mw output power), using an ideal input voltage source and an ideal output current sink. The efficiency of the power and its first-stage driver was evaluated (these 2 elements are the biggest contributors to losses). The table below summarizes the optimization results. Table VI --Efficiency evaluation of power stages in various configurations 15/23

16 These results show that each power stage gives better efficiency when working at 1 MHz and 168 mw. For a nominal power of 336 mw, this will be the configuration of a 2-phase converter. For the 2-phase converter, an optimization has been done on the output filter. This optimization assumed ideal power stages. L1 k L Lout Structure used of output inductors optimization Case 1: No coupling and no output inductor Optimization results: - k =, L OUT = nh, L PH = 45.5 nh - Phase current ripple: 172 ma - Ripple reduction vs. previous case: % Case 2: Coupling and no output inductor. Optimization results: - k =.4, L OUT = nh, L PH = 45.5 nh - Phase current ripple: ma - Ripple reduction vs. uncoupled: 12 % Case 3: coupling and output inductor. Optimization results: - k = 1, L OUT = 21 nh, L PH = 35 nh - Phase current ripple: ma - Ripple reduction vs. uncoupled: 28 % The results of this optimization show that having tightly coupled inductors on each phase and an output inductor gives the smallest phase current ripple, thus the smallest switching and conduction losses on the power stage. 16/23

17 These 2 optimization results are leading to the fully optimized but still quite ideal system that will have 2 interleaved and cascoded phases, and a coupled output filter, as depicted in the figure below. 2.3 Switch Capacitor Figure 11 Full architecture of DC-DC converter The switch capacitor converter will be integrated with the LV DC-DC converter. The target specifications for this converter are summarized in Table VII. Input voltage can be either 3.3V or 5V with a +/- 1% variation. Table VII Target Specification for the SC Converter To fulfill these requirement a 4 stage SC capacitor topology is selected as a trade-off between capacitance reduction due to interleaving and complexity (see Figure 12). Due to the 4 phases interleaved configuration in which all the phases are driven with the same pattern, but phaseshifted 9º among them, it is possible to reduce the capacitance required for the same output voltage ripple or, in this case, to reduce the switching frequency to boost the efficiency. 17/23

18 Figure 12 Top level diagram of the four phases Swithed Capacitor Converter The topology selected for each phase of the SC converter is a Series-Parallel configuration (see Figure 13) with two Gain modes: 1/2 ( Vin = 3.3V ) 1/3 ( Vin = 5V ) The switches will be implemented in C4FLA (Technology) as the LV DC-DC converters, operating at a switching frequency of 5 MHz. The nominal switch resistance is 2 Ohms. The external components (capacitors) are integrated on separate dies, and the values selected for them are: C fly = 3nF C in = 665nF C cout = 26nF Flying (Powertrain) Capacitor shared with the LV DC-DC given by the Interposer area 18/23

19 Efficacy [%] Figure 13 Topology of each phase of the Switched Capacitor Converter The regulation of the output voltage is achieved by means of Pulse Frequency modulation (PFM). The Efficiency of the converter has been estimated by means of accurate CADENCE simulations in which both Semiconductor models of the technology (C4FLA) and SPICE model of the integrated trench capacitors developed by IPDIA has been implemented. The implemented converter efficiency vs. ILoad simulation results are shown in Figure 14 for the two nominal input voltages (5V and 3.3V). Expected efficiency is over 75% for both input voltages and from 5mA to 25mA Vin = 5V Vin = 3.3V Target ILoad [ma] Figure 14 Switched Capacitor Converter efficiency vs load for input voltage of 5V and 3.3V 19/23

20 3. High Voltage DC-DC Converter System (HVDC-DC) The Powerswipe HV DC-DC is an inductor-based step-down converter that is part of a multi-die system on chip. The architecture of the proposed solution is shown in Figure 15. The design allows using both integrated inductors in a separate die and a small SMD inductor soldered also in a separate die. The main specifications for this supply are: Vin = 6V to 16V Vout = 3.3V, 5V Iload up to 5mA Switching frequency = 1MHz Figure 15 HV DC-DC Converter High Level description The passive components (inductance and capacitors) to be integrated on separate dies are selected to be: Output filter inductor L = 1μH Input Capacitor C in = 2nF Output capacitor C out = 1μF Driver capacitors: o C LS = 4nF capacitor for low-side driver supply o C HS = 2nF bootstrap capacitor for high-side driver 2/23

21 Regarding the semiconductors, both power switches are 2V NMOS devices (isolated drain) with SPT9U Technology. The supply for the low-side switch driver is generated by an LDO that is supplied from the buck-regulator output voltage (for higher efficiency).the output capacitor is pre-charged to 3V before switching is started. The high-side switch driver is powered off a bootstrap capacitor. POWER SWITCH DIMENSIONING Low-side switch type = 2V NMOS (isolated drain) nominal RON = 36mΩ High-side switch type = 2V NMOS (isolated drain) nominal RON = 48mΩ Note: the dimensions were derived starting from an initial concept target of 25mohm for the low-side and 5mohm for the high-side and subsequently optimized for best efficiency (compromise between conduction losses and capacitive losses). Simulation models are still preliminary and cause convergence problems for higher currents (however R ON and parasitic caps should match silicon quite well) The expected efficiency with the following operating paramenters ( Vin=12V, ESR L =5mΩ, ESR COUT =5mΩ, ESR CHS =1mΩ, ESR CLS =5mΩ) is shown in Figure ILOAD [ma] Efficiency - Vout=5V Efficiency - Vout=3.3V Figure 16 HV DC-DC Converter efficiency vs load for two different output voltages (Vout =5V and Vout=3.3V) 21/23

22 4. Conclusions This deliverable shows the detail analysis and optimization results for all of the converters that will be developed within this project. These are the results of a tight cooperation between all the partners that have provided all their knowledge about their technologies. This knowledge has been combined into an optimization tool that is able to perform extensive analysis to achieve the optimum design that complies all the requirements. The summary of the results obtained for the converter designed is: HV DC-DC converter, that converts the battery voltage, variable between 6V and 16V, to an intermediate voltage of 5 V. This converter uses a buck type dc-dc converter to perform the conversion and will operate at 1MHz. The expected efficiency for this converter is around 85% at 4mA LV DC-DC converter. This converter uses a buck converter with C4FLA Semiconductor Technology (with 5V devices) switching at 12 MHz, an integrated inductor and integrated capacitors to reduce the intermediate voltage provided by the HV DC-DC converter down to 1.2V. The size of the integrated inductor is 3.2mm 2 and the available area for the input capacitor and output capacitor is 1.4x1.9 mm 2 and 1.6x1. mm 2 respectively. The expected overall efficiency is 75% at typical load (28mA) SC DC-DC converter. This converter uses Switched Capacitor technology to supply 1.2V and 2mA from the intermediate voltage of either 5V or 3.3V. The converter consist on 4 switched capacitor cells (using 5V devices) operating in parallel and interleaved (phase shift of 9º among the phases) to reduce the requirement of capacitance. The expected efficiency is over 75% for all the operating load (5mA to 2mA) HF DC-DC converter. This converter reduces an intermediate voltage of 3.3V down to 1.2V but operating at 1MHz-2MHz. To achieve high efficiency, this converter uses a cascoded power stage based on 1.2 V devices. It consists of 3 PMOS transistors, acting as the HS transistor of the standard power stage. Three NMOS transistors act as the LS transistor of the standard power stage. The expected efficiency for this converter (not accounting for inductor losses) is 92% operating at 1MHz and 88% working at 2MHz. 22/23

23 5. References [1] D2.1: Architecture Analysis and Evaluation [2] D2.2: Analysis and optimization of the integrated Passives 23/23