AND8291/D. >85% Efficient 12 to 5 VDC Buck Converter

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>5% Efficient to 5 VDC Buck Converter Prepared by: DENNIS SOLLEY ON Semiconductor General Description This application note describes how the NCP363 can be configured as a buck controller to drive an

1 >5% Efficient to 5 VDC Buck Converter Prepared by: DENNIS SOLLEY ON Semiconductor General Description This application note describes how the NCP363 can be configured as a buck controller to drive an external PFET transistor to produce a cost effective, high efficiency 3 A switching regulator. The NCP363 has a wide input voltage range up to V which makes it attractive for industrial and consumer applications such as LCD-TVs. The design example illustrates a buck converter delivering 3 A at 5 or 3.3 V from a V supply. The block diagram of the NCP363 controller is shown in Figure. This switching regulator is based on a very flexible gated oscillator or bust mode architecture that can be used to create step-down (buck), step-up (boost) and buck-boost voltage regulators. The NCP363 contains an internal switch capable of up to.5 A but in applications requiring higher current, this device can be configured as a controller driving an external MOSFET. NCP363 NC TSD Switch Collector SET Dominant R I pk Sense +V CC 7 6 Comparator V S R S Q Q SET Dominant Oscillator CT 3 Switch Emitter Timing Capacitor Inverting Input 5 Comparator V Reference Regulator GND Figure. Block Diagram of the NCP363 Semiconductor Components Industries, LLC, 7 September, 7 - Rev. Publication Order Number: AND9/D

2 Typical operating waveforms, including the timing ramp C T, are illustrated in Figure. Feedback Comparator Output I PK Comparator Output Timing Capacitor, C T Output Switch On Off Nominal Output Voltage Level Output Voltage Startup Figure. Typical Operating Waveforms Operation For detailed information regarding controller operation refer to the NCP363 data sheet. The essentials of the control method can be observed in the waveforms of Figure. The output voltage is fed back to the inverting input 5 of the comparator (Figure ) via a resistor divider. If the output is below the set point, the comparator gates a series of clock cycles through the power switch. Control of the output voltage is achieved by varying the average number of on cycles to the number of off cycles in a given time interval. The transfer function (or gain) V OUT/ V IN for a conventional buck converter, neglecting circuit losses, is given by the following equation: Buck Transfer Function D (eq. ) If the value for D MAX (.6) set by the NCP363 is inserted into the above equation, the maximum gain is determined. Maximum Available Gain.6 (eq. ) This maximum gain value may be considerably more than a particular application requires. For example, a typical V to 5 V buck application requires a gain of. and a corresponding D =.. Consequently the gated oscillator operates at a small effective duty cycle, delivering power to the load for a few switching cycles before turning off for extended periods. The burst mode frequency is low causing the converter's output ripple to be high. The design may be optimized as follows. The NCP363 oscillator section consists of two current sources; one charging, the other discharging the timing capacitor C T, between two fixed voltage levels (Figure 3). The levels are approximately 5 mv apart. The ratio between the charge current and the discharge current is set within the controller to be :6. This ratio creates a fixed duty cycle D MAX of 6/7 or.6. The ramp circuit is modified (also illustrated in Figure 3) by adding of an external current source I FF to I CHARGE at the C T pin. This current source, in the simplest case, is created by adding a feedforward resistor between V IN and C T. (Additional information is available in the application note AND.) V IN I FF C T I CC I CHARGE I DISCHARGE Figure 3. Current Sources Charging and Discharging the Timing Capacitor C T Adding an external current will reduce the time it takes to charge the C T capacitor between the ramps's minimum and maximum thresholds. The design equations relating to the oscillator section are given below. T ON C T V RAMP I CHARGE (eq. 3) T OFF C T V RAMP I DISCHARGE (eq. ) T S (T ON T OFF ) (eq. 5)

3 D MOD T ON T S (eq. 6) F S T S (eq. 7) Table shows the corresponding reduction in duty cycle D MOD as a normalized function of the charging and discharging currents flowing into the timing capacitor C T. The table also shows the change in normalized oscillator frequency. Once an optimum duty cycle has been identified and I FF selected, the value of C T can be ratio metrically increased to reset the design frequency. This done, the converter's design frequency remains constant over a wide range of operating conditions. Table. Variation of Duty Cycle External Charging Current Internal Charging Current Internal Discharging Current Duty Cycle D MOD Frequency F MOD Variation of duty cycle D MOD and frequency F MOD as a function of normalized external current, charging the timing capacitor C T. Practical Example Figure is a schematic of the buck converter. The input is a nominal V while the output is regulated to 5 V. The NCP363 is used as the imbedded controller driving an external PFET switch. V IN = V R NTMS5PR Q L H V OUT = 5 V R 3.76 k.5 R k Q D3 MBRD3 C F / 6V3 C F / 6V3 MMBT39TTG C F / 5 V C F / 5 V U NCP NC I SENS V CC CMPINV SWC SWE CT GND D D 3 MMSD9TG MMSZ5V6T RTN R5. k C3 R6. F / 5 V 5 k C 3.9 nf RTN Figure. Schematic of Buck Topology The selection of the timing capacitor C T (C) and feedforward resistor R6 is discussed next. Assuming no circuit losses, the transfer function or gain of this application is. and is also.. Referring to Table, a 3: ratio for the external charging current to internal charging current would generate a modified duty D MOD of.5. This is a good starting point. The nominal charge and discharge currents for the NCP363 are listed below: - charging current is 6 5 V V CC / 5 C and V V CC / 5 C. - discharging current is 55 5V V CC / 5 C and 7 V V CC / 5 C. Assume we chose to operate at a switching frequency of approximately khz. Then T S is 5 S and T ON is.5 S giving the required modified duty cycle D MOD of.5. Rearranging Equation 3, a value for the timing capacitor CT is obtained: 3

4 C T I CHARGE T ON V RAMP (eq. ) Substituting values of I CHARGE of x 6 A and ΔV RAMP of.6 V into Equation, gives a nominal value of C T as.3 nf. The nearest standard value for C T is 3.9 nf. The value of R6 is selected as follows. Assume the average amplitude of the ramp waveform is.9 V. We require an external charging current I FF of 3 x 6 A, hence R6 equals ( V -.9 V) / 7 A or. k. The nominal value selected for R6 was 5 k Figure 5. Ramp Waveform C T = 39 pf, T S =. S With the values selected the observed ramp was captured in Figure 5. The measured values are given below. T ON =. S T S =. S F S = 5 khz ΔV RAMP =.5 V ΔV AVG =.9 V D MOD =. /. =.3. The experimental duty cycle is close to our actual design requirement of D MOD =.. Selection of External Transistor Q Given the design requirements for a V input and 3 A output buck converter running with low ripple current in continuous conduction mode, the maximum switch current and voltage ratings of the MOSFET must be considered. A V, 5 A, 6 m PFET such as the NTMS5P meets our criteria with margin for de-rating. For a smaller package footprint, the NTHS5TG PFET could also be an option, depending on output current and thermal considerations. The R DS(on) and total gate charge Q g curves for ON Semiconductor's NTMS5PR P channel MOSFET are shown in Figures 6 and 7. R DS(on), DRAIN-TO-SOURCE RESISTANCE ( ) T J = 5 C V GS = -.5 V V GS = -.7 V V GS = -.5 V 6 -I D, DRAIN CURRENT (A) -V GS, GATE-TO-SOURCE VOLTAGE (V) 5 3 Q -V DS Q QT 6 Q g, TOTAL GATE CHARGE (nc) -V GS I D = -5. A T J = 5 C 6 -V DS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 6. R DS(on) vs. Drain Current I D NTMS5PR Figure 7. Q g vs. V GS NTMS5PR

5 The conduction loss P Q is given by Equation 9. P Q I OUT R DS(on) D MOD (eq. 9) P Q = 3 * 6 m *.3 = mw A 5.6 V zener diode D (Figure ) is used to drop the gate drive voltage V GS below V IN The gate power P G required to switch the FET channel on and off is given by: P G Q G V G F S (eq. ) For V GS =.5 V, the gate charge Q G (from Figure 6) is nc P G = nc *.5 V * khz = mw The gate drive waveform is captured in Figure. The network consisting of a small signal NPN transistor Q, D and R, illustrated in the schematic (Figure ) provides a fast turn off for the PFET Q. The turn on/off behavior of the external PFET Q is determined as follows. When the internal switch within the NCP363 turns on, the gate charge for Q is provided by current flowing from V IN via D and D to ground return. The positive voltage across D creates a reverse bias condition across Q's base emitter junction. Q remains in the off state until the internal switch in the NCP363 is itself turned off. At this time, current flowing through resistor R is diverted to provide Q base current. Q conducts until Q's gate charge is neutralized. Figure. High Side Gate Drive for PFET Q with Clock Ramp Selection of Output Inductor L The value selected for L determines the AC ripple current in the inductor as well as the output current boundary between discontinuous conduction mode (DCM) and continuous conduction mode (CCM) operation. The ripple current ΔI L flowing in the output inductor I L is calculated from the standard flux equation I L (V IN V OUT ) D MOD T S L (eq. ) Since CCM was selected to keep the peak current to a minimum, a peak ripple of % of the output current (3 A) is our design criteria, requiring ΔI L to be.6 A. Also (V IN - V OUT ) = 7 V, D MOD =.3 and T S = 5 S, so L may be determined by substitution into equation. The required output inductor value is 5 H. A H inductor would meet our design objective and is commercially available from several vendors. For example, part number SLF575T-MR is a H inductor from TDK with a winding resistance R W of 6 m and rated DC current of A. The winding loss P L in the output inductor is given by the equation, P L I OUT R W (eq. ) P L = 3 A * 6 m = 3 mw By employing the feedforward technique, the maximum flux (V S) the component sees has been reduced. Being 5

6 able to selecting a lower value for L reduces the winding resistance R W, improving converter efficiency. Selection of Freewheel Diode D Figure 9 shows the forward drop of the MBRD3 series of SWITCHMODE power rectifiers in a DPAK surface mount package. I F, INSTANTANEOUS FORWARD CURRENT (A).. 5 C..3 5 C. 75 C.5.6 T J = 5 C V F, INSTANTANEOUS VOLTAGE (V) Figure 9. Forward Drop of MBRD3 As can be seen from Figure 9, the typical forward drop V FWD at 3. A is. V at 75 C. The conduction loss P FWD for the free wheel diode is given by the equation:. P D I OUT V D ( D MOD ) (eq. 3) P FWD = 3. A *. V *.3 =.5 W Selection of Input and Output Capacitors The input and output voltage peak to peak ripple across C and C are given by the equations below: V C I L D MOD T S C (eq. ) Small value MLCC capacitors in 5 and 6 SMD packages can be an alternative to electrolytic or tantalum capacitors. These MLCCs have extremely low ESR ( m ) and ESL ( nh) parasitic values and so individually or in parallel combinations can form the perfect lossless capacitor when used for filtering at mid to high switching frequencies. For example if C = C = F, ΔI L =.6 A and D MOD =.3, the peak to peak voltage ripple ΔV C across the input and output of the converter are 3 mv and 7 mv respectively. However as the NCP363 controls the output voltage by gating the oscillator on and off, additional electrolytic or tantalum capacitances C and C are required at the input and output to filter these lower frequencies. Current Limit The NCP363 has a peak current limit sense circuit, set by connecting a sense resistor R (Figure ) between pins 7 and of the controller. The reference voltage for the current limit function is nominally mv so selecting a 5 milliohm resistor for R allows the converter to operate above 3 A before current limit protection is activated. The power loss in the sense resistor is 3 * R or Ps = 5 mw. Bias Current The maximum bias current to power the NCP363 is 7 ma. Bias power P B is mw. Loss Budget Summing the theoretical losses for Q's conduction and gate drive, inductor winding, freewheel diode, current sense and bias power, we obtain a loss budget of mw + mw + 3 mw + 5 mw + 5 mw + mw or.57 W, neglecting hysteresis losses in the inductor and esr losses in the input and output capacitors. The converter's maximum theoretical efficiency is 5/6.57 or 9.5%. Experimental Results The efficiency of the buck converter at 5 V and 3.3 V output is shown in Figure. The 5. V output data is in good agreement with the calculated loss budget above. V C I L ( D MOD ) T S C (eq. 5) 6

7 BUCK CONVERTER EFFICIENCY 9 5. V EFFICIENCY (%) V OUTPUT CURRENT AMPS (A) Figure. Measured Efficiency Data The waveforms across freewheel diode D3 and ramp capacitor C are illustrated in Figure at the full load condition of 5 V and 3 A. By reducing the duty cycle to D MOD, the gated oscillator operates in a near continuous mode, providing drive pulses every clock cycle. Figure. Voltage across freewheel diode D3 and ramp capacitor C 7

8 Figure illustrates the output ripple, under the same test condition, together with the switch node (D3) for reference. Note the ripple frequency is 5 mv p/p and approximately one third of the converter's khz clock frequency. Figure. Output Ripple (C) referenced to switch node (D3) Conclusion By summing an external current source into the C T pin of the NCP363, it is possible to optimize the open loop gain of buck, boost or buck boost topologies for any given application. Reducing the controller's maximum duty cycle of.6 to a lower value D MOD allows the power components to be designed for lower stress. Input capacitors, output capacitors, inductor, switches and diodes can all benefit from the D MAX reduction. In the case of a V to 5 V buck converter, the selection criteria of each component is discussed and experimental data and waveforms presented. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 7 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative AND9/D

1. DEFINE THE SPECIFICATION 2. SELECT A TOPOLOGY

1. DEFINE THE SPECIFICATION 2. SELECT A TOPOLOGY How to Choose for Design This article is to present a way to choose a switching controller for design in the s Selector Guide SGD514/D from ON Semiconductor. (http://www.onsemi.com/pub/collateral/sgd514d.pdf)