Analysis and optimization with improved models

Transcription

1 PowerSWIPE (Project no ) POWER SoC With Integrated PassivEs D.5: Status Report Analysis and optimization with improved models Dissemination level: Responsible Beneficiary Centro de Electrónica Industrial, Universidad Politécnica de Madrid FP7-ICT-11-8 Collaborative Project (STREP) Objective ICT Very advanced nanoelectronic components: design, engineering, technology and manufacturability

2 Analysis and optimization with improved models, October 14 Summary Name Analysis and optimization with improved models Status Due Month 1 Date 1-October-13 Author(s) Editor(s) DoW Dissemination Level Nature Document history Vladimir Šviković, Jorge Cortes, Pedro Alou, Jesús Ángel Oliver (UPM) Gerhard Maderbacher, Christoph Sandner (INFINEON-Austria) Florian Neveu, Christian Martin, Bruno Allard (INSA-LYON) Jesús Ángel Oliver (UPM) Analysis and optimization with improved models: Report on Detailed analysis and optimization of individual blocks with improved models based on first prototype [month 4] PU Report V Date Author Description V V1 V 8-October November-14 -November-14 Vladimir Šviković, Cortés Jorge Florian Neveu, Christian Martin, Bruno Allard Gerhard Maderbacher, Christoph Sandner UPM contribution INSA Lyon contribution INFINEON contribution Final 6-November-14 Jesús A. Oliver Final Deliverable Page

3 Analysis and optimization with improved models, October 14 Content 1. Introduction Low-Frequency Low-Voltage DC-DC Converter System (LVDC-DC) Models Magnetics model Semiconductors model Capacitor model Low-frequency LVDC-DC System design Static behavior High-Frequency LVDC-DC Switch Capacitor converter SC DC-DC Converter High-Voltage DC-DC Converter System (HVDC-DC) Conclusions... 1 References... Page 3

4 Analysis and optimization with improved models, October Introduction This document provides detailed the optimization results and the analysis of the individual blocks with improved models. The optimization and analysis are based on the CAD analysis and optimization tool described in D.1 developed within this project. The analysis and optimization tool is continuously updated along the project to both increase its accuracy and improve the models and optimization algorithms. Fig. 1 PowerSwipe System Level Architecture The complete PowerSwipe System Level Architecture is shown in Fig. 1, this document will cover the individual optimization results of all the converters selected for this architecture: The HV DC-DC converter that reduces the battery input voltage that can vary from 16V to 6V to an output voltage of either 5V or 3.3V. The PMIC will be implemented in BCD-CMOS technology. The LV DC-DC converter will supply the µcontroller Core (1.V) from the intermediate voltage generated by the HV DC-DC. The SC DC-DC converter will generate a controllable output voltage of 1.3V from the intermediate input voltage (5V or 3.3V). The HF DC-DC converter will scale down an intermediate voltage of 3.3V to 1.V using high switching frequency techniques (1MHz-MHz). The system level specification was generated by INFINEON and BOSCH in cooperation with all the partners in a previous deliverable D1.1. The results of this document are the consequence of a tight cooperation among all the partners. In this document the design results for all the converters to be developed within this project will be described with the expected results.. Low-Frequency Low-Voltage DC-DC Converter System (LVDC-DC).1 Models In this subchapter modification of component models with respect to [] and [3] are presented. The component models are provided by manufactures of the components or derived based on the simulations provided by the manufactures and they are used for the estimation of the power losses. On the other hand, the models of the system are based on the literature and can be divided as the switching model, implemented as a hybrid state-space model [5], and average model, implemented as a liner state-space model based on [5] for VMC and [6] for PCMC. The converter models have not been modified with respect to [], Page 4

5 Analysis and optimization with improved models, October Magnetics model The magnetic components are designed using Tyndall National Institute [7] technology. The components are based on Magnetics on Silicon process which is used for fabrication of micro-inductor and micro-transformer structures. The process is currently employed to fabricate elongated spiral or racetrack device structures. The top view and the cross-section of the racetrack magnetic structure are shown in Fig.. Fig. Top view and cross-section of the Magnetic structure (ILD- Inter layer dielectric, IMD- Inter metal dielectric). The model of a basic inductor has been implemented in the CAD tool having in mind constrains of the technology and, for optimization in [], the inductor models had been implemented as a series impedance of an inductor and frequency dependent resistance, as shown in Fig. 3a. a) R (f) L v OUT b) R (f) R (f) L L v OUT R (f) L M L c) R (f) 1:1 L v OUT Fig. 3 The models of magnetic: a) basic inductor (L inductance, R (f) frequency dependant resistance), b) modified inductors for Twophase Buck converter (L inductance, R (f) frequency dependant resistances) and c) equivalent model of Coupled Two-Phase Buck inductors (L leakage inductance, L M magnetsing inductance, R (f) frequency dependant resistances). The frequency dependent resistance R (f) is composed of the DC component, R DC, which is dependent on desired inductance L, and AC components which represent the skin effect in the metal strips. For each frequency of interest, defined by the number of harmonic, the skin depth is calculated and based on DC resistance and the thickness of the metal strip h, AC resistances are calculated. In the improved model, which is currently used in the optimization, additional effects have been considered and included as following: A. Basic Inductor From the previous version of the models, presented in [3], both the inductance and the losses calculation have improved based on [8], where models developed by Tyndall are presented. New inductance calculation: before, the only considered inductance was the one obtained from the reluctance of the core. Now, the self-inductance of the winding part inside the core and the inductance contribution of the non-cored circular parts are added for improved accuracy. Page 5

6 Analysis and optimization with improved models, October 14 Core inductance: obtained from the general formula using the reluctance A 1 c core N N r (1) c lc L Where A c is the cross-sectional area of the core and l c is the magnetic path length Self-inductance: obtained assuming a straight wire with rectangular cross section lw, core L self, winding.lw, coreln. 5 () tw Where l W,core is total length of the winding that is inside the core and t W is half the external perimeter of the cross section of the winding. Noncored inductance: obtained assuming it is a single circular planar spiral inductor with outer and inner diamerers d o and d i. L noncored N d avg.46 ln. p p (3) Where d avg = (d o+d i)/ is the average diameter and p=(d o-d i)/(d o+d i) is the fill factor.. New losses calculation: before, the inductor losses calculation was very simple. Now, an accurate calculation of winding losses (DC and AC conduction losses) and core losses (due to hysteresis and induced eddy currents) have been added. Winding losses: The DC component of resistance is calculated using R DC lw (4) A Where ρ is resistivity of the winding material, l w is the total length of the winding and A w is the thickness of the winding. The AC components are calculated using R W ( nf ) F( nf ), (5) AC R DC where F(nf) is the ac resistance factor of the nth switching frequency harmonic. F(nf) is obtained using the Dowell s analysis assuming horizontal field direction in the winding window. Further, the power losses of the winding of the inductor can be calculated using P coppper R DC I Lmean Nharm n1 R AC In ( nf ), (6) where I Lmean is mean value of the inductor current, Nharm is the number of harmonics of interest and I n is the amplitude of n th component of the Fourier series if the inductor current. Core losses: The core losses due to hysteresis are determined with the empirical equation: Bpp Physteresis K f Volcore (7) where K and b are material-dependent parameters, ΔB pp is the peak-to-peak flux density and Vol core is the total volume of the core. The core losses due to induced eddy currents are determined by the proximity losses in a bus bar assuming that the core is composed by four bus bars of equal thickness: P eddy cs t Nharm c vn c n n b sinh( vn) sin( vn) H cosh( v ) cos( v ) n n (8) Page 6

7 Analysis and optimization with improved models, October 14 Where S c is the total external surface of the core, t c is the core thickness, v n is the core thickness to skin depth ratio at the nth switching frequency harmonic and H n is the magnetic field amplitude at the nth fsw harmonic. B. Inductors for two-phase multiphase buck: The inductance and losses calculations are exactly the same as for a single inductor. C. Coupled inductors for two-phase multiphase buck: A study on coupled inductors has been carried out. A structure with three cores has been proposed where the two cores will contribute to the leakage inductances and a central core will contribute to the magnetizing inductance. The same analytical calculations as in the case of a single inductor can be used to calculate the leakage inductances, L. On the other hand, new complex analytical calculations have been derived to calculate the magnetizing inductance, L m: L m =.l W,core [ln ( l W,core ) 1 + ( t W ) ( t W l W,core t W ) l W,core ln k] + N R (9) Additionally, Finite-Element-Analysis simulations have been carried out using 3D Maxwell in order to validate the equations: Fig. 4 Maxwell 3D simulation for coupled inductors. Yi+1,j+1 Yi+1,j+1 SOUT3 i,j IMAX YINT i,j SOUT i,j Yi,j+1 Yi,j+1 SOUT4 i,j y(w, I) SIN3 i,j SIN i,j Yi+1,j Yi+1,j Ij+1 Ij+1 IMIN SIN4 i,j wi+1 wi+1 wmin a) y(w, I) wmax b) Yi,j Ij wi SIN1 i,j c) I Ij wi SOUT1 i,j w Fig. 5 Basic modeling cell: a) Input plain defined by w[i] and I[j]; b) interpolation between four input points, input sub-domains, intermediate point Y INT i,j; and c) the output plains and calculation of y(w,i). The derived equations are being tested now. Preliminary results show very good agreement (Lm_analytical = 1.8nH, Lm_maxwell =.18nH and L_analytical = 41.3nH, L_maxwell = 43.47nH)..1. Semiconductors model The semiconductors used in LV-DCDC converter are implemented using Infineon MOSFET technology [9]. The model is presented in [1] and consists of nine functions, three static characteristics and five dynamic characteristics: 1. NMOS body diode voltage drop,. NMOS on-resistance, 3. PMOS on-resistance, 4. NMOS gate charge, 5. PMOS gate charge, Page 7

8 Analysis and optimization with improved models, October NMOS body diode reverse-recovery energy loss, 7. PMOS turn-off energy loss, 8. PMOS turn-on energy loss. The modeling functions based on discrete number of simulations performed by Cadence, where the input variables are MOSFET width w and current I. The modeling functions are obtained by interpolating the output variable using linear plains as presented in Fig. 5. After the measurements are obtained (Fig. 5a), for each four points are the intermediate point is defined (Fig. 5b) which is used to create output linear plains (Fig. 5c). In the case that a function is defined with three input variable (e.g. the on resistance), the third variable is declared as a parameter and interpolation is performed, once again, using the MOSFET width and the MOSFET current. i L I 1 TABLE I. Losses component CALCULATION OF SEMICONDUCTOR LOSSES Time Equation instance I P PMOS_Cond - R PMOS (w P, V GSP, I L) I PmosRMS P PMOS_turn_on, (T SW) E PMOSturn-on(w P, I ) f SW i PMOS I 1 P PMOS_turn_off DT SW E PMOSturn-off(w P, I 1) f SW P PMOS_gate, (T SW) Q PMOS(V GSP, w P, I ) V GSP f SW I P NMOS_Cond - R NMOS (w N, V GSN, I L ) I NmosRMS P NMOS_gate DT SW Q NMOS(V GSN, w N, I 1) V GSN f SW i NMOS I 1 P NMOS_rev_rec, (T SW) E Nrev-rec(w N, I ) f SW I P Ndiode_NP, (T SW) I V D-NMOS (w N, I ) f SW t dead_np P Ndiode_PN DT SW I 1 V D-NMOS (w N, I 1) f SW t dead_pn Fig. 6 Buck converter currents: inductor current i L (blue), PMOS current i PMOS (red) and NMOS current i NMOS (green). Obtaining all needed functions, power losses of semiconductors can be calculated based on the waveforms of the MOSFETs currents, shown in Fig. 6, using the equations presented in TABLE I., where w P and w N are widths of PMOS and NMOS, respectively; V GSP and V GSN are gate to source voltage of PMOS and NMOS, respectively; I L, I and I 1 are mean, minimal and maximal inductor currents, respectively; I Pmos_eff and I Nmos_eff are PMOS and NMOS RMS currents, respectively; f SW is converter switching frequency; T SW is converter switching period; D is duty-cycle; t dead_np and t dead_pn are dead-times at (T SW) and DT SW, respectively; R PMOS and R NMOS are onresistance calculation functions of PMOS and NMOS, respectively; Q PMOS and Q NMOS are one-switching gatecharge calculation functions of PMOS and NMOS, respectively; E PMOSturn-on and E PMOSturn-off are turn-on and turnof one-switching energy-loss calculation functions of PMOS; E Nrev-rec is body diodes reverse-recovery oneswitching energy-loss calculation function; V D-NMOS is NMOS body-diode voltage drop calculation function; P PMOS_Cond and P NMOS_Cond are PMOS and NMOS conduction power losses, respectively; P PMOS_gate and P NMOS_gate are PMOS and NMOS driving power losses, respectively; P PMOS_turn_on and P PMOS_turn_off are turn-on and turn-of losses of PMOS; P NMOS_rev_rec is NMOS body diode reverse-recovery power loss and P Ndiode_NP and P Ndiode_PN are dead-times losses at (T SW) and DT SW, respectively. Further, the validation of the model is presented. The model has been developed for an input voltage of 5 V, maximal driver current of 8 ma, driving voltage from 3V to 5V with a step of.5v, MOSFETs currents from to 8mA with a 1mA step, and MOSFETs widths from mm up to 3mm with a step of mm, which is the main difference with the semiconductor model used in [] and [4] since the operating range is extended from 16 mm to 3 mm. The model is applied to calculate buck converter power losses using Cadence software as the reference simulation. The buck is converting 5 V to 1. V, the driving voltages are 5 V and it is designed with lossless output filter composed of 465 nh inductor and 8 nf output capacitor. The Spice calculations have been performed for three scenarios: 1. the converter is switching at 5 MHz while the widths of both PMOS and NMOS are 16 mm;. the converter is switching at 1 MHz while the widths of both PMOS and NMOS are 1 mm; and 3. the converter is switching at 15 MHz while the widths of both PMOS and NMOS are 1 mm. The comparisons of the Spice calculations with the model estimation are presented in Fig In all figures, the losses calculated by the model in CCM operation are shown with the solid blue lined, while in DCM operation are presented with solid red lined with x marker. The Spice calculations are presented with green square marker for CCM operation and violet triangle for DCM operation. In Fig. 6 comparison of total losses of the converter are presented. It can be seen that the model predictions are in good agreement with obtained Spice calculations for both CCM and DCM operation. In Fig. 7 the drain to source PMOS losses (without the driving losses) are Page 8

9 Analysis and optimization with improved models, October 14 presented for all three scenarios, while the Fig. 8 shows PMOS driving losses. One again the Spice calculations are in good agreement with the estimations. Fig. 9 and Fig. 1 present the drain to source NMOS losses (without the driving losses) and NMOS driving losses are presented for all three scenarios respectively. Although the model predicts NMOS driving losses with relatively high accuracy, an error is present in NMOS drain to source losses due to the sensitivity of the model on estimated dead times (t dead_np and t dead_pn). In addition, it is assumed that NMOS is switching with ZVS, which is not the case since prior to the switching, NMOS is blocking the bodydiode voltage. As the switching frequency is increasing, those losses components have bigger influence on the error. In the Table II statistical parameters are shown. It can be seen that maximal absolute error in total power loss estimation is 5.6 mw for the output power range from 6 mw to 6 mw and that standard deviation is.1 mw. The relative errors are normalized to the output power, giving the maximal relative error of 4.43%, while the relative standard deviation of the error is 1.89%. Regarding the losses components, PMOS losses are estimated with relatively high accuracy, obtaining for drain to source losses maximal error of 1.6 mw (1.4% relative) and standard deviation of.58 mw (.5% relative), while driving losses have maximal error of 1.16 mw (1.94% relative) and standard deviation of.36 mw (.54% relative). As shown previously, NMOS losses are exhibiting bigger error: for NMOS drain to source losses, maximal error is 3.87 mw (3.54%) and the standard deviation is 1.76 mw (1.87%), while for NMOS driving losses, the maximal error is 1.83 mw (3.6%) and standard deviation is.51 mw (.81%). TOTAL 6 4 f SW = 5 MHz NMOS 1 f SW = 5 MHz TOTAL 1 5 f SW = 1 MHz NMOS 3 1 f SW = 1 MHz TOTAL 1 5 f SW = 15 MHz I OUT [ma] NMOS 4 f SW = 15 MHz I OUT [ma] TOTAL TOTAL TOTAL Fig. 7 Total losses: Estimation of CCM (blue solid line) and DCM (red solid, x marker), Spice calculations CCM (green, square) and DCM (violet, triangle) f SW = 5 MHz f SW = 1 MHz f SW = 15 MHz I OUT [ma] Fig. 9 PMOS source to drain losses: Estimation of CCM (blue solid line) and DCM (red solid, x marker), Spice calculations CCM (green, square) and DCM (violet, triangle) Fig. 8 NMOS source to drain losses: Estimation of CCM (blue solid line) and DCM (red solid, x marker), Spice calculations CCM (green, square) and DCM (violet, triangle) NDrive NDrive NDrive f SW = 5 MHz f SW = 1 MHz f SW = 15 MHz I OUT [ma] Fig. 1 NMOS gate driving losses: Estimation of CCM (blue solid line) and DCM (red solid, x marker), Spice calculations CCM (green, square) and DCM (violet, triangle) Page 9

10 Analysis and optimization with improved models, October 14 PDrive PDrive PDrive f SW = 5 MHz f SW = 1 MHz f SW = 15 MHz I OUT [ma] Fig. 11 PMOS gate driving losses: Estimation of CCM (blue solid line) and DCM (red solid, x marker), Spice calculations CCM (green, square) and DCM (violet, triangle) TABLE II. ERRORS OF THE MODEL err AVR [mw] err MAX [mw] σ [mw] P TOTAL P PMOStotal P PMOSdrv P NMOStota l P NMOSdrv REL err AVR [%] REL err MAX [%] σ REL [%] P TOTAL P PMOStotal P PMOSdrv P NMOStota l P NMOSdrv C e S S ph 8 ph 18 ph a) b) nf. nf 3.64 nf 6 pf 1.6 nf 7 pf 74 mω 86 mω 1.85 Ω ESR (Ohm) 1.1 N1n x 1 nf N3n6 x 3.6 nf N1n6 x 1.6 nf Capacitor (nf).1 Fig. 1 MOSAIC PICS3 capacitor: a) capacitor implementation and b) ESR C product. Fig. 13 Basic capacitor cells: 1 nf (blue), 3.6 nf (red) and 1.6 nf (green) basic building blocks..1.3 Capacitor model The capacitors are designed using IPDiA [11] low voltage MOSAIC PICS3 capacitor technology presented in Fig. 1a. Furthermore, in Fig. 1b the dependence of equivalent series resistance ESR on desired capacitance is presented. It can be seen that ESR C product is not constant and that for bigger values of capacitance the product increases. In other words, the zero of the capacitor, defined by the ERS and C goes down on the lower frequencies thus influencing the converter dynamic behavior. Moreover, the losses of the capacitor do not reduce linearly with increase of capacitance. Thus in order to improve behavior, capacitor model has been developed based on a basic capacitor blocks with low capacitance, presented in Fig. 13. Doing so, constant ESR C product is maintained, so the dominate zero is kept on higher frequencies and the losses reduce linearly with the capacitance. This approach has been used in [],[3],[4]. In order to generate desired capacitance C OUT, the basic building blocks are put in parallel in that manner that minimal number of cells is used. The blocks are defined for a cell of 1 nf, 3.6 nf and 1.6 nf, as shown in Fig. 13. Each cell is designed to occupy the same silicon area, penalizing density while improving performance. The equivalent capacitance, C eq, series resistance, ESR, and inductance, ESL, are calculated as parallel connections of each block capacitances, resistances and inductances, respectively: Page 1

11 Analysis and optimization with improved models, October 14 C eq N C N C N C, (1) 1n 1n 3n6 3n6 1n6 1n6 R1n R3n6 R1n 6 ESR, (11) N N N 1n 1n 3n6 3n6 1n6 L1n L3n6 L1n 6 ESL. (1) N N N The losses are calculated using capacitor RMS current, I C_RMS, and equivalent ESR: P C _ ESR 1n6 C _ RMS ESR I (13) Similarly as in the case of the inductor, both the input and the output capacitors are connected to the rest of the converter with TVSs at both terminals. The TVS is, once again, modeled as series impedance composed of a resistance R Cpar and an inductance L Cpar, which is added to the total impedance of the capacitor. The additional losses component, P Cpar, is calculated using capacitor current RMS value: P Cpar R Cpar I C _ RMS. (14). Low-frequency LVDC-DC The low-frequency LVDC-DC converter, presented in Fig. 14, is implemented as a single phase synchronous buck converter with peak current mode control (PCMC). The design details, presented in this chapter are obtained using CAD tool developed within this project and presented in [], [4]with improved models presented in previous subchapter. PCMC REGULATION S 1 C IN S L i L C OUT + v OUT -..1 System design Fig. 14 Low Voltage Low-frequency DC-DC converter. The system, optimized using the CAD tool, is composed of the 7 nh output inductor, nf output capacitor and 3 nf input capacitor while switching at 1 MHz. LVDC-DC is converting V to 1. V. As mentioned, the PCMC control of the converter is employed and the system is operating in continuous conduction mode (CCM), while discontinuous conduction mode (DCM), frequency modulation (FM) or Burst mode can be used for light load operation. In this sub-chapter, the implementation details of all components are presented. A. Inductor design The output inductor has been optimized by the CAD tool, with improved inductor model, while its design is validated using Finite element analysis (FEA) tool. The inductance of the output filter inductor is 7 nh. The geometry parameters as well as electrical are presented in TABLE III. while the geometry of the inductor is shown in Fig. 15. Page 11

12 Analysis and optimization with improved models, October 14 Fig. 15 The inductor geometry: 3D view (left), footprint (right) TABLE III. OUTPUT INDUCTOR GEOMETRY AND ELECTRICAL PARAMETERS Geometry Parameters Name Value Total area A T 3. mm Number of turns N 4 Core thickness T core 5.15 μm Core width W core 9.79 μm Core height H core 75.3 μm Core length L core μm Copper width W cu 45.6 μm Copper thickness T cu 35 µm Vertical spacing H air 15 µm Horizontal spacing W air µm Distance between cores D core.35 mm Electrical Parameters L (analytical) L (FEA tool) B. Capacitor design Value 7 nh 68 nh The output and input capacitors are designed using cell based approach presented in []. A targeted value of the capacitance is obtained by combining basic cells (1 nf, 3.6 nf and 1.6 nf). The optimal values and implementation of both the input and output capacitor are presented in TABLE IV. TABLE IV. INPUT AND OUTPUT CAPACITOR PARAMETERS Cap ESR N1n N3n6 N1n6 area CIN 3 nf 17.5 mω mm COUT nf 11.7 mω mm C. Semiconductor design Semiconductors design details are presented in TABLE V., where it can be seen that optimal widths for PMOS and NMOS are 1 mm and 1.8 mm, respectively, while using minimal length of the channels for rated input Page 1

13 Analysis and optimization with improved models, October 14 voltage of 65 nm for PMOS and 56 nm for NMOS. The driving voltages for both MOSFETs are 5 V in the case when the input voltage V IN is equal to 5 V, defining on-resistances of 46.7 and mω for PMOS and NMOS respectively; in the case that the input voltage is 3.3 V, the driving voltage is 3.3 V and the on resistances of PMOS and NMOS are 53.9 mω and 14.4 mω, respectively. As it can be noted, the on-resistance of the PMOS is around 4 times bigger than the NMOS, which is consistent with big conversion ratio (duty cycle is 4%), balancing conduction losses between the switches. TABLE V. SEMICONDUCTORS PARAMETERS Width Length RON (VGS=5V) RON (VGS=3.3V) IDrive PMOS 1 mm 65 nm 46.7 mω 53.9 mω 8 ma NMOS 1.8 mm 56 nm mω 14.4 mω 8 ma.. Static behavior Proposed optimal design has been tested in order to validate that the specification has been met. In order to obtain more realistic results, additional parasitic impedances are added to the passives, degrading the performance. The added impedances are representing interconnections and through-silicon via parasitics and they are modeled as series resistance of 1 mω and series inductance of 1 ph (values taken from IPDIA parasitic extraction). System variables waveforms for typical load operation (I OUT = 8 ma) with 5V input voltage are presented in Fig. 16 where it can be seen that both input and output voltage deviations are inside the specified range: the maximal output voltage peak-to-peak ripple is 7 mv and the input voltage peak-to-peak ripple is 6 mv, while the specification is imposing 6 mv and 5 mv respectively for the output and input voltage peak-to-peak ripple. The inductor current peak-to-peak ripple is 36 ma. Operating under maximal load operation (I OUT = 5 ma) the maximal output voltage peak-to-peak ripple is 8 mv and the input voltage peak-to-peak ripple is 44 mv, while the inductor current peak-to-peak ripple is ma. 1 Duty 14 1 v OUT [mv] i L [ma] 1 i Cout [ma] i Pmos [ma] v Cin [mv] i Nmos [ma] 4 i Cin [ma] t [ns] t [ns] Fig. 16 Waveforms of the state variables at typical load (8 ma) and V IN = 5V Page 13

14 Analysis and optimization with improved models, October 14 In the case when the input voltage is 3.3 V, the system variables waveforms for typical load operation (I OUT = 8 ma) are presented in Fig. 17. Once again it can be seen that both the input and the output voltage are within specified band. The steady-state output voltage peak-to-peak ripple is 13 mv, while the maximal specified value is 6 mv. The static input voltage peak-to-peak ripple is 8 mv, while the maximal specified value is 165 mv. The inductor current steady-state peak-to-peak ripple is 4.7 ma. Operating under maximal load operation (I OUT = 5 ma) the maximal output voltage peak-to-peak ripple is 13 mv and the input voltage peak-to-peak ripple is 48 mv, while the inductor current peak-to-peak ripple is 41.4 ma. 1 Duty 14 1 v OUT [mv] i L [ma] 1 i Cout [ma] i Pmos [ma] v Cin [mv] i Nmos [ma] 4 i Cin [ma] t [ns] t [ns] Fig. 17 Waveforms of the state variables at typical load (8 ma) and V IN = 3.3V Optimum efficiency results and total power losses for both cases of the input voltage are shown in TABLE VI.. Additionally, in TABLE VII. the absolute and relative breakdown of the losses are presented for typical load current. The system has been optimized for operation at the typical load, thus it can be seen that the losses for that case (Fig. 16 and Fig. 17) are balanced between the passives and the semiconductors: a) In the case when the input voltage is 3.3 V, the passives are generating 5.4% of the total power losses, while achieving efficiency of %; b) In the case when the input voltage is 5 V, the passives are generating 58.7% of the total power losses, while achieving efficiency of %. I OUT = 8 ma I OUT = 5 ma TABLE VI. TOTAL LOSSES AND EXPECTED EFFICIENCY V IN 3.3 V 5 V f SW MHz MHz Efficiency 78.71% % P Total 9.88 mw mw Efficiency 73.75% 73.59% P Total mw 15.9 mw Page 14

15 Analysis and optimization with improved models, October 14 TABLE VII. LOSSES BREAKDOWN AT TYPICAL LOAD CURRENT AT YPICAL LOAD (8 MA) V IN 3.3 V 5V P LoutCuDC 4.96 mw (7.46%) 5.3 mw (3.17%) P LoutCuAC 3.34 mw (3.67%) 5.37 mw (4.93%) P LoutFeHyst 6.7 mw (6.9%) 9.8 mw (8.5%) P LoutFeEddy 1.46 mw (13.7%) 3.38 mw (1.48%) Passive losses Cap. Losses Inductor Losses Semiconductor losses: NMOS Losses PMOS Losses P LTotalCu 8.3 mw (31.13%) 3.6 mw (8.1%) P LTotalFe mw (.6%) 3.66 mw (3%) P Lpar.83 mw (.9%).87 mw (.8%) P LTotal 47.3 mw (51.75%) 63.6 mw (58.1%) C OUTESR.9 mw (.9%).14 mw (.13%) C OUTpar.5 mw (.5%).8 mw (.7%) C INESR.5 mw (.7%).1 mw (.19%) C INpar.1 mw (.3%).18 mw (.16%) P PMOScond 18.5 mw (.36%) 9.58 mw (8.8%) P PMOSturn-on.95 mw (1.5%) 1.1 mw (1.1%) P PMOSturn-off 3.8 mw (3.61%) 5.6 mw (5.14%) P PMOSgate-drive 3.66 mw (4.3%) 7.37 mw (6.77%) P NMOScond 6.91 mw (7.6%) 7.8 mw (6.68%) P NMOSrev-rec 1.58 mw (1.74%).36 mw (.17%) P NMOSgate-drive 3.31 mw (3.64%) 6.59 mw (6.5%) P DT:PMOS NMOS 3.19 mw (3.51%) 3.48 mw (3.%) P DT:NMOS PMOS 1.4 mw (1.14%).8 mw (.73%) 8% 8% V IN = 3.3V 7% 6% 5% CCM DCM Burst I [ma] OUT V IN = 5.V 7% 6% 5% CCM DCM Burst I [ma] OUT Fig. 18 Dependence of the converter efficiency on the load current with V IN = 3.3V (left) and V IN = 5.V (right) Furthermore, in Fig. 18 the converter efficiency dependence on the load current is presented for both 3.3V input voltage and 5V input voltage. The estimation of the efficiency is calculated assuming CCM operating mode (blue), DCM+CMM operating mode (green) and BURST+CCM operating mode (red). Operating with moderate and high load, the system efficiency is defined with CCM operation, thus the dependences are the same, while under the light load the best efficiency can be achieved operating in BURST mode since the switching losses are minimized. Comparing the efficiency with two different input voltages, the efficiency is improved by reducing the input voltage to 3.3V since conduction losses are not drastically affected, as it can be seen when the converter operate under heavy load, and the switching losses are reduced. Page 15

16 Analysis and optimization with improved models, October 14.3 High-Frequency LVDC-DC For the high frequency converter (1 MHz), the main effort has been first focused on the power stage. Two main configurations were intensively investigated: the standard power stage and the cascode power stage, depicted in the figures below. Fig. 19 Standard power stage Fig. Cascode power stage The standard power stage uses only 3.3 V devices. It consists of power transistors, referred as the HS (High Side) and LS (Low Side) power transistors. The HS transistor is a PMOS, driven by tapered buffers. The LS transistor is a NMOS, also driven by tapered buffers. The optimization of this power stage was made by varying the sizes of the HS and LS transistors, and the drive strength of each buffer rail. The cascode power stage, on the other hand, uses only 1. V devices. It consists of 3 PMOS transistors, acting as the HS transistor of the standard power stage. Three NMOS transistors act as the LS transistor of the standard power stage. To enable these transistors to work together, it is necessary to add other transistors to keep the right polarization on each power transistor. This power stage is driven by 3 buffers rails, switching 1.1 V each, with shifted DC bias: the low rail is switching from V to 1.1 V, the middle rail is switching from 1.1 V to. V and the high rail from. V to 3.3 V. During the optimization, all the sizes of the MOSFETs were allowed to vary independently, except for the 3 power PMOS that had the same size, and the 3 power NMOS also had the same size. A primary optimization was carried out for various configurations (1 and MHz switching frequency, and 336 and 168 mw output power), using an ideal input voltage source and an ideal output current sink. The efficiency of the power and its first-stage driver was evaluated (these elements are the biggest contributors to losses). The table below summarizes the optimization results. TABLE VIII. EFFICIENCY EVALUATION OF POWER STAGES IN VARIOUS CONFIGURATIONS These results show that each power stage gives better efficiency when working at 1 MHz and 168 mw. For a nominal power of 336 mw, this will be the configuration of a -phase converter. In order to avoid short-circuit current in the power stage, the drivers have been changed to non-overlapping drivers (depicted in Fig. ), i.e. one driver controls only one MOSFET. In order to achieve proper behavior at MHz, these drivers need to be controlled very precisely. Page 16

17 Analysis and optimization with improved models, October 14 Fig. 1 Cascode power stage Fig. Cascode power stage with non-overlapping drivers TABLE IX. POWER STAGES AND FULL CONVERTERS (INCLUDING ALL ACTIVE DEVICES: DRIVERS, LEVEL SHIFTER, CURRENT REFERENCE) EFFICIENCIES WITH NON-OVERLAPIING DRIVERS Standard Cascode Power stage Full converter Power stage Full converter FSW (MHz) POUT (mw) Max efficiency (%) Using non-overlapping drivers increases significantly the power stage efficiency (from 9.5 % to 94.4 % for the cascode power stage). However, the efficiency is reduced when taking into account all the contributors. The TABLE IX. summarizes the efficiency results of the designed structure, measuring the power stage efficiency only and the full converter efficiency (active part). We note that for the standard converter, the complimentary circuits (mainly the drivers) are adding more losses than the cascode, because the drivers are switching with a higher voltage swing. For the -phase converter, an optimization has been done on the output filter. This optimization assumed ideal power stages. Page 17

18 Analysis and optimization with improved models, October 14 k L1 L Lout Structure used of output inductors optimization Case 1: No coupling and no output inductor Optimization results: - k =, L OUT = nh, L PH = 45.5 nh - Phase current ripple: 17 ma - Ripple reduction vs. previous case: % Case : Coupling and no output inductor. Optimization results: - k =.4, L OUT = nh, L PH = 45.5 nh - Phase current ripple: ma - Ripple reduction vs. uncoupled: 1 % Case 3: coupling and output inductor. Optimization results: - k = 1, L OUT = 1 nh, L PH = 35 nh - Phase current ripple: 13.8 ma - Ripple reduction vs. uncoupled: 8 % The results of this optimization show that having tightly coupled inductors on each phase and an output inductor gives the smallest phase current ripple, thus the smallest switching and conduction losses on the power stage. These optimization results are leading to the fully optimized but still quite ideal system that will have interleaved and cascoded phases, and a coupled output filter, as depicted in the figure below (non-overlapping drivers are omitted for the sake of readability). Fig. 3 Full architecture of DC-DC converter Page 18

19 Analysis and optimization with improved models, October 14.4 Switch Capacitor converter.4.1 SC DC-DC Converter The designed switched capacitor DC- DC converter is implemented as a four phase interleaved converter. It converts a 5V or 3.3V input voltage down to 1.3V or 1.V with a typical efficacy of 75%. The converter can handle load currents up to maximum ma with dynamic load jump of 5mA/ns. Figure 4 shows the top level block diagram of the designed switched capacitor DC-DC converter. It consists mainly of four switched capacitor unit stages, a voltage comparator, a start-up current source and the Pulse Frequency Modulation (PFM) controller. The power flow from the converter input to the output is highlighted in red and buffered by the input capacitor Cin and the output capacitor Cout. The four times placed unit stage includes a switch network, a chain of buffers and a level-shifter block. The switch network illustrated in Figure 7 is the core of the converter and consists of nine power switches and two flying capacitors. Out of that, two different gain modes (1/ and 1/3) are realized to convert the input voltage down to the output voltage. Each of the nine power switches is driven by its own buffer circuit, which get its input signal from the level-shifter block. Inside the level shifter block, a switching signal coming from the controller is decoded depending on the gain mode into nine individual switching signals. To regulate the output voltage, a voltage comparator is implemented which monitors the output voltage and compares it with an internal generated reference voltage. The output signal of the comparator is used inside the controller to generate the Pulse Frequency Modulated (PFM) switching pulses. These switching pulses are further on converted into four time interleaved signals, which controls the four unit stages. In Addition, a digital Finite State Machine (FSM) is implemented which controls the start-up and puts the converter into normal operation or into different debugging modes. Fig. 4: Block diagram switched capacitor DC-DC converter The output voltage ripple and the power conversion efficiency of the converter were optimized on model level in Matlab but also on circuit level with transient simulations over PVT. In order to consider also parasitic layout effects the optimization process of the circuit included also simulations with RC extracted netlists from the layout. Simulation results that show the regulation behavior of the converter and the output current capability are shown in Fig. 5. It can be seen that the switching frequency of the converter depends on the load at the output of the converter (PFM). Furthermore, the output voltage of the converter will remain stable also at maximum load current, Page 19

20 Analysis and optimization with improved models, October 14 Fig. 5: Transient simulation results of the SC DC-DC for different gain modes.5 High-Voltage DC-DC Converter System (HVDC-DC) The HV DC-DC converter is an inductor-based step-down regulator that operates at a frequency of 1MHz. The acceptable input voltage range goes from 6V to 16V while the output voltages for which the design has been optimized are 3.3V and 5V. The maximum output current is 5mA. Figure 9 shows the block diagram of the optimized design. The PWM signal driving the power stage can be either provided from outside (from an external controller) or generated internally (for open loop testing). In the latter case the duty cycle can be programmed through SPI. The supply for the low-side switch driver is generated by an LDO (the low-side LDO ) which in turn is supplied by the regulator output voltage (for higher efficiency). Because the output voltage is initially low at startup another LDO ( the Startup LDO ) will pre-charge the output capacitor to 3V before the switching begins. An external bootstrap capacitor generates a voltage (higher than V IN) from which the high-side driver is powered. The external capacitors are integrated on a separate die that will be enclosed in the same package as the regulator IC: C IN = nf, C OUT = 1μF, C LS = 4nF, C HS = nf. The 1uH inductor is a separate component that is also enclosed in the package. The power stage of the converter, the driver and switching time instants of the power switches were optimized for best power conversion efficiency. The optimization was done for PWM-CCM. Fig. 7 shows simulation results of the power conversion efficiency at different load currents and for two different converter output voltages of 5V and 3.3V. The converter achieves a peak efficiency of about 87% at a load current of 4mA and an input voltage of 1V. Page

21 Analysis and optimization with improved models, October 14 Fig. 6: Block diagram of optimized HV DC-DC converter Fig. 7: Power conversion efficiencies of the converters at different load currents with the optimized converter power stage at 1MHz switching frequency 3. Conclusions This report shows the main results of the analysis and optimization with improved models of the main converters of the systems. Regarding the improvements of the models with respect to the previous report: Integrated magnetic analytical models have been improved for both the estimation of the inductance and the calculation of the losses. Optimization of the magnetic components has also been improved by not constraining the design to achieve the highest saturation (reduce volume). By allowing the optimizer to choose a flux density bellow the maximum it it possible to reduce core losses, which is beneficial at high frequencies. Improved models of semiconductor losses estimation by means of the characterization of the energy losses of the semiconductor devices under wide operating conditions. This characterization is made offline by extensive simulations in CADENCE and the results are stored for future optimizations. With respect to the optimization results of the converters selected for this architecture: LV Low Frequency DC-DC. Page 1

22 Analysis and optimization with improved models, October 14 o When the input voltage is 3.3 V, the passives are generating 5.4% of the total power losses, while achieving efficiency of %; o When the input voltage is 5 V, the passives are generating 58.7% of the total power losses, while achieving efficiency of %. o In both cases, the optimum design is obtained at a switching frequency of 1 MHz LV High Frequency Converter o Two main configurations have been intensively investigated: the standard power stage and the cascode o The optimization shows that having tightly coupled inductors on each phase and an output inductor gives the smallest phase current ripple, thus the smallest switching and conduction losses on the power stage. SC DC-DC Converter o It is implemented as a four phase interleaved converter. It converts a 5V or 3.3V input voltage down to 1.3V or 1.V with a typical efficacy of 75%. o The converter can handle load currents up to maximum ma with dynamic load jump of 5mA/ns. o The power conversion efficiency of the converter were optimized on model level in Matlab but also on circuit level with transient simulations. The HV DC-DC converter o It is an inductor-based step-down regulator that operates at a frequency of 1MHz. o The power stage of the converter, the driver and switching time instants of the power switches were optimized for best power conversion efficiency. o The optimization was done for PWM-CCM. o The converter achieves a peak efficiency of about 87% at a load current of 4mA and an input voltage of 1V. References [1] [] D.1: Architecture Analysis and Evaluation [3] D.: Analysis and optimization of the integrated Passives [4] D.3: Analysis and optimisation of selected architectures [5] R. W. Ericson and D. Maksimović, Fundamentals of Power Electronic, second edition, University of Colorado, Boulder, Colorado. [6] Y. Yan, F. C. Lee and P. Mattavelli, Unified Three-Terminal Switch Model for Current Mode Controls, IEEE Trans. Power Electron., vol. 7, no. 9, pp , Sep. 1. [7] [8] T. M. Andersen, C. M. Zingerli, F. Krismer, J. W. Kolar, N. Wang and C. O. Mathuna, Modeling and Pareto Optimization of Microfabricated Inductors for Power Supply on Chip, IEEE Trans. Power Electron., vol. 8, no. 9, pp , Sep. 13 [9] [1] V. Svikovic, J. Cortes, P. Alou, J. Oliver, and J. A. Cobos, Energy-Based switches losses model for the optimization of PwrSoC buck converter, in Control and Modeling for Power Electronics, 14. COMPEL 14., June, 14. [11] Page