CAD Tool for the optimization of Power Converters on Chip

Transcription

1 CAD Tool for the optimization of Power Converters on Chip Jesús A. Oliver, Pedro Alou and José A. Cobos Universidad Politécnica de Madrid

2 2 The need of an integrated multi-domain tool μc 3.4mm 16V-6V CHVin PMIC HV DC-DC 130nm BCD-CMOS L1 CHVout IFAT Automotive Specifications (ISO pulses, temperature, 101V VINT= 5V-3.3V CLVin System IC LV DC-DC SC DC-DC Dummy Load 1 HF DC-DC Load 2 L2 CLVout Vcore=1.2V C3out Vdd2=1.2V IFAT 40nm Flash CMOS Ampere 40nm Flash CMOS C IN Cout SC 2.6mm x 0.4mm 260nF S 1 Cin LV+SC+LDO 665nF 1.4mm x 1.9mm Chip: 1.8mm x 1.39mm Cf Cf flying cap Cf: 30nF PCMC REGULATION S 2 Cf Cf Cf Cf Cf Cf L Lout LV 400nF 1.6mm x 1.6mm Cout LV 400nF 1.6mm x 1mm i L COUT + v OUT - 2.6mm 40V 4V/ms 14V 6ms 400 ms 2

3 3 State of the art CAD Tools Circuit Level Simulators Magnetic Component Optimization Tools PEXprt-Pemag developed by UPM Lack of integrated design environment for Power Systems on Chip Finite Element Analysis Tools General Purpose Math Tools 3

4 System Level Analysis and Optimization Tool Total Area Static Spec Dynamic Spec 5 V 1.2V I o Capacitors 280mA v o Δv o Topology Regulator Constraints Inductor Optional V RAMP + V REF + - H V (s) - v OUT Rippled signal + Power Stage Semiconductors v OUT Operating Mode Continuous Conduction Mode Converter efficiency (%) Frequency Sweep of the solutions ηrm-il ηim-rl ηrm-cul ηrm-rl PWRSoC fsw (MHz) 2016 Madrid Analysis of the system i L v OUT i L v OUT i L Discontinuous Conduction Mode BURST Mode 4

5 Built-in Simulator Steady-state and transient waveforms Optimal Control Design System level performance Open loop vs closed loop Zout Time domain waveforms Loop Gain 5

6 Turn-Off Transient Energy of PMOS Example: HI-Side (LV-DC-DC) PMOS Switching Losses 1.2 E DRIVER E TurnON E TurnOFF 2 1 E turnoff [nj] w [mm] f SW = 10 MHz I DS [ma] E LOSSES [nj] nj 0.78 nj 0.16 nj 0 I 0 I I DS [ma] 700 I P TurnOFF P TurnON P Driver = 7.86 mw = 1.6 mw = 6.25 mw i PMOS [ma] I 0 I PMOSrms = ma R PMOSon P COND = 410 mω = 14.2 mw t/t SW 6

7 7 LV DC-DC Optimization Results Geometry Parameters Name Value Total area A T 3.2 mm 2 Number of turns N 4 Core thickness T core 5.15 μm Core width W core μm Core height H core 75.3 μm Core length L core μm Copper width W cu μm Copper thickness T cu 35 µm Vertical spacing H air 15 µm Horizontal spacing W air 20 µm Distance between cores D core 0.35 mm Electrical Parameters Value L (analytical) 270 nh L (FEA tool) 268 nh Cap ESR area C IN 300 nf 17.5 mω 1.5 mm 2 C OUT 200 nf 11.7 mω 1 mm 2 R ON R ON Width Length (V GS =5V) (V GS =3.3V) PMOS 12 mm 650 nm mω mω 80 ma NMOS mm 560 nm mω mω 80 ma 7 I Drive

8 8 LV DC-DC Optimization Results IN S 1 PCMC S 2 L REGULATION i L C OUT + v OUT - V IN 3.3 V 5 V f SW MHz MHz I OUT = 280 ma Efficiency 78.71% % P Total mw mw I OUT = 500 ma Efficiency 73.75% 73.59% P Total mw mw Losses Breakdown Total P TOTAL [mw] P MOSFET s [mw] P C [mw] P L [mw] 80 Inductor loss CMOS loss f PWRSoC 2016 SW [MHz] Madrid 8

9 Evaluation of the Impact of technology 100 Efficiency of the system FOM = R Q DSON G 95 2x actual Si 90 Actual Si 2% η [%] Actual L f SW [MHz] Improvement of Si technology has stronger influence at high f sw A technology two times better, provides 2 % improvement in the efficiency (@ f sw >12MHz) η (tech, 12MHz) = 89% η (2xtech, 12MHz) = 91% 40% switching losses and 60% conduction losses 9

10 10 Efficiency: 77.21% Lout 1% < 1% 20% 27% PMOS System Level Optimization electrical performance 2% Losses breakdown 6% NMOS 3% 3% 9% 4% 1% < 1% 5% % Lout hf: (1.67 %) Lout dc: (20.38 %) Lout PAR (1.47 %) Cout ESR (0.03 %) Cout PAR (0.05 %) Cin ESR (0.15 %) Cin PAR (0.30 %) PMOS conduction (26.73 %) PMOS turn-on (3.16 %) PMOS turn-off (8.69 %) PMOS gate-drive (4.60 %) NMOS conduction (18.23 %) NMOS turn-off (0.00 %) NMOS reverse-recovery (1.43 %) NMOS gate-drive (4.17 %) dead-time:pmos2nmos (6.29 %) dead-time:nmos2pmos (2.65 %) CCM DCM Burst Dynamic behavior CCM Efficiency vs load CCM DCM Burst I OUT [ma] i L [ma] i REF [ma] i REF -ramp [ma] v OUT [mv] t [ns] 10

11 FEA Modeling/Validation of Coupled Inductors PARAMETERS Option A: Maxwell 3D simulations Geometry Parameters Name Value Total area A T xx mm 2 Number of turns N 4 Core thickness T core 6 µm Core width (Inductor) W corei 157 µm Core width (Transformer) W corei 187 µm Core height H core 127 µm Core length L core 1.00 mm Copper width W cu 50 µm Copper thickness T cu 35 µm Vertical spacing H air 15 µm Horizontal spacing W air 15 µm Distance between cores D core 264 µm Material parameters Value Resistivity core 45 μω*cm Relative Permeability core 280 Resistivity copper 1.71 μω*cm L Analytical (simple) L Analytical L M = nh(complex) L K = nhl M = nh L K = L FEA L M = nh L K = nh 11

12 PowerSWIPE ITVs L (nh) 200 MHz Single Inductor (33nH) Core Thickness Simulation Results Core Length Copper width Copper Thickness DCR (Ohm) Device Footprint ITV 2A µm 1.22 mm 72.2 μm 35 μm mm 2 87,4% 33nH 95,5 % 200 MHz Total converter efficiency 83% 12

13 100 MHz Coupled Inductors (47nH) Simulation Results PowerSWIPE ITVs ITV 2B L (nh) 47 Coupled (k=0.4) Core Thickness Core Length Copper width Copper Thickness DCR (Ohm) Device Footprint 1.6 µm 1.78 mm μm mm % 90,4% Total converter efficiency 81% 13

14 PowerSWIPE ITVs ITV 2C L (nh) 35 nh Coupled k= MHz Coupled Inductors (35nH) + Single Inductor (20nH) Core Thickness Simulation Results Core Length Copper width Copper Thickness DCR (Ohm) Device Footprint 1.6 µm 1.83 mm μm 15 μm mm 2 20 nh 1.6 µm 0.78 mm 97 μm 35 μm mm % 90.25% 94.8% 90,4% Total converter efficiency 77% 14

15 Coupled Inductor Comparison Comparison single-phase and two-phase dc/dc converter Inductor design Freq. (MHz) L (nh) Coupling factor Efficiency (magnetics) Efficiency (IC) Total efficiency ITV2a Single phase ,5 % 87,4% 83% ITV2b Coupled ~0.4 90% 90,4% 81% ITV2c Coupled +Lout > % (90.25% 94.8%) 90,4% 77% 15

16 16 Conclusions 1 st Integrated multi-domain optimization tool for PwrSoC Physical Design Topologies and Control Minimim LC requirements Technologies E turnoff [nj] Turn-Off Transient Energy of PMOS w [mm] I DS [ma] Accurate Models 16

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