Chapter 2 Buck PWM DC DC Converter

Transcription

1 Chapter 2 Buck PWM DC DC Converter H. Wang, Power Management and High-speed I/O in CMOS Systems 1/25

2 Buck Circuit and Its equivalent circuits CCM: continuous conduction mode DCM: discontinuous conduction mode Critical mode: CCM/DCM boundary Duty cycle D freewheeling diode, a flywheel diode, or a catch diode H. Wang, Power Management and High-speed I/O in CMOS Systems 2/25

3 CCM / DCM CCM: continuous conduction mode DCM: discontinuous conduction mode H. Wang, Power Management and High-speed I/O in CMOS Systems 3/25

4 How to reach the steady state? H. Wang, Power Management and High-speed I/O in CMOS Systems 4/25

5 Idealized current and voltage waveforms in the PWM buck converter for CCM v GS v L 0 V I -V O 0 -V O il I O V I DT A + DT V I A - T V O L i L _ V O L T t t 0 i S I SM DT I O T t I I 0 v S DT T t V SM =V I 0~DT 0 i D DT T I O t I D 0 v D 0 DT DT T T t t DT~T -V I H. Wang, Power Management and High-speed I/O in CMOS Systems 5/25

6 Device Stresses for CCM The maximum voltage and current stresses of the switch and the diode in CCM for steady state operation are H. Wang, Power Management and High-speed I/O in CMOS Systems 6/25

7 DC Voltage Transfer Function for CCM Based on the principle of inductor volt-second balance, we know that A A ( V V ) DT V (1 D) T I O O ( V V ) D V (1 D) I O O VD I VODVO VOD M V O VDC DV V V O I I D H. Wang, Power Management and High-speed I/O in CMOS Systems 7/25

8 Efficiency How about of the efficiency of the ideal buck DC-DC converter? 100%!!! H. Wang, Power Management and High-speed I/O in CMOS Systems 8/25

9 Boundary between CCM and DCM Peak inductor current DC load current at the boundary Load resistance at the boundary The worst case for maintaining in CCM The minimum inductance required to maintain the CCM. H. Wang, Power Management and High-speed I/O in CMOS Systems 9/25

10 Ripple Voltage in Buck Converter for CCM i i I C L O Figure 2.6 Output circuit of the buck converter v (0) v ( DT) v ( T) c c c Figure 2.7 Waveforms illustrating the ripple voltage in the PWM buck converter. v v v o rc c H. Wang, Power Management and High-speed I/O in CMOS Systems 10/25

11 Ripple Voltage in CCM C C min C C min The peak-to-peak ripple voltage is independent of the voltage across the filter capacitance C and is determined only by the ripple voltage across the ESR if C C min max D,1 D max 2 f s r C min For the worst case, Dmin = 0 or Dmax = 1. Thus, the above condition is satisfied at any value of D if C C min 1 f r 2 s C C C min Namely rc C T 2 H. Wang, Power Management and High-speed I/O in CMOS Systems 11/25

12 Ripple Voltage in CCM If condition shown in following equation is not satisfied, both the voltage drop across the filter capacitor C and the voltage drop across the ESR contribute to the ripple output voltage. C C min max D,1 max f r 2 s C D min The conservative estimation of the total voltage ripple is H. Wang, Power Management and High-speed I/O in CMOS Systems 12/25

13 Power losses Switching Losses with Linear MOSFET Output Capacitance C o Switching energy loss in every cycle W CV 2 sw o I Total switching loss in the converter is P f CV 2 sw s o I H. Wang, Power Management and High-speed I/O in CMOS Systems 13/25

14 Power losses Assume: The inductor current i L is ripple-free and equals the dc output current I O. Figure 2.9 Equivalent circuit of the buck converter with parasitic resistances and the diode offset voltage. Similarly H. Wang, Power Management and High-speed I/O in CMOS Systems 14/25

15 Converter Efficiency The overall power loss is given by Thus, the converter efficiency is H. Wang, Power Management and High-speed I/O in CMOS Systems 15/25

16 Efficiency vs Output Current H. Wang, Power Management and High-speed I/O in CMOS Systems 16/25

17 DC Voltage Transfer Function of Lossy Converter for CCM H. Wang, Power Management and High-speed I/O in CMOS Systems 17/25

18 MOSFET Gate-drive Power W Q V G g GSpp P W f W f Q V T G G S G S g GSpp The power gain is defined by k p P P O G The power-added efficiency (PAE) ( 附加功率效率 ) PAE P O P I P G The total efficiency is defined by t P I PO P G H. Wang, Power Management and High-speed I/O in CMOS Systems 18/25

19 DC Analysis of PWM Buck Converter for DCM 0~DT DT ~( D D ) T 1 ( D D ) T ~ T 1 H. Wang, Power Management and High-speed I/O in CMOS Systems 19/25

20 CCM/DCM H. Wang, Power Management and High-speed I/O in CMOS Systems 20/25

21 DC Voltage Transfer Function for DCM DC Voltage Transfer Function for DCM volt-second balance principle: A + =A -, so, We can also get (p58 in textbook.) Maximum Inductance for DCM Maximum duty cycle at the CCM/DCM boundary H. Wang, Power Management and High-speed I/O in CMOS Systems 21/25

22 Power Losses and Efficiency for DCM Neglecting the power loss in the ESR of the filter capacitor H. Wang, Power Management and High-speed I/O in CMOS Systems 22/25

23 Buck Converter with Synchronous Rectifier H. Wang, Power Management and High-speed I/O in CMOS Systems 23/25

24 CCM at no load condition H. Wang, Power Management and High-speed I/O in CMOS Systems 24/25

25 Summary Step-down, transformerless, nonisolated, CCM/DCM The converter has conduction losses and switching losses. The duty cycle D of the lossy converter is greater than that of the lossless converter at the same dc voltage transfer function. The peak-to-peak value of i L is independent of the dc load current for CCM. Input current is pulsating. The ESR of the inductor in DCM is usually lower than that in CCM because the inductance is lower. The efficiency of the converter in CCM is higher than that in DCM at the same dc input and output currents and the same switching frequency. Why? H. Wang, Power Management and High-speed I/O in CMOS Systems 25/25