Deliverable 3.1 Passive Components Fabrication

Transcription

1 PowerSWIPE (Project no ) POWER SoC With Integrated PassivEs Deliverable 3.1 Passive Components Fabrication Dissemination level: PU Responsible Beneficiary Tyndall National Institute, University College Cork Due Date 31 st August 2014 Submission Date 15 th October 2014 FP7-ICT Collaborative Project (STREP) PowerSWIPE (Grant agreement ) Objective ICT Very advanced nanoelectronic components: design, engineering, technology and manufacturability

2 Summary No and name D3.2 Passives Components Fabrication 1 Status Released Due Month 23 Date 31-August-2014 Author(s) Santosh Kulkarni, Editor Santosh Kulkarni, Nicolás Cordero DoW Report on Passive Components Fabrication Dissemination Level PU - Public Nature Report Document history V Date Author Description Draft 29-September-2014 Santosh Kulkarni Draft Final 15-October-2014 Santosh Kulkarni Final 1 Disclaimer - The information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability. 2/10

3 1. Table of Contents 1. Table of Contents Introduction Passive Component Fabrication process Magnetics on silicon process flow for SLM inductor devices Magnetics on silicon process flow for DLM inductor devices Initial evaluation results Conclusions /10

4 2. Introduction This report details the fabrication process of all the different inductor designs for Powerswipe project. The main technical objective of the work is to develop high efficiency magnetic components on Silicon, which will later be packaged on the interposer along with the capacitor and PMIC. In particular the focus is on the development of micro-inductors, for low power, nonisolated converters, and capable of operating efficiently at frequencies in the range of 10 MHZ (Demo 1) and hundreds of MHz (ITV2). Consequently the focus of the design and modelling work is on how to achieve high inductor efficiency through different inductor structures including single phase, multi-phase and coupled inductor structures, when the operation frequency is increased from 5 MHz to as high as 200 MHz. Figure 1. Top view and cross-section of the Magnetic structure (ILD- Inter layer dielectric, IMD- Inter metal dielectric) This is a 5 mask process, with 3 metal layers (2 magnetic and 1 conductor) and two insulation layers (Inter layer dielectric and Inter metal dielectric). The conductor layer is sandwiched between two magnetic layers. Two different dielectrics are used for passivation of the bottom magnetic core-conductor and conductor-top magnetic core. This report describes the fabrication of the first inductor run. In particular some process changes were introduced in order to ensure that the performance of the inductors could be implemented as a coupled topology with lower coupling factors. This report details the fabrication steps involved in developing a single layer metal structures and double layer metal structures. 3. Passive Component Fabrication process In the design phase, the Powerswipe consortium were targeting to demonstrate a low frequency Power Supply in Package for automotive applications and a very high frequency Power Supply topology using capacitor interposer. The design optimization phase proposed seven inductor 4/10

5 designs to address the requirements of the different demonstrators. The table below details the design specifications of different demonstrators. PowerSWIPE ITVs L (nh) Core Length (mm) Copper Width (μm) Copper Thickness (μm) DCR (Ohm) Device Footprint (mm 2 ) Demo ITV 2A ITV2B 47 Coupled Coupled ITV2C 35 Coupled Push pull Table 1. Design specifications for Powerswipe inductors 3.1 Magnetics on silicon process flow for SLM inductor devices The Tyndall Magnetics on silicon Single Layer Metal (SLM) or single copper winding process is a 5 mask with 20 process steps. A flow chart of all the steps involved in shown in Figure 2. This process is used to realise Demo 1 and ITV 2A inductors. Figure 2. Flow chart of steps in SLM Tyndall Magnetics on Silicon process The magnetic core used in the structure is Ni45Fe55 thin film. This core is electroplated on a sputtered Ni80Fe20 seed layers. This material and is used for top core deposition also. The first 5/10

6 insulation layer or the Inter Layer Dielectric is a BCB46 polymer which is spun on, patterned and cured. The copper windings are electroplated on a sputtered copper seed within high aspect ratio resist structures. The second insulation layer or Inter Metal Dielectric is a spun on and patterned Su The top core passivation is done by a spin coated and patterned Su The mask layout for SLM devices is shown below in Figure 3. Figure 3. Mask Layout for SLM Inductor Devices 3.2 Magnetics on silicon process flow for DLM inductor devices For ITV2 devices Tyndall are in the process of prototyping Double Layer Metal structures (stacked copper). The DLM mask layout is shown in Figure 4. The process for realising an inductor structure with double copper windings is shown below in Figure 5. The DLM fabrication process is the same as the SLM process for the first three steps (until 1 st Copper layer). At this point, the DLM process uses a thinner Su-8 to insulate the 1 st copper windings and then deposit the second copper windings using electroplating technique. The remaining steps for IMD deposition to top core passivation are the same as in SLM process. 6/10

7 Figure 4. Mask Layout for DLM inductor devices Figure 5. Process flow for DLM inductor device fabrication 7/10

8 3.3 Initial evaluation results Figure 6 shows a fully fabricated SLM device wafer. Further initial electrical characterization of the SLM inductor designs was also completed. The characterization involved small signal testing using HP 4285 LCR meter with HP42841 current source. Two different inductance tests were conducted one at varying frequency (100 khz-20 MHz) and second at varying bias currents (0-500 ma). Figure 6. Fully fabricated SLM device wafer Figure 7 show the frequency scan of inductance for three different Demo 1 inductors. Figure 8 compares the inductance variation with design value for 80 Demo 1 devices. These devices will be included in the reliability study task. 8/10

9 Figure 7. Inductance vs Frequency plots for typical Demo 1 devices Further, the variation of inductance with bias current is plotted in Figure 9. This measurement was done at 10 MHz frequency and ac current of 10 ma. Figure 8. Inductance variation over 80 Demo1 devices 9/10

10 4. Conclusions Figure 9. Variation of inductance with bias current This report details Passive Component fabrication processes for different inductor designs developed in PowerSwipe project. The fabrication process is based on Tyndall s Magnetics on silicon process technology for racetrack structures. The report explains in detail the different process steps involved in realising a SLM and DLM device structure. The Tyndall s SLM magnetics on silicon process is a 5-mask layer technique with the DLM process requiring additional two masks. The report also includes initial characterization for Demo 1 SLM devices. These devices will be subjected a detailed reliability study which will include thermal cycling, high temperature storage, high humidity test etc. Further, two SLM wafers will be used for packaging Demo 1 converter using Infineon s ewlb process. 10/10