CAD tool to optimize the design of a PowerSoC converter: Powerswipe design case

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cei@upm.es CAD tool to optimize the design of a PowerSoC converter: Powerswipe design case V.

1 CAD tool to optimize the design of a PowerSoC converter: Powerswipe design case V. Šviković; J. Cortes, P. Alou; J. A. Oliver; José A. Cobos Universidad Politécnica de Madrid

2 Introduction CAD Tool Consortium Leader Magnetics on Silicon IC Design 200MHz LV PMIC IFAT Villach IC Design / Architecture IFX Regensburg Chip/Package CoDesign Capacitors Integration Interposer Gasoline engine ECU System requirements PAGE 2

3 10 6 x factor PAGE 3

4 FDxprt (Filter Design) Part of this knowledge is needed in PowerSoC 3 PHASE GENERA TOR AGxprt (Architecture Generator) EMI AC/DC C o COxprt (circuit optimization) DC/DC isolated DC/DC isolated DC/DC isolated DC/DC isolated LOAD LOAD LOAD... LOAD ChTool (Characterization Tool) PExprt (Magnetic components) PAGE 4

6mm x 0.4mm 260nF Cin LVSCLDO 665nF 1.4mm x 1.9mm Chip: 1.8mm x 1.

5 The need of an integrated multidomain tool μc 3.4mm 16V6V CHVin PMIC HV DCDC 130nm BCDCMOS L1 CHVout IFAT VINT= 5V3.3V CLVin System IC LV DCDC SC DCDC Dummy Load 1 HF DCDC L2 CLVout Vcore=1.2V C3out IFAT 40nm Flash CMOS Ampere Cout SC 2.6mm x 0.4mm 260nF Cin LVSCLDO 665nF 1.4mm x 1.9mm Chip: 1.8mm x 1.39mm Cf Cf Cf Cf PCMC Cf Cf flying cap Cf: 30nF Cf Cf Lout LV 400nF 1.6mm x 1.6mm Cout LV 400nF 1.6mm x 1mm REGULATION 2.6mm Load 2 Vdd2=1.2V 40nm Flash CMOS C IN S 1 S 2 L i L COUT v OUT PAGE 5

lack of integrated design environment for Power Systems on

6 CAD Tools available Circuit Level Simulators Magnetic Component Optimization Tools PEXprtPemag developed by UPM lack of integrated design environment for Power Systems on Chip Finite Element Analysis Tools General Purpose Math Tools PAGE 6

7 IC perspective Optimized PwrSoC 3.3 5V DCDC DCDC V 1.2 V DCDC 40 nm DCDC 3.3 5V DCDC DCDC ~10 MHz V 1.2 V ~ 100 MHz DCDC 40 nm DCDC PAGE 7

8 IC perspective Optimized PwrSoC 3.3 5V DCDC DCDC V 1.2 V DCDC 40 nm DCDC Defined Si tech PAGE 8

9 IC perspective V DR_PMOS V IN v SG_PMOS i PMOS S HIGH Optimized PwrSoC v SD_PMOS L 3.3 5V i L DCDC DCDC 40 nm V 1.2 V DCDC DCDC known switching structure VDR_PMOS VIN V DR_NMOS vsg_pmos ipmos SHIGH vsd_pmos L il i NMOS v GS_NMOS v int S LOW C OUT v OUT inmos VDR_NMOS vgs_nmos vint SLOW COUT vout Defined Si tech PAGE 9

10 IC perspective Optimized PwrSoC t 0 t 1 t 2 i G 3.3 5V DCDC DCDC 40 nm V 1.2 V DCDC DCDC v GS i SD v int known switching structure t0 t1 t2 ig v SD vgs VIN VDR_PMOS VDR_NMOS vsg_pmos ipmos inmos vgs_nmos SHIGH vsd_pmos L vint SLOW il COUT vout vint vsd psd Understanding the origin of the losses p SD isd Defined Si tech PAGE 10

11 IC perspective Optimized PwrSoC V IN L 3.3 5V DCDC DCDC V 1.2 V DCDC V IN 40 nm DCDC VDR_PMOS VDR_NMOS VIN I G known switching structure DUT Simple sim circuit to obtain needed energy calculations I VIN LOAD vsg_pmos ipmos inmos vgs_nmos SHIGH vsd_pmos L vint SLOW v int t0 t1 t2 ig ILOAD il COUT vout IG DUT vint vgs isd vint vsd psd vsd DUT RG v SD VIN L S ILOAD DUT R G Understanding the origin of the losses S I LOAD Defined Si tech PAGE 11

12 IC perspective S OUT3 i,j Optimized PwrSoC Y i1,j1 S OUT2 i,j 3.3 5V DCDC DCDC 40 nm V 1.2 V DCDC DCDC Passives models Y i,j1 S OUT4 i,j SOUT3 i,j Yi1,j1 SOUT2 i,j y(w, I) Simple sim circuit to obtain needed energy calculations Yi,j1 SOUT4 i,j Ij1 y(w, I) Yi1,j Y i1,j VIN VIN I L Ij wi SOUT1 i,j w wi1 I j1 known switching structure VDR_PMOS VDR_NMOS VIN vsg_pmos ipmos inmos vgs_nmos SHIGH vsd_pmos L vint SLOW I t0 t1 t2 ILOAD ig il COUT vout IG DUT vint I j vgs isd vint vsd psd vsd DUT RG S ILOAD Understanding the origin of the losses Accurate and fast computational models w i S OUT1 i,j w w i1 Defined Si tech PAGE 12 Control

13 PowerSoC perspective Optimized PwrSoC 3.3 5V DCDC DCDC V 1.2 V DCDC CAD optimization tool 40 nm DCDC Passives models Yi1,j1 Simple sim circuit to obtain needed energy calculations known switching structure VDR_PMOS VDR_NMOS VIN vsg_pmos ipmos inmos vgs_nmos SHIGH vsd_pmos L vint SLOW t0 t1 t2 ILOAD ig il COUT vout IG DUT vint VIN vgs isd vint vsd psd vsd Ij1 DUT RG Yi,j1 SOUT4 i,j VIN I L S Ij SOUT3 i,j ILOAD wi SOUT2 i,j y(w, I) SOUT1 i,j w Yi1,j Understanding the origin of the losses wi1 Accurate and fast computational models Defined Si tech PAGE 13 Control

14 PowerSoC perspective Optimized PwrSoC 3.3 5V DCDC DCDC V 1.2 V DCDC CAD optimization tool 40 nm DCDC Passives models Simple sim circuit to obtain needed energy calculations Yi,j1 SOUT4 i,j Ij1 SOUT3 i,j Yi1,j1 SOUT2 i,j y(w, I) Yi1,j Optimal design: SI, L, C, f SW, area distribution VIN VIN I L Ij wi SOUT1 i,j w wi1 known switching structure IG DUT t0 t1 t2 ILOAD ig vint vgs isd vsd DUT RG S ILOAD Accurate and fast computational models VDR_PMOS VDR_NMOS VIN vsg_pmos ipmos inmos vgs_nmos SHIGH vsd_pmos L vint SLOW il COUT vout vint vsd psd Understanding the origin of the losses Defined Si tech PAGE 14 Control

15 PowerSoC perspective Optimized PwrSoC 3.3 5V DCDC DCDC V 1.2 V DCDC CAD optimization tool 40 nm DCDC Passives models Simple sim circuit to obtain needed energy calculations Yi,j1 SOUT4 i,j Ij1 SOUT3 i,j Yi1,j1 SOUT2 i,j y(w, I) Yi1,j Optimal design: SI, L, C, f SW, area distribution VIN VIN I L Ij wi SOUT1 i,j w wi1 known switching structure IG DUT t0 t1 t2 ILOAD ig vint vgs isd vsd DUT RG S ILOAD Accurate and fast computational models VDR_PMOS VDR_NMOS VIN vsg_pmos ipmos inmos vgs_nmos SHIGH vsd_pmos L vint SLOW il COUT vout vint vsd psd Understanding the origin of the losses Defined Si tech PAGE 15 Control

16 PowerSoC design flow : Designer options Specification Technology Topology Control Inductor Semiconductors Capacitors 1phase Buck converter 2phase Buck converter 2phase coupled Buck converter Voltage mode Current mode Ripplebased V RAMP V REF H V (s) v OUT Optional Ripplebased Rippled signal Loadsteps I o Power Stage v OUT i L v OUT i L v OUT Modes of operation Modulation strategy CCM DCM Lightload mode Constant frequency Constant ontime Continuous Conduction Mode Discontinuous Conduction Mode BURST Mode v o Δv o i L PAGE 16

17 PowerSoC design flow : Designer options Specification Technology Topology Control Inductor Semiconductors v OUT Modes of operation Modulation strategy Continuous Cond. Mode Discontinuous Cond. Mode Lightload mode Constant frequency Constant ontime Continuous Conduction Mode i L v OUT Discontinuous Conduction Mode Capacitors i L BURST Mode v OUT i L PAGE 17

18 PAGE 18 CAD GUI

H V (s) v OUT Optional Rippled signal Power

Operating Mode Continuous Conduction Mode i

19 CAD GUI Capacitors 5 V Static Spec 1.2V 280mA Regulator Constraints V RAMP V REF H V (s) v OUT Optional Rippled signal Power Stage Load Design Topology Inductor v OUT Operating Mode Continuous Conduction Mode i L v OUT Discontinuous Conduction Mode Semiconductors i L BURST Mode v OUT i L Analysis of the system Total Area Dynamic Spec I o v o Δv o PAGE 19

20 CAD GUI Capacitors 5 V Static Spec 1.2V Regulator Constraints Load Design Topology 280mA Inductor v OUT Operating Mode Continuous Conduction Mode i L v OUT Discontinuous Conduction Mode Semiconductors i L BURST Mode v OUT i L Analysis of the system Total Area Dynamic Spec I o v o Δv o PAGE 20

21 Design Flow Specification Designer options Technology Topology Control Modes of operation Design tools Models Design space Optimization Optimization of Losses Final design PAGE 21

22 Design Flow Specification Technology Topology Control Modes of operation Models Design space Voltage mode control Current mode control Ripplebased control Optimization of Losses Final design PAGE 22

Ripple based Control V 2 I c control Simplis simulation OPTIMAL RESPONSE!

Voltage reference Complex analysis, SIMPLE implementation Ref [V] Control [V] v o [V] Del

23 Ripple based Control V 2 I c control Simplis simulation OPTIMAL RESPONSE!! Duty [V] I o [A] I L [A] Very fast even with low ESR caps Feedforward of: Output current Voltage reference Complex analysis, SIMPLE implementation Ref [V] Control [V] v o [V] Del Viejo, M.; Alou, P.; Oliver, J.A.; Garcia, O.; Cobos, J.A., "V 2 IC control: A novel control technique with very fast response under load and voltage steps," Applied Power Electronics Conference and Exposition (APEC), 2011 TwentySixth Annual IEEE, vol., no., pp.231,237, 611 March 2011 PAGE 23

24 PAGE 24 EASY implementation

25 PAGE 25 V 1 concept

26 Control: V 2 I c Load step 4A 0A Load step 0A 4A V 2 I c control DVS 1.2V 2.2V DVS 2.2V 1.2V Simplis simulation Line step 5V 3.3V Duty [V] V in [V] 5V 3.3V 5V 2.2V v o [V] V ref [V] 1.2V 1.2V i L [A] 4A 4A i o [A] 0A ALMOST OPTIMAL RESPONSES IN ALL TRANSIENTS PAGE 26

27 Design Flow Specification Technology Topology Control Modes of operation Models Design space Capacitor model Inductor model MOSFET model Switched models of converter Optimization of Small signal model of converter Losses Final design PAGE 27

28 I DRV V DD V SS DUT Models: MOSFETS Optimization requires Low computational cost model based on accurate CADENCE simulations, mapping the whole design space I Load I DSnom = 200 ma I DSmax Y i1,j1 Y INT i,j V X Y i,j1 y(x 1, x 2 ) Y i1,j x 2j1 Y i,j x 1i1 I DSmin x 2 x 2j x 1i x 1 (w Pmin, w Nmin ) (w Pmax, w Nmax ) w Pnom =10.6mm w Nnom =10.8mm Svikovic, V.; Cortes, J. ; Alou, P. ; Oliver, J. ; Cobos, J.A. ; Maderbacher, G. ; Sandner, C. EnergyBased switches losses model for the optimization of PwrSoC buck converter, COMPEL 2014 PAGE 28

2 TurnOff Transient Energy of PMOS Example: HISide Circuit waveform to quickly calculate losses in the optimization algorithm E turnoff [nj] 1.

8 0.6 0.4 0.2 0.62 nj 0.78 nj 0.16 nj 0 I 0 I 1 0.2 0 100 200 300 400 500 600 700 800 I DS [ma] P TurnOFF P TurnON P Driver = 7.86 mw = 1.6 mw = 6.

29 2 TurnOff Transient Energy of PMOS Example: HISide Circuit waveform to quickly calculate losses in the optimization algorithm E turnoff [nj] E DRIVER PMOS Switching Losses E TurnON E TurnOFF w [mm] f SW = 10 MHz I DS [ma] E LOSSES [nj] nj 0.78 nj 0.16 nj 0 I 0 I I DS [ma] P TurnOFF P TurnON P Driver = 7.86 mw = 1.6 mw = 6.25 mw I 1 I PMOSrms = ma R PMOSon P COND = 410 mω = 14.2 mw i PMOS [ma] I t/t SW PAGE 29

30 Inductor Optimization fixed dimensions degrees of freedom 220nH F = 10 MHz L c H c W cu W c PAGE 30

31 Models: Inductors Racetrack inductor Geometry design Core inductance Self inductance of wires Losses calculation Copper losses Hysteresis losses Eddy current losses T.M. Andersen, C.M. Zingerli, F. Krismer, J.W. Kolar, Ningning Wang and C.O. Mathuna, "Modeling and Pareto Optimization of Microfabricated Inductors for Power Supply on Chip," Power Electronics, IEEE Transactions on, vol.28, no.9, pp.4422,4430, Sept Symbol N t w c t c s c w c t c l d h d w d l Description Number of turns Winding width Winding thickness Winding spacing Core width Core thickness Core length Device height Device width Device length PAGE 31

Models: Inductors Geometry design Geometry design Core inductance Self inductance of wires Core inductance L core = 2 μ oμ c N 2 A c l m = μ oμ c N 2 c t c l c w d h Selfinductance of wires L t,self

32 Models: Inductors Geometry design Geometry design Core inductance Self inductance of wires Core inductance L core = 2 μ oμ c N 2 A c l m = μ oμ c N 2 c t c l c w d h Selfinductance of wires L t,self 0. 2c l ln 2c l t w t t 1 2 Inductance of coreless spirals L t,spiral μ on 2 d avg c l ln p 0. 2p 2 Average diameter Fill factor d i d o d avg = d o d i 2 p = d o d i d o d i L = L core L t,self L t,spiral PAGE 32

DIODE Capacitors Models: Capacitors Spice Model y = 0.0003x 0.4266 R 2 = 0.8047 PICS3 Std design 10 B terminal PICS C A terminal D C BOT C TOP ESR (Ohm) 1 R SUB 0.1 0.01 1.00E11 1.00E10 1.00E09 1.

33 DIODE Capacitors Models: Capacitors Spice Model y = x R 2 = PICS3 Std design 10 B terminal PICS C A terminal D C BOT C TOP ESR (Ohm) 1 R SUB E E E E E E E05 Capacitor (F) Parameters min typical max Pits Capacitance [nf/mm 2 ] Planar capacitance [nf/mm 2 ] Metal M1 to metal M2 [pf/mm 2 ] Metal M1 to substrate [pf/mm 2 ] Parameters BV [V] 30 IS [A] 1.83e16*perimeter 2.9e15 * surface IBVL 2 * IS M 0.3 CJ0 [pf/mm 2 ] 10 EG [ev] 1.11 Defined by PAGE 33

34 Design space Specification Technology Topology Control Modes of operation Models Design space LC constraints Effect of Modulation DELAY Closing the loop Optimization of Losses Final design PAGE 34

ripple Modulation delays Filter resonance in Voltage mode i L Δv o G vd f res 1 5 f sw t d I o V ref v o v o

35 Design space: constraints BUCK CONVERTER Design decisions: Output capacitor Inductor filter Switching frequency Control Singlephase / Multiphase Constraints Load transients Voltage reference tracking Static ripple Modulation delays Filter resonance in Voltage mode i L Δv o G vd f res 1 5 f sw t d I o V ref v o v o Δv o t s Area to close the loop v o ~cte L C t s ~cte LC v o ~cte 1 1 f sw LC t d ~cte 1 f sw f res ~cte f sw 1 LC PAGE 35

36 Output capacitor Design space: load transient Constraints Load transients Voltage reference tracking Static ripple Modulation delays Filter resonance in Voltage mode m I o i L v o,load ~cte L C v o Δv o,load Design space v min o,load = 1 2C C ESR 2 m I 2 o m Load transient Loading m = V in v o L Unloading m = v o L Inductance PAGE 36

37 Output capacitor Design space: voltage reference tracking Constraints Load transients Voltage reference tracking Static ripple Modulation delays Filter resonance in Voltage mode i L t s ~cte LC V ref v o2 =V in d 2 t s Voltage reference tracking Design space v o1 =V in d 1 t s min = 2 L C 1 d m (1 d m ) d 1 2 Design space Load transient d m = d 1 d 2 2 d = d 2 d 1 Inductance PAGE 37

38 Output capacitor Design space: static ripple Constraints Load transients Voltage reference tracking Static ripple Modulation delays Filter resonance in Voltage mode Δv o v o,pp ~cte 1 2 f sw 1 LC Voltage reference tracking v min o,pp i L i L = V in v o L 1 8Cf sw ESR d f sw Design Design space space Load transient Static output voltage ripple Inductance PAGE 38

39 Output capacitor Output capacitor Design space: static ripple Constraints Load transients Voltage reference tracking Static ripple Modulation delays Filter resonance in Voltage mode What if there is no solution in the design space?? To comply with voltage ripple Voltage reference tracking To comply with voltage tracking Static output voltage ripple Load transient Voltage reference tracking Inductance The solution is to decrease output voltage ripple by other means Design space Load transient Static output voltage ripple Use multiphase topology Increase switching frequency Inductance PAGE 39

40 Design Flow GOAL Technology Topology Control Modes of operation Models Design space Optimization of Losses Final design Technology Topology Control Modes of operation Inductor design Capacitor design MOSFETs sizing PAGE 40

41 Specifications Control specs Peak current mode ΔB < f sw /7 CCM/DCM/Burst PM = 60º f sw,min = 1MHz f sw,max = 30MHz Input specs Static V in = 5V ΔV in,max = 250mV Dynamic ΔV in,max = 600mV ΔV in,trans = 250mV@0ns Output specs Static Dynamic V out = 1.2V ΔV out,max = 144mV ΔV out,max = 60mV Δi out,trans = 300mA@2μs I out,typical = 280mA Δi out,trans = 50mA@2ns I out,max = 500mA I out,min = 50mA Common for pmos and nmos MOSFET specs w min = 2mm Dead time p n = 1ns w max = 30mm Dead time n p= 1ns V gs = 5V I g, max = 80mA Inductor specs L max = 2μH ΔI L,max = 500mA R par =10mΩ L par =100pH Capacitor specs C min = 50nF σ cap,ensity = 220nF/mm 2 R par =10mΩ L par =100pH PAGE 41

42 CAD GUI Capacitors 5 V Static Spec 1.2V Regulator Constraints Load Design Topology 280mA Inductor v OUT Operating Mode Continuous Conduction Mode i L v OUT Discontinuous Conduction Mode Semiconductors i L BURST Mode v OUT i L Results of the optimization process Analysis of the system Total Area Dynamic Spec 175 nf / 245 nf 201 nh 11.7 MHz I o 12 mm 14.1 mm 9.9 mm 2 v o Δv o PAGE 42

43 Results (& what if analysis) Ideal MOSFETs Real Inductor Real MOSFETs Ideal Inductor Real MOSFETs Inductor with Cu losses PAGE 43

44 Real MOSFETs Real Inductor Results (& what if analysis) PAGE 44

45 Results (& what if analysis) Optimal solution: Losses Breakdown efficiency comparison PAGE 45

Summary Technology impact: CMOS improvement:

for your specs: Load steps Voltage or reference

46 Summary Technology impact: CMOS improvement: optimum f sw Inductor technology improvement: : optimum f sw Models, algorithms and tools to OPTIMIZE your design Calculate the Design space for your specs: Load steps Voltage or reference steps V out ripple Multiphase, modulation delays, PAGE 46

Acknowledgement PowerSwipe Partners: Tyndall National Institute / University College Cork, Ireland Infineon Technologies AG, Germany Infineon Technologies Austria AG, Austria IPDiA, France

47 Acknowledgement PowerSwipe Partners: Tyndall National Institute / University College Cork, Ireland Infineon Technologies AG, Germany Infineon Technologies Austria AG, Austria IPDiA, France Universidad Politécnica de Madrid (UPM), Spain Robert Bosch GmbH, Germany Université de Lyon, Claude Bernard (UCBL), Lyon This work is funded by: EU FP7ICT20118 PowerSWIPE Project no.: PAGE 47

CAD Tool for the optimization of Power Converters on Chip

CAD Tool for the optimization of Power Converters on Chip Jesús A. Oliver, Pedro Alou and José A. Cobos Universidad Politécnica de Madrid 2 The need of an integrated multi-domain tool μc 3.4mm 16V-6V CHVin