LSP5504. PWM Control 2A Step-Down Converter. Applications. General Description. Features LSP5504. Typical Application Circuit

Transcription

1 Applications Cellular Phones PC Motherboard LCD Monitor Graphic Card DVD-Video Player Telecom Equipment ADSL Modem Networking power supply Microprocessor core supply Printer and other Peripheral Equipment Features Input voltage: 3.6V to 18V. Output voltage: 0.8V to VCC. Duty ratio: 0% to 100% PWM control Oscillation frequency: 300KHz typ. Soft-start, Current limit, Enable function Thermal Shutdown function SOP-8L Package. General Description The LSP5504 is high efficiency, simple to use, 2A step-down regulator flexible enough to be optimized for a variety of applications. LSP5504 provides low-ripple power, high efficiency, and excellent transient characteristics. The PWM control circuit is able to vary the duty ratio linearly from 0 up to 100%. This converter also contains an error amplifier circuit as well as a soft-start circuit that prevents overshoot at startup. An enable function, an over current protect function and a short circuit protect function are built inside, and when OCP or SCP happens, the operation frequency will be reduced from 300KHz to 50KHz. Also, an internal compensation block is built in to minimum external component count. With the addition of an internal buffer driver, a coil, capacitors, and resistors connected externally, these ICs can function as step-down switching regulators. They serve as ideal power supply units for portable devices when coupled with the SOP-8L mini-package, providing such outstanding features as low current consumption. Since this converter can accommodate an input voltage up to 18V, it is also suitable for the operation via an AC adapter. Typical Application Circuit Vout=5V/2A LSP5504 1/14 Ver.1.2

2 Ordering Information LSP5504 X X X X Package: S: SOP-8L Output Voltage: Blank: Adj Packing: A: Tape & Real Temperature Grade: C: -20 ~ +85 C Pin Assignment Top View FB 1 8 VSS EN OCSET 2 3 SOP-8L 7 6 VSS OUTPUT VCC 4 5 OUTPUT Pin Description Pin NO. Pin Name Pin Description 1 FB Feedback Pin 2 EN Enable Input Pin. H: Normal operation. L: All circuits deactivated. 3 OCSET Add an external resistor to set max output current 4 VCC IC power supply pin 5,6 OUTPUT Switch pin. Connect external inductor here. Minimize trace area at this pin to reduce EMI. 7,8 VSS GND pin 2/14 Ver.1.2

3 Functional Block Diagram Output Buffer Absolute Maximum Ratings Parameter Value Unit VCC Pin Voltage, V CC V SS -0.3 to V SS +20 V Feedback Pin Voltage, V FB V SS -0.3 to V CC V EN Pin Voltage, V EN V SS -0.3 to V IN V Switch Pin Voltage, V OUTPUT V SS -0.3 to V IN V Power Dissipation, P D Internally limited mw Operating Range, T OP -20 to 85 C Storage Temperature Range, T STG -40 to +150 C Note: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect device reliability. 3/14 Ver.1.2

4 Electrical Characteristics (V IN = 12V, T A = 25 C, unless otherwise specified.) Parameter Symbol Test Conditions Min. Typ. Max. Unit Input Voltage V IN V Feedback Voltage V FB I OUT = 0.1A V Feedback Bias Current I FB I OUT = 0.1A µa Switch Current I SW 3.5 A Current Consumption During Power Off I SSS V EN = 0 10 µa Line Regulation V OUT / V OUT V IN =5V~18V, I OUT = 0.3A 1 2 % Load Regulation V OUT / V OUT I OUT = 0.1A~0.3A % Oscillation Frequency fosc Measure waveform at SW pin KHz Frequency of Current Limit or Short Circuit Protect fosc1 Measure waveform at SW pin KHz V SH Evaluate oscillation at SW pin 2.0 Enable Pin Input Voltage V SL Evaluate oscillation stop at SW pin 0.8 V Enable Pin Input Leakage Current I SH 20 I SL -10 µa OCSET Pin Bias Current I OCSET µa Soft-Start Time t SS ms Internal MOSFET Rdson R dson V IN =5V, V FB = V IN =12V, V FB = mω Efficiency EFFI V IN =12V, V OUT =5V, I OUT = 2A 91 % Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case θ JA 65 C/W θ JC 20 C/W Over temperature shutdown TSD 150 C Over temperature shutdown Hysteresis THYS 25 C 4/14 Ver.1.2

5 Application Description CON1 U1 L1 CON3 CON1_1 C1 470uF/25V R2 100K C3 C4 R2 4.7K C5 NC OUTPUT VCC OUTPUT LSP5504 OCSET FB EN VSS VSS 22uH D1 C6 NC R3 31K R4 C7 NC C2 470uF/ 6.3V C8 470uF/ 6.3V CON1_1 0.1uF 0.1uF 10K CON2 CON4 CON1_1 CON1_1 1. PWM Control The LSP5504 is a DC/DC converter that employs a pulse-width modulation (PWM) system. The pulse width varies in a range from 0 to 100%, according to the load current. The ripple voltage produced by the switching can easily be removed through a filter because the switching frequency remains constant. Thus, the converter provides a low-ripple power over broad ranges of input voltage and load current. 2. Under Voltage Lockout The under voltage lockout circuit of the LSP5504 will turn off PWM-Switched control circuit when the supply voltage drops below 3.3V. Normal operation resumes once VCC rises above 3.5V. 3. Output Voltage Programming Output voltage can be set by a resistor divider network. In this application circuit, a designer can calculate the Vout as below equation: R V OUT = A R B The resistor should be large enough to avoid power loss in feedback voltage divider that combination of R A and R B. And the lower resistor values minimize noise pickup in the sensitive feedback pin. Designer can reference the values of Table 1, to initial your design. Vout is determined by the two feedback resistor And the Vout=VFB*(1+R3/R4)=0.8V*(1+R3/R4) the feedback resistor table for some common output voltage is list below: Vout 0.8V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V R3 (KΩ) R4(KΩ) open the feed forward capacitor C6 The feed forward capacitor is the capacitor which connects the feedback resistor R3 in parallel, referring to the schematic circuit in page 6; the C6 range is 100pF~1nF; And you had better layout C6 s position and add C6 to add up the loop stability when you find the switching waveform swing left and right. 5/14 Ver.1.2

6 3.1 Inductor selection To Buck DC/DC, the inductor s formula is listed below: L Vout*(Vin min-vout)/(vin*fsw*0.2*iload max) The below inductor selection table is for some common output voltage application: Vin=5V Vout 0.8V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V N/A L 5uH 6.8uH 6.8uH 6.8uH 10uH 10uH 10uH N/A Vin=12V Vout 0.8V 1.0 V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V L 5uH 6.8uH 6.8uH 10uH 10uH 15uH 15uH 22uH Vin=18V Vout 0.8V 1.0 V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V L 5uH 6.8uH 6.8uH 10uH 10uH 15uH 22uH 22uH 3.2 Output capacitor selection The output capacitor type must be Aluminum Electrolytic Capacitor or Tantalum Capacitors, not MLCC capacitor; The capacitor voltage rating should be at least 1.5 times greater than the output voltage, and often much higher voltage ratings are needed to satisfy the low ESR requirements needed for low output ripple voltage. Output capacitor s ESR Vripple/(2* Iload min) For typical Vout 5V,we use 470uF/10V Aluminum Electrolytic Capacitor 3.3 Input capacitor selection This capacitor should be located close to the IC using short leads and the voltage rating should be approximately 1.5 times the maximum input voltage. And Input capacitor s RMS current is calculated by the below formula: Symbol δ IPK Im IL Calculation TON TON +TOFF Iload max + Iload min Iload max - Iload min 2 L LOAD(min) IIN(rms) 6/14 Ver.1.2

7 3.4 R1 selection R1 is used for limit the maximum inductor peak current in order to realize the OCP function; R1 s formula is listed below Ipeak Rds(on) =Iocset R1 Ipeak is the maximum inductor peak current, in general, Ipeak=1.1* Iload max and we define Ipeak=3.5A for LSP5504, Iocset=100uA for LSP5504, the below R1 table for common combination with Vin and Vout 3.5 delay startup R2 C4 selection The R2 and C4 connected with LSP5504 s PIN2 constitute the integrator circuit which realize the delay startup function. The voltage of CEN formula: VEN=1.3V for LSP5504 t=r2*c4 so for R2=100K C4=0.1uF delay time=1.147ms 4. Design Example 4.1 the target design specification Input Power Vin max = +12V; Vin min = +12V Regulated Output Power Vout = + 5V; Iload max = 2.0A; Iload min = 0.2 A Output Ripple Voltage Vripple 50 mv peak-to-peak Output Voltage Load Regulation 1% (1/2 full load to full load) Efficiency 91% minimum at full load Switching Frequency f = 300KHz ± 15 % 7/14 Ver.1.2

8 4.2 Calculating and Components Selection Calculation Formula Select Condition Component spec. R3 = R4 ( VOUT 1) 470Ω R4 5KΩ VRE R4=1.3KΩ; R3=6.8KΩ Lmin (Vin min - VOUT) Vout Vin min*fsw*0.2*iload max L(min) 22µH Irms IPK = 2.2 A 22µH/2.5A ESR= VRIPPLE 2 ILOAD(min) VWVDC 1.5 VOUT ESR 125mΩ VWVDC 7.5V 470uF/10V IIN(rms)= VWVDC 1.5 VIN(max) Iripple IIN(rms) 1.29 A VWVDC 18V 470uF/25V 4.3 BOM Item Part Number MFG/Dist. Description Value Quan 8/14 Ver.1.2

9 4.4 Layout the actual Layout Layout suggestion Cin and Cout should be used over 220uF high frequency low ESR Aluminum Electrolytic Capacitor or Tantalum Capacitors, not MLCC capacitor. It is recommended to add a 0.1uF MLCC decoupling capacitor (Decoupling capacitor must be connected by the same copper). Place the Cin and Cout capacitor as close as possible to the IC. Care should be taken to minimize the loop area formed by the Cin capacitor connections, the IN pin, and the ground pin. It is suggested to use VIAs around Cin negative pole from top side to bottom side OUT PIN (PIN5/6) s copper should be large enough to reduce the thermal resistance, which helps to distribute the heat of the internal PMOSFET and reduce LSP5504 s temperature. Inductor should be close to OUT PIN, to avoid the high frequency oscillation caused by inductor s drain capacitance and trace s distributed capacitance. 9/14 Ver.1.2

10 minimize the output current loop area( surround by OUT pin, L1, Cout and GND) Connect the VOUT trace to the FB pin using the resistor divider network to set the output voltage. Do not route this trace too close to the SW trace. Due to the size of the IC package and the device pin-out, the trace may need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if a trace under the output capacitor is not desired. And it is better to make the sampling point is the maximum current point of load. The sampling line should not overflow large current The copper trace s width should be large enough for the large current path, 40 mil trace per 1A. Such as the path from Vin to LSP5504 s PIN4; the path from LSP5504 s PIN5/6 to L1; the path from L1 to Vout; It should add VIAs from LSP5504 s PIN7/8 to the bottom GND It should avoid to layout signal or other power line under the inductor L1, and avoid to layout GND trace under the inductor L1,It is better to keep 15 mil distance around SW s trace. 4.6 Demo board test data and curve(vout=5v) quiescent current I Q # # AVG load regulation / line regulation I L % VFB I L Efficiency curve eff V V /14 Ver.1.2

11 Typical Characteristics 0.83 V IN vs. V FB (V OUT =3.3V, IOUT = 0.2A) 350 V IN vs. Frequency (V OUT =3.3V, I OUT = 0.2A) VFB (V) FOSC (khz) V IN (V) V IN (V) 3.50 Line Regulation (V OUT =3.3V, IOUT = 0.2A) 3.35 Load Regulation (VIN =12V) V OUT (V) V OUT (V ) V IN (V) I OUT (A) 100% Efficiency (V IN =12V, V OUT =3.3V) 90% Efficiency (%) 80% 70% 60% 50% I OUT (A) 11/14 Ver.1.2

12 Typical Characteristics (Continued) Vout Ripple Vout Ripple ( Vin =12V; Vout = 3.3V; Iout = 0.1A ) ( Vin = 12V; Vout = 3.3V; Iout = 2A ) 12/14 Ver.1.2

13 Test Circuit 1) Enable Function Test 2) Feedback Function Test 3) Operation Function Test Marking Information 13/14 Ver.1.2

14 Package Information SOP-8L: Dimensions In Millimeters Dimensions In Inches Symbol Min. Nom. Max. Min. Nom. Max. A A A B C D E e 1.27 BSC BSC H L θ 0 ο 8 ο 0 ο 8 ο 14/14 Ver.1.2