2015 International Future Energy Challenge Topic B: Battery Energy Storage with an Inverter That Mimics Synchronous Generators. Qualification Report

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1 2015 International Future Energy Challenge Topic B: Battery Energy Storage with an Inverter That Mimics Synchronous Generators Qualification Report Team members: Sabahudin Lalic, David Hooper, Nerian Kulla, Kevin Bisson, and Shawn Maxwell University of Connecticut Department of Electrical and Computer Engineering January 15, 2015

2 1. Progress In the past several months, the UCONN IFEC team has made much important advancement towards the goal of designing a battery energy storage system with an inverter that mimics a synchronous generator. We have chosen a topology, simulated the chosen topology, chosen our parts, and gotten preliminary test results shown in Table. 1. and Fig. 1. Table. 1 UCONN team accomplishment during fall semester. Category List of project activities Progress Back-End Converter Topology: full bridge phase shift converter Front-End Inverter Topology: full bridge LCL inverter Hardware Transformer design and implementation DSP control board design and implementation Power stage schematic design Power stage PCB layout In progress Control Board Simulation DSP GPIO coding and PWM generation coding DSP ADC reading and scaling coding Buck converter operation and control Buck converter close loop control with C block Full bridge step-up/down converter simulation DC-AC inverter standalone operation simulation System level power flow simulation (charging mode) System level power flow simulation (discharging mode) System level power flow simulation (mimic generator) Plan Plan Plan Fig. 1. Picture during test of the prototype DC-AC inverter stand alone mode.

3 2. Design and Parts Selection 2.1 Specifications Table. II shows a few of the key specifications we have focused on throughout designing the circuit and choosing the key parts in our circuit. In addition to the specifications, our circuit will also mimic a synchronous generator by adopting an advanced grid-connected inverter algorithm. Table. II Key Specifications Dimensions <1 Liter Battery Input Voltage 48V DC Weight <1 kg Output Power Rating 500 VA continuous Manufacturing Cost <US$0.5/W Output Voltage 230V AC rms Overall Energy Efficiency >95% Output Frequency 50 Hz 2.2 Topology Selection and Simulation Results Many considerations had to go into the design of the power stage for this circuitry. First, the design can be broken down into two parts: a front-end (AC-DC) converter and a back-end (DC- DC) converter. Each converter needs to be highly efficient to meet the aforementioned specifications and requirements. Furthermore, the design needs to be bidirectional as power needs to flow from the battery to the grid and from the grid to the battery. Based on these considerations, we came up with two viable design options for this project, but one clearly stood out above the other Preliminary DC-DC design The preliminary design for this project used a bidirectional buck boost converter for the DC- DC conversion shown in Fig. 2. With this design, when the converter is in buck mode, the top switch is switching, while the bottom switch remains off, and when the converter is in boost mode, the bottom switch is switching, while the top switch remains off. In this manner, we can calculate the duty ratio for each switch based on the different modes. Table. II Duty ratio calculation in preliminary design Mode Equation Result Buck D = V OUT /V IN 0.12 Boost D = V OUT - V IN /V OUT 0.88

4 Table. II summarizes our results for the duty ratios calculated for the preliminary design, where D is the duty ratio, V OUT is the output voltage from the converter, and V IN is the input voltage of the converter. Knowing that 48V must come from and go to the battery, some losses were assumed, and the voltage coming from the AC side was assumed to be around 400V. Using these numbers and the above equations, the resulting duty ratios were calculated. These duty ratios are very high, and would more than likely result in lower-than-required efficiencies. The output filter calculations were made using the buck and boost converter design equations in the following table. Fig. 2. Bidirectional buck-boost converter Preliminary DC-AC design The preliminary design for the AC-DC side of our project used an AC-DC rectifier circuit to convert the AC waveform from the grid to our desired DC waveform. This AC waveform from the grid is higher than what is required at the battery, so the buck-boost converter mentioned above is in buck mode. When the battery is supplying power to the grid, the voltage from the battery is lower than desired at the grid, so the buck-boost converter is in boost mode. The DC voltage in the above schematic represents the DC voltage after the buck-boost converter circuit. The switches in the above circuit are turned on in diagonal pairs. For example, switches Q1 and Q4 would be on at the same time, while Q2 and Q3 would be off.

5 Fig. 3. Bidirectional AC-DC rectifier Final Design The final design has a new topology for the DC-DC conversion while DC-AC side remains the same. The reason for this change was that the duty cycle needed to drive the MOSFET switch for the boost converter on the earlier design was too high. That causes power switching losses which in turn lowers the overall efficiency of our design. That is if we assume that other circuit components behave as ideal elements. In reality there are power losses from other components of the circuit and therefore an even higher duty cycle may be needed. Therefore, we came to the conclusion that the buck-boost converter of the previous design be replaced by a high frequency transformer. The new design is shown in figure 3. The transformer that is incorporated in the new design has a 7:1 ratio and will reduce the voltage in buck mode from 336V DC to 48V DC. When the battery is used as the power source the circuit will operate in boost mode and the voltage will be boosted from 48V DC to 336V DC to the DC link. If we look further in detail, during the buck mode the only the MOSFETs on the left side of figure 3 are active and working two at a time. For half of the cycle MOS1 and MOS4 are ON while for the next half of the cycle the MOS2 and MOS3 are ON. During buck mode the switches on the right hand side remain OFF while the built in diodes act a rectifier bridge. On the other hand, when the circuit is operating in boost mode the switches on the left hand side shown in figure 3 remain OFF while the switches on the switches on the right hand side turn on and of two at a time. For half of the cycle MOS5 and MOS8 are ON while for the next half of the cycle the MOS6 and MOS7 are ON. Turning the switches on and off two at a time is necessary to create an oscillating voltage

6 which in turn will create a change in magnetic flux in the transformer in order to induce current in the secondary. Fig. 4. Final selected topology: full bridge dc-dc converter and inverter Fig. 5. Full bridge converter simulation: step up from 48V to 336V with 1:7 ratio

7 2.3. Transformer design To design a high frequency transformer, we have taken in consideration the parameters shown in Table. III. Pp=500VA Ps=500VA Ip=10.42A Is=1.3A Vp=48V Vs=380V Fsw=100kHz Fig. 6. Prototype 1:7 ratio transformer (a). transformer test waveform (b) Considering the high frequency requirement of this transformer design, we decided to use a ferrite core. Ferrite core materials can handle switching frequencies from 10 khz up to 1 MHz. Since we had available the ETD49 3F3 core and 260/38 Litz-wire (14 AWG) in the lab that can carry up to 22Amps. We decided to use them in our preliminary design. In designing a transformer, we need to consider some constraints such as Maximum flux density, Magnetizing inductance value, Winding area and Winding resistance. The maximum flux density should be less than saturation flux density of the material. The Magnetizing inductance is calculated by (Lm= N^2/Reluctance) and it should be less than differential inductance Ld. Winding area gives the maximum number of turns of the primary and secondary windings. Last but not least the winding resistance affects the efficiency of the transformer and the heat dissipation. Some useful data associated with ETD49 core that we used for design calculations are shown below: Volume of the core Effective crosssectional area of the core Winding are of the core Bsat = 350 mt Mean length of a turn Minimum winding width Saturation flux of the core

8 For the final design, the transformer design can be further improved by using a smaller core such as the ETD44, which is 5 mm shorter in length and width compared to the ETD49. It can handle more than 600VA and it is 24% lighter. Another improvement would be the use of smaller gauge wire windings for the primary and the secondary windings which will further reduce the weight of the transformer and will increase the efficiency of the transformer as a consequence of the primary and secondary windings cross section area being more equal to each other MOSFET selection V DSS (V) I D (A) R DS(on) (Ώ) V GS(TH) (V) Price(UKP) Quantity to to Parts Selection Part Name and description Unit Price ($) Quantity Op-amp (Scaling) Op-amp (Voltage Scaling) Bridge Rectifier MOSFET Power Driver Transducer V, 6VA Transformer V, 10VA Transformer microfarad Electrolytic Capacitor Heatsink Switching Regulator microfarad Electrolytic Capacitor Blocking diode microfarad Electrolytic Capacitor microhenry Inductor

9 2.6. Schematics Fig. 7 Battery current sensing and full bridge converter power stage circuit Fig. 7 shows the back-end dc-dc converter circuit diagram. In addition, battery current measurement circuit is added. There are six terminals (P3, P4, P7, P8, P9, and P10). These terminals are to provide flexible location of transformer and inductor. During test, optimal value and components can be replaced easily. Fig. 8. DC-AC inverter and inverter current sensing circuit. Fig. 8 shows dc-ac inverter schematic. Not only four MOSFETs for full bridge inverter, but also inductor current sensor is added to monitor the output inverter current control.

10 Fig. 9. Gate drive circuit and PWM signals. Fig. 9 shows sample gate drive circuits for main MOSFETs. The same circuits are designed for other 8 MOSFET gate drive circuits. In order to achieve low cost solution, we selected a single gate drive IC using boost strap for high side switch and low side switch gate. ADUM IC provided interconnection between DSP PWM signals and gate drive with signal isolation. NTE1215 is to provide isolated power supply to the gate drive chip. Fig. 10. Grid voltage sensing circuit Fig. 10 shows the ac voltage sensing circuit. 8 voltage divide resistors provide low current consumption and voltage sensing path to the differential op-amp.

11 Fig Pin connector for control board interface. Fig. 11 shows 40 pin connectors. It is a very important interface between DSP control board and power stage board. Main PWM signals and current, voltage sensing signals are transferred. In order to reduce the signal noise, ground lines are inserted in between digital and analog signals. Fig. 12. Dual input sources auxiliary power supply circuit. Fig. 12 shows dual input power auxiliary power supply circuit. In the IFEC requirement, the auxiliary power for control board should be either battery power or grid power. Therefore, two power sources are connected via current blocking diodes.

12 Fig. 13. Schematic of the TMS320F28335 Controller Fig. 13 shows the TI DSP controller. TMS320F2335 is the high performance TI DSP controller chip. Definitely, it has high performance, 32 bit floating arithmetic unit, and many GPIOs. In the initial design stage, we wanted to design the control algorithm with a high performance controller. After validating the control algorithms, we plan to migrate to a reduced TI DSP for low cost solutions.

13 2.7. Additional Simulation PSIM was used in order to simulate inverter side test conditions for stand-alone mode before performing the hardware tests to validate our design. The input voltage to the inverter portion of 20V was chosen as a safe, low power input for testing purposes. The inverter configuration of our design consisting of the full bridge, LC filter, and resistive load is shown below. Fig. 14. Simulation schematic of inverter stage. The output voltage (Vo), output current (I1), and sinusoidal PWM (Vinv) were simulated as shown below. The sinusoidal PWM generated by the full bridge is cleanly filtered by the following low pass LC filter with a cutoff frequency of 2.73 khz in order to remove the much higher 100 khz frequency of the PWM. The resulting output voltage and current thus look like clean 50 Hz sine waves as desired.

14 Fig. 15. Simulation results of inverter stage. 3. Hardware Testing In order to validate the design we have set up a test layout utilizing the power stage from the 2013 UCONN IFEC team s design interfaced with the DSP control board we designed. This allowed us to start testing without having to wait for our board to be fully designed, assembled, and tested. This provided a convenient method to test the intermediary stages of the inverter side operation (right hand side of power board) under open loop and stand-alone conditions just like in the previous simulation in addition to testing proper operation of the DSP control board. The test was performed with the same conditions as the simulations, 20V input across the DC link capacitor and with a 30Ω load resistance.

15 Fig. 16. Hardware testing setup of inverter stage. The results of this test setup in the figure below match our simulation in the previous section. The output voltage and current measured after the LC filtering are clean 50 Hz sinusoids as expected. Fig. 17. Hardware testing results of inverter stage.

16 4. Timeline To ensure the goals of the project are met, a strict time line needs to be planned, followed, and met. IFEC places requirements on each team to submit several documents during the course of the challenge. During fall semester 2014, Prof. Park and IFEC team members had a weekly meeting to discuss about the project progress. Meanwhile, IFEC team presented project outline and basic design with three more ECE faculty members as a senior design review process. At the end of fall semester 2014, all IFEC team members presented to the ECE senior students. During winter break, UCONN IFEC team members added some efforts in simulation, hardware design and test. Now, parts for the proposed design are being selected and ordered. Once we acquire these parts, we will construct the system and begin performance testing this prototype. Table. IV shows the specific task within the given timeline. Table. IV Project timeline 2015 Research items Qualification report Finalize Power Stage PCB Layout Order PCB, parts, and battery FB PS Converter simulation: charging FB PS Converter simulation: discharging Inverter standalone close loop simulation Rectifier close loop simulation Inverter mimic synchronous generator simulation Assemble Power stage board Test Power stage full bridge converter Test Power stage full bridge inverter Test System level sequence control Test Power flow charging mode Test Power flow discharging mode Attend IFEC workshop at APEC Design and order Enclosure Test Basic function in the case Test System level operation in the case Test one-hour long battery Prepare final report Code optimization Prepare IFEC final report