Single-phase Variable Frequency Switch Gear

Transcription

1 Single-phase Variable Frequency Switch Gear Eric Motyl, Leslie Zeman Advisor: Professor Steven Gutschlag Department of Electrical and Computer Engineering Bradley University, Peoria, IL May 13, 2016

2 ABSTRACT A variable frequency drive (VFD) controls the speed of a three-phase alternating current (AC) motor by varying the frequency and voltage supplied to the motor. Variable frequency drives provide energy efficiency benefits to industries that consume large amounts of power operating AC machines. The goal of this project was to construct single-phase variable frequency switch gear (SPVFSG) to produce a switched pulse-width modulated (PWM) waveform corresponding to a user selected motor frequency as an input. The switched PWM signal was applied to gate drive circuitry to amplify the voltage of the switched PWM. To convert direct current (DC) bus voltages to AC voltages, a DC-to-AC voltage inverter was designed using power transistors. The output of gate drive circuitry was used to switch power transistors in the DC-to-AC voltage inverter to drive an inductive load. The voltage and frequency of the inverter output was measured to verify proper Volts/Hertz ratio. i

3 TABLE OF CONTENTS ABSTRACT... i I. INTRODUCTION... 1 A. Problem Background... 1 B. Problem Statement... 1 C. Constraints... 1 II. SYSTEM DESCRIPTION... 2 A. System Block Diagram... 2 B. Subsystem Block Diagram... 2 C. High-level Flowchart... 2 III. METHOD OF SOLUTION... 4 A. PWM Generation Controller Design... 4 Lookup Table Testing Results... 5 B. Gate Drive Circuitry Design Testing Results... 6 C. DC-to-AC Voltage Inverter Design Testing Results... 9 IV. CONCLUSIONS V. REFERENCES ii

4 I. INTRODUCTION A. Problem Background A variable frequency drive (VFD) controls the speed of a three-phase alternating current (AC) motor by varying the frequency and voltage supplied to the motor [1]. When AC motors were introduced in 1888, motor speed control required either varying the magnetic flux or changing the number of poles on the motor. In contrast, direct current (DC) motor speed control could be achieved by inserting an external rheostat into the DC field circuit. In the 1980 s VFD technology became reliable and inexpensive enough to compete with traditional DC motor control [2]. VFDs are important because they provide energy efficiency benefits to industries that consume large amounts of power operating AC machines. Through the use of VFDs, industries can match the speed of the motor driven equipment to the load requirements, rather than running the AC motor at full speed with variable speed mechanical drive trains [1]. Another benefit of using VFDs is the smooth startup of AC motors, which extends equipment life by reducing belt, gear, and bearing wear [3]. The smooth startup of AC motors also reduces shaft fatigue. Previously at Bradley University, a senior project group designed and built a low-voltage singlephase variable frequency AC source using a LabVIEW based cdaq controller from National Instruments to generate a switched pulse-width modulated (PWM) waveform [5]. Alternative software can be used to generate a switched PWM waveform. B. Problem Statement Single-phase variable frequency switch gear that accepts a user-selected input frequency between 1 and 60 Hz and generates an output voltage with a constant Volts/Hertz ratio was designed, built, and tested. C. Constraints Design constraints for the single-phase variable frequency switch gear are shown in Table I. The variable frequency switch gear must provide outputs frequencies in the range of 1-60 Hz. All devices used must be rated for a current of 1.5 A RMS. The switch gear must be safe and must have a grounded neutral. TABLE I: CONSTRAINTS FOR SINGLE-PHASE VARIABLE FREQUENCY SWITCH GEAR Constraints Output Frequencies In the range of 1-60 Hz Hardware Devices rated for a current of 1.5 A RMS Safety Safe to operate Neutral Grounded neutral 1

5 II. SYSTEM DESCRIPTION A. System Block Diagram The system block diagram for the single-phase variable frequency switch gear is shown in Fig. 1. The inputs are a user-selected frequency input between 1 and 60 Hz and a bipolar DC source voltage. The output is a single-phase variable frequency voltage with a constant Volts/Hertz ratio. B. Subsystem Block Diagram The design of the single-phase variable frequency switch gear will be accomplished through the design of its subsystems. A subsystem block diagram for the overall system is shown in Fig. 2. A PWM generation controller accepts a user-selected frequency between 1 and 60 Hz to generate an upper (positive voltage) and a lower (negative voltage) switched PWM waveform. The switched PWM waveforms become the input to gate drive circuitry, which consists of a high side and low side driver that amplifies the voltage and current levels from the PWM generation controller. Two separate signals, an upper and lower half PWM are the outputs of the gate drive circuitry. A DC-to-AC voltage inverter has two DC rails and the upper and lower half PWM signals as its inputs. DC bus voltages are converted to AC voltages and the voltage inverter has a single-phase variable frequency output with a constant Volts/Hertz ratio. C. High-level Flowchart The team is utilizing Atmel Studios to accomplish the task of generating the PWM signal. The software flow chart provided in Fig. 3 shows the program logic used to generate the PWM signal. Pin 1 and pin 2 are the outputs of the Atmega128 microcontroller. The End of Countdown decision block shown in the flow chart signifies the end of each half-cycle of the fully rectified sine wave. +VDC User-selected Frequency Input Variable Frequency Switch Gear Single-phase, Variable Frequency Output with Constant V/Hz Ratio -VDC Fig. 1. System block diagram for the single-phase variable frequency switch gear. 2

6 Gate Drive Circuitry + VDC User-selected Frequency Input PWM Generation Controller Upper half PWM Lower half PWM DC-to-AC Voltage Inverter VDC Fig. 2. Subsystem block diagram for the single-phase variable frequency switch gear. Single-phase, Variable Frequency Output with Constant V/Hz Ratio Start User select sine frequency Sine > Triangle True Set PWM pin 1 HIGH Set PWM pin 2 LOW False Set PWM pin 1 LOW Set PWM pin2 LOW False True End of Count Down True Sine > Triangle True Set PWM pin 2 HIGH Set PWM pin 1 LOW False Set PWM pin 2 LOW Set PWM pin 1 LOW False End of Count Down Fig. 3. High level flowchart for the PWM generation controller. 3

7 Fig. 4. Subsystem block diagram for the PWM generation controller. III. METHOD OF SOLUTION A. PWM Generation Controller 1. Design The PWM generation controller will accept a user selected frequency as an input for the desired output frequency. The input frequency will be entered via the keypad on an Atmega128 development board, and the software will then generate the PWM signal on the pins of the Atmega128 development board. The PWM signal will be the input for the gate drive circuitry. To create the PWM signal, the PWM generation controller will use a comparison between a triangle wave and fully rectified sine wave. The values for the two waves were generated using MATLAB. Both the triangle and sine waveforms are stored in lookup tables in programmable memory on the Atmega128 development board. The two waveforms are then read from programmable memory and compared. If the amplitude of the sine wave is greater than the amplitude of the triangle wave then the PWM signal will be high, but the PWM signal will be low if the opposite is true. Every half cycle the PWM signal will activate alternate output pins to power the high and low side of the power transistors. It is important that the high and low side of power transistors are not on at the same time. The subsystem block diagram shown in Fig. 4 shows the 3 khz triangle wave is compared with the fully rectified sine wave. The comparison generates the switched PWM signal with the varying duty cycle representative of the fully rectified sine wave at the selected frequency. Lookup Table The sine and triangle waveforms were created by using lookup tables based on simulation results. The results were computed using a MATLAB script to generate the appropriate number of values converted to 8 bit hexadecimal values for both waveforms. The purpose of using the lookup table to store the values of the two waveforms is to compare each triangle value with the corresponding sine value. The result of the comparison is the value associated with the PWM signal. The number of total values for the sine wave is 150,000. A fully rectified sine wave only needs half the number of the predetermined values. In the software developed for this project, the maximum number of values required to generate a fully rectified sine wave at 1Hz is 37,500 because the lookup table can be read in ascending and descending order. The lookup table for the triangle wave contains the 50 values calculated using the MATLAB script. 4

8 Amplitude (V) Sine and Triangle Triangle (3kHz) Sine (30Hz) Time (ms) Fig. 5. Excel generated 3 khz triangle wave and 30 Hz sine wave from DAC and Op Amp circuitry output data recorded by an oscilloscope. Fig. 6. Oscilloscope plot of 60 Hz fully rectified sine wave (yellow), 3 khz triangle wave (blue), PWM signal from pin 1 (purple), and PMW signal from pin 2 (green). 2. Testing The generated triangle, sine, and PWM waveforms were displayed on an oscilloscope using a digital-to-analog converter (DAC) to permit viewing the PWM generation in real time. The digital data was first converted to an analog signal by using a DAC, and then an oscilloscope displayed the output of the amplified voltage from the LM741 Op Amp. The ability to view the waveforms generated by the microcontroller provided a means to experimentally verify that the software was performing as designed before applying the PWM outputs to the power electronic components. 3. Results The Excel plot in Fig. 5 was generated using data collected from an oscilloscope on the output of the DAC and Op Amp circuitry. The 3 khz triangle wave and 30 Hz sine wave were displayed as expected. 5

9 A PWM signal was created to control the power electronics. The PWM generation controller was designed to receive a user selected input frequency for the fully rectified sine wave and compare the selected frequency with a constant 3 [khz] triangle wave. The result of the comparison generates a high or low signal in the form of a PWM signal with a varying duty cycle. The fully rectified sine wave is compared with the triangle wave, and the active output pin alternates every half cycle. There is a small delay where both the pins are set low to ensure the power transistors are never on at the same time. B. Gate Drive Circuitry 1. Design Two Avago HCPL-3120 IGBT Gate Drive Optocoupler integrated circuit packages were used to make up high side and low side drivers. A gate drive with an optocoupler was selected to protect the Atmega128 board used for the PWM generation controller from high voltages used (or generated) in the DC-to-AC voltage inverter circuitry. Both driver integrated circuits used the same 18 V power supply. The high-side driver was used to switch the power transistor connected to the positive DC voltage rail in the half H-bridge circuit used for the DC-to-AC voltage inverter. The low-side driver was used to switch the power transistor connected to the negative DC voltage rail in the half H-bridge used for the DC-to-AC voltage inverter. 2. Testing The test circuit shown in Fig. 7 was used to determine whether or not the HCPL-3120 would amplify an input voltage to a usable level for hardware to be used in the DC-to-AC voltage inverter. A resistor value R D was computed to limit the diode current to pin 2 of the HCPL-3120 using a 5 V supply. A TTL input was supplied to pin 3 of the HCPL-3120 by the sync output of a function generator. A DC power supply was used to supply 5 V to pin 2 of the HCPL-3120, and a second DC power supply was used to supply 18 V to pin 8 of the HCPL Pin 5 was tied to ground, and pins 6 and 7 were tied together as suggested in the datasheets. An oscilloscope was used to measure the TTL input at pin 3 and the output of the gate driver at pin Results An oscilloscope was used to measure the TTL input to the gate driver and the HCPL-3120 output for the test circuit in Fig. 7 to display the plot shown in Fig. 8. Since the output of the HCPL-3120 reached 18 V, the test circuit verified that the HCPL-3120 gate driver amplified a 5 V input as expected. 5 V 18 V R D 1 HCPL V o TTL Open Collector Fig. 7. Test circuit used to verify that HCPL-3120 amplified an input voltage as desired with ground reference. 6

10 Fig. 8. Oscilloscope plot for the test circuit in Fig. 7 displaying the TTL input (dark blue) and output of the HCPL (light blue). C. DC-to-AC Voltage Inverter 1. Design A half H-bridge with 2 power transistors and bipolar supplies was designed to drive an inductive load. (The half H-bridge is shown in Fig. 11 and will be discussed later in this report.) The upper half PWM is generated from the output of the high side gate driver and the lower half PWM is generated from the output of the low side gate driver. For initial testing of the DC-to-AC voltage inverter, the low side driver test circuit shown in Fig. 9 was built first. The low side driver uses the output of the HCPL-3120 to provide a gate voltage for an IRF640 MOSFET. The value of the current-limiting diode R D is the same as before. Resistor values for the gate resistor R g and the load resistor R Load were computed to limit the maximum gate and load currents, respectively. 2. Testing For initial testing of the DC-to-AC voltage inverter, a low side driver test circuit shown in Fig. 9 was built. The low side driver used the output of the HCPL-3120 to provide a gate voltage for an IRF640 MOSFET. The gate resistor R g was computed so that the current through pins 6 and 7 of the HCPL-3120 did not exceed 2 A. The sync output of a function generator was used as a TTL input to pin 3 of the HCPL One DC power supply was used to supply 5 V to pin 2 of the HCPL A second DC power supply was used to supply 18 V to pin 8 of the HCPL-3120 and the drain of the IRF640 MOSFET. A wire-wound rheostat was used as an inductive load. A free-wheeling diode was placed across the inductive load to eliminate the sudden voltage spike seen across an inductive load when its supply voltage is suddenly reduced or removed. An oscilloscope was used to measure the TTL input, gate voltage of the IRF640 MOSFET, and load voltage. Since the load being driven is inductive, a turn-off snubber capacitor circuit was added to the low side driver test circuit to eliminate excessive transient over-voltages due to the forward recovery time of the free-wheeling diode across the inductive load. The low side driver test circuit with turn-off snubber capacitor circuit is shown in Fig. 10. Source current when the transistor begins to turn off, fall time for source current, switching period, and minimum duty cycle for which the transistor is on were considered 7

11 when values for R s and C s were computed. An oscilloscope was used to measure the TTL input, gate voltage to the IRF640 MOSFET, and load voltage. 18 V 5 V 18 V RLoad RD 1 HCPL Rg IRF640 TTL Open Collector Fig. 9. Low side driver test circuit with ground reference. 18 V RLoad 5 V 18 V RS RD 1 HCPL Rg IRF640 CS TTL Open Collector Fig. 10. Low side driver test circuit with ground reference and snubber capacitor circuit. 8

12 25 V 5 V R R D 1 HCPL Rg TTL Open Collector C BS R 5 V R D 1 HCPL R S 2 7 Rg C S TTL C BS -25 V Fig. 11. High and low side driver test circuit with bipolar DC supplies. Once testing of a low side driver with ground reference was complete, a test circuit with bipolar supplies to the half H-bridge was built as shown in Fig. 11. Since bipolar supplies were used, a bootstrap capacitor arrangement with a Zener diode was designed. A resistor R was computed such that the current through the resistor was limited enough to supply 18 V to pin 8 of the HCPL-3120 gate drivers without damaging the Zener diodes. One DC power supply was used to supply +25 V to the drain of the upper transistor of the half H-bridge. A second DC power supply was used to supply -25 V to the source of the lower transistor of the half H-bridge. High and low side drivers were tested independently of one another. To test the low side driver, the sync output of a function generator was used for the TTL input to pin 3 of the lower HCPL-3120 in Fig. 9. There was no connection to pin 3 of the upper HCPL To test the high side driver, the TTL input to pin 3 of the lower HCPL-3120 was disconnected and a TTL input was connected to pin 3 of the upper HCPL A wire-wound rheostat was used as an inductive load, and an oscilloscope was used to measure both the gate voltage of the respective IRF640 MOSFET to the driver being tested and the load voltage. 3. Results Figure 12 shows an oscilloscope plot of measurements made for the low side driver test circuit driving an inductive load as shown in Fig. 9. When the output of the HCPL-3120 goes high, the IRF640 MOSFET turns on and the load voltage goes to 0 V. When the output of the HCPL-3120 goes low, the IRF640 MOSFET turns off and the load voltage goes to 18 V as desired. The low side driver test circuit was also switching as desired. However, there was some voltage ripple in the output of the IRF640 output waveform. The test circuit in Fig. 10 with the snubber capacitor circuit was subsequently used to eliminate the voltage ripple. Figure 13 shows an oscilloscope plot of the measurements made for the low 9

13 side driver test circuit with snubber capacitor circuit shown in Fig. 10. It was found that the snubber capacitor circuit eliminates the voltage ripple at the output of the IRF640 MOSFET as desired. Fig. 12. Oscilloscope plot showing TTL input (dark blue), HCPL-3120 output (light blue), and load voltage (purple) for the low side driver test circuit in Fig. 9. Fig. 13. Oscilloscope plot showing TTL input (dark blue), HCPL-3120 output (light blue), and load voltage (purple) for the low side driver test circuit with snubber capacitor circuit in Fig

14 Fig. 14. Oscilloscope plot showing gate voltage (dark blue) and load voltage (light blue) for the low side driver in Fig. 11. Fig. 15. Oscilloscope plot showing gate voltage (dark blue) and load voltage (light blue) for the low side driver in Fig. 11. Figure 14 shows an oscilloscope plot when the circuit in Fig. 11 was tested as a low side driver. When the output of the HCPL-3120 goes high, the lower transistor in the half H-bridge turns on and the load voltage gets pulled to -25 V. When the output of the HCPL-3120 goes low, the lower transistor in the half H-bridge turns off. While the transistor is off, the bootstrap capacitor for the low side driver charges and the gate voltage to the transistor is at -7 V. The bootstrap capacitor arrangement for the low side driver switches the IRF640 MOSFET as desired. Figure 15 shows an oscilloscope plot of the circuit in Fig. 11 when tested as a high side driver. When the output of the HCPL-3120 goes high (approximately 40V), the upper transistor in the half H-bridge turns on and the load voltage gets pulled to 11

15 24 V. When the output of the HCPL-3120 goes low (i.e., the MOSFET gate is tied to its source), the upper transistor in the half H-bridge turns off and the bootstrap capacitor for the high side driver charges. While the upper transistor is off, the gate-to-source voltage for the transistor is 0 V. Testing confirmed the high side driver with bootstrap capacitor arrangement switches the IRF640 MOSFET as desired. IV. CONCLUSIONS A PWM generation controller was developed using software to generate a switched PWM waveform. The software successfully generated a sine and triangle wave from lookup tables and compared them to produce a switched PWM output on two separate output pins of an Atmega128 microcontroller. However, the software does not provide the proposed constant Volts/Hertz ratio. Hardware for gate drive circuitry and DC-to-AC voltage inverter was developed. High and low side drivers were tested independently of each other with bipolar DC supplies of ±25 V. For future work, hardware can be tested using the output of the PWM generation controller as the input to gate drive circuitry. Once the switched PWM based inverter is successfully implemented in hardware, modifications can be made to the hardware to provide for operation at 120 V RMS. The software for the PWM generation controller can also be adjusted to account for the desired constant Volts/Hertz ratio by modifying the switching period of the PWM signal. 12

16 V. REFERENCES [1] Introduction to AC Drives, [Online]. Available: /ITACDS-D.PDF [2] P. Novak. (2009). The Basics of Variable-Frequency Drives, [Online]. Available: [3] C. Hartman. (2014). What is a Variable Frequency Drive, [Online]. Available: [4] M. Spear. (2005). Drive up energy efficiency, [Online]. Available: /2005/489/ [5] K. Lemke and M. Pasternak. (2014). Variable Frequency AC Source, [Online]. Available: projects/proj2014/vfacs/deliverables/lemke_pasternak_project_proposal.pdf 13