An Ultrawideband CMOS Low-Noise Amplifier with Dual-Loop Negative Feedback

Transcription

1 . An Ultrawideband Low-Noise Ampliier with Dual-Loop Negative Feedback Fu Ting, Sumit Bagga and Wouter A. Serdijn, Member, IEEE Abstract A Low-Noise Ampliier or ultrawideband (UWB) applications is presented. Dual-loop negative eedback is avorable, since it can achieve impedance matching and very low noise at the same time, and saves a lot o chip area as no bulky inductors are needed. We employ a nullor and a resistive eedback network and, in order to ulill the noise-igure and power-gain requirements or an UWB receiver, deine the values o the eedback elements involved. The input stage o the nullor is very important or noise, so to optimize the noise perormance, we deine the width and bias current o its input transistor. For the output stage, we have to make sure that the inite output impedance will not aect our impedance matching. To obtain a large bandwidth, we add an intermediate stage and optimize the width o all the transistors involved. Frequency compensation is necessary to ensure the circuit stability. The design is based on TSMC 0.8um technology. Post-layout simulations show that the gain o the LNA is 8.8dB and the bandwidth spans rom 3GHz to 8GHz, the S is below 0dB up to 0GHz and the minimum noise igure is.0db or a 3.3V supply voltage, while consuming 5mA. At the end o this paper, a comparison with previously reported works is given and the advantages and disadvantages o the proposed LNA are discussed. Index Terms dual-loop negative eedback, ultrawideband (UWB), low-noise ampliier (LNA), broadband, impedance matching U I. INTRODUCTION LTRA WIDEBAND (UWB) is one o the most promising approaches to radio communication due to its inherent ability o transmitting data over a wide requency spectrum with high speed and low power. With these advantages, UWB can be used or imaging systems, vehicular and ground-penetrating radars and wireless communication systems. Especially or Personal Area Networks, it can provide wireless link connection at home and in the oice instead o heavy cables with data rates o a ew hundred megabits up to a ew gigabits. UWB communication poses big challenges or low noise ampliier (LNA) design. Since the LNA is the irst active component close to antenna, it must provide suicient low noise behavior not only at one requency but over the whole bandwidth o 7.5GHz. The Manuscript received October, 006. This work was supported in part by the Dutch Freeband Knowledge Impulse Program under Grant DTC.596. Fu Ting is with IMEC-NL, Netherlands. S Bagga and W A Serdijn are with Delt University o Technology, Mekelweg 4, 68 CD Delt, the Netherlands, and with 3UB Innovative Wireless Solutions, phone: , ax: , w.a.serdijn@tudelt.nl. targeted noise igure is around db, which is quite a challenging value compared to other reported works. Power gain is another important parameter; S should be larger than 5dB. Wideband matching is another critical issue: we have to match the LNA to 50Ω, the characteristic impedance o the antenna, so S should below -0dB over the entire requency band. At the same time, we need to ensure that matching network will not destroy the noise perormance and waste chip area. Some LNA designs by other UWB groups in the world employ LC ladder networks. However, an inductor is a costly component since it consumes most o the chip area and also introduces a lot o parasitic resistance that will increase noise. Power consumption is another consideration. Our goal is to limit the current consumption to 5mA. The IC technology we use is TSMC (Taiwan Semiconductor Microelectronics Corp.) 0.8μm. In Section II, we will discuss the dual-loop eedback topology chosen or the LNA and we will deine the eedback network according to our speciications. In Section III a nullor implementation with optimized perormance and relevant simulation results will be presented. A comparison between our work and previously reported wide-band ampliiers will be given in Section IV. II. LNA TOPOLOGY A. Resistive Feedback To achieve accurate input impedance matching, we use two eedback loops: a voltage-to-current (V-I) eedback loop and an indirect current-to-current (I-I) eedback loop, as shown in Fig.. The reason that this topology is called indirect eedback is because the I-I eedback does not sense the output directly, but senses it in an indirect way, by means o a replica o the output current. For the I-I loop, it holds, Io = + (0.) I R For the V-I loop, i I V O i = (0.) R R denotes the V-I eedback resistor and R and R are the current divider resistors. Hence, we can deine the input impedance as: 0

2 . V I I R Ri = = = + R (0.3) I I V R i o / o ( ) i i i By proper selection o the eedback resistors, appropriate values or the input impedance, power gain and noise igure can be designed. For the power gain (S), we can derive Po Io I o R S = = Zl = + Z (0.4) l Pi Ii Vi R R Z l being the load impedance, usually equal to 50 ohms. We need S larger than 5dB in our design. So rom (0.3) and (0.4), we have R 8.8Ω (0.5) 50 = 4.7 (0.6) R R The resistors in the two eedback loops will contribute noise and have inluence on the noise transer. Ater shiting and combining all the noise sources, we arrive at the ollowing expression or the total noise voltage power spectral density: RS RS SVn, eq = 4 ktrs + ( RS + R ) in + ( + ) Vn + 4kT + 4kTR (0.7) v n and i n are the equivalent voltage and current noise sources o the irst stage o the nullor. R s is the source impedance, assumed to be 50 Ω. As we can see rom the equations above, R does not appear in the equation while R and R do. I we decrease the value o R and increase the value o R, the total noise power spectral density will be reduced. So in order to achieve low noise, R has to be chosen as small as possible and R as large as possible. However, some practical limitations arise. For example, i R is too small, the distortion is getting worse, because or the same input signal, more current needs to low through it. This is likely to cause clipping distortion. From a technology point o view, R should be between a ew hundred and a ew kilo ohms. Based on simulation results we choose R =8Ω, R =5.5kΩ and R =kω, so S =5.9dB and NF=0.7dB. B. Capacitive Feedback Instead o using resistive eedback by means o R and R, it is possible to use inductors as I-I eedback elements as long as you keep the current division, set by the ratio o both inductances constant; it will not change the impedance matching and power gain. However, or the same reason the excludes the use o LC ladders, we cannot use inductors as they consume a rather large area. On the other hand, capacitive eedback, thus by means o capacitors, also provides an accurate current division, and does not contribute thermal noise. As a consequence, the noise igure can be made smaller. For capacitive eedback, we have RS SVn, eq = 4 ktrs + ( RS + R ) in + ( + ) Vn + 0 (0.8) Z should have same impedance as R at the highest requency to suppress the noise o the nullor. However, rom calculations and simulations it ollows that the dierence between the resistive and capacitive eedback networks is equivalent to the noise generated by a 0.5 ohm resistor. As a consequence, capacitive eedback does not help much to improve the noise perormance. Moreover, a drawback o capacitive eedback is that it will make the loop gain dependent on the requency. It will also add an additional pole to system transer that has to be compensated or in the subsequent receiver block. Fig.. Dual loop indirect negative-eedback power-to-current ampliier III. NULLOR DESIGN The nullor is a very critical part in our design, since the parameters such as bandwidth, noise igure, distortion etc. will all depend on how good the nullor implementation is. For proper design o the irst stage, its noise perormance is o prime importance. Further, a high gain is required to suppress noise rom other stages. Generally, a nullor at least has two stages, but in order to increase the bandwidth, we can add intermediate stages. Each stage will add gain and a dominant pole, so i more than 3 stages are used, requency compensation will be very diicult, compromising the stability o the circuit. A. Input Stage As we discussed above, or the irst stage, noise is the main consideration. Since its noise igure is inversely proportional to the drain bias current, I d, in order to minimize the noise, I d should be chosen as large as possible. Trading o noise igure or power consumption, we choose 4mA or the drain current o the irst stage. Since the gain o a transistor is proportional to its g m, which, in turn, is proportional to its W/L, W being the width o the transistor and L its length, we choose the minimum eature size 0.8μm or L. In weak inversion, the g m o the transistor no longer depends on its width and as the parasitic capacitances still do, the gain o the transistor reduces again or increasing widths. As a consequence, the NF increases again. As a compromise, we choose W=00μm, yielding a NF as shown in Fig.. 0

3 . 3 Fig.. NF o irst stage as a unction o requency or W=00μm, I d =4mA ) Noise Matching As we can see in Fig., the minimum NF is about.6db. We can introduce another degree o reedom that leads to lower NF. Inductor noise matching is oten applied in narrow band ampliiers, but seldom applied in wide-band negativeeedback ampliier design. Here, we introduce the use o an inductor in series with the input o the irst stage transistor. It will resonate with C gs at a particular requency to keep the NF close to the minimum noise igure, NF min. The value o the inductor is derived rom circuit simulations on the circuit in Fig. 3. The noise igure results are shown in Fig. 4. Based on the simulation results, we choose L =nh. The minimum value o NF is around.3db and is equal to NF min at 8GHz. The average value o NF is below db, so this method improves the noise perormance a lot. ) Current Follower C gd o M introduces an extra pole and will reduce the bandwidth. To reduce its eect, we use a CG (common-gate) stage as current ollower, as shown in Fig. 5. Now C gd is in parallel with Cgs and /g m o the CG stage. We choose its width equal to 00μm and a 3mA bias current. As shown in Fig. 5, we even add an extra CG stage, so two CG stages are ollowing the input stage. This additional increase in output impedance means more output current o irst stage will low to the next stage, M4. Fig. 5. Current ollower ater irst stage Fig. 3. Circuit diagram used or noise simulation o irst stage The inductor using in the simulation is still considered to be ideal. We will replace it with a realistic model later. B. Output Stage For the two (indirect) output stages, like or the input stage, to have a large gain, we use CS stages. The width o each transistor equals 0μm. Their bias currents equal 3mA. Unortunately, the output impedances o both CS stages is not very large. As a consequence, they will load the eedback network and aect the impedance matching. To achieve a high gain and a large output impedance, we use a cascode structure or both output stages as shown in Fig. 6. To increase the loop gain, we add an intermediate CS stage, its width=00μm and bias current=3ma. Fig. 3. NF and NFmin ater inductive noise matching Fig. 6. Cascode structure or output stage 03

4 . 4 C. Frequency Compensation Realization o a phantom zero is an eicient way to do requency compensation. The characteristic property o a phantom zero is that it is not present in the system transer. Phantom zeros are mostly placed near the band edge. Hence, their inluence on the distortion and distortion perormance is only apparent beyond the requency band o interest. The zero is either realized in the eedback network, at the input or at the output. In our case, the load impedance is not well deined and not part o any o the negative-eedback loops. Hence, the ormer two options remain. Since we have three intermediate stages, two phantom zeroes are required. We can make an estimation o how big an inductor or capacitor we need to create a phantom zero. Since the characteristic property o phantom zero is that it appears near the band edge, then to calculate the inductor in series with R, it ollows: R kω ωl= R L= 5nH (0.9) π π 0GHz For the capacitor in parallel with R : C 3F ωc = = πr (0.0) Since this capacitor is very small, the parasitic capacitance o R will act as a phantom zero. 5nH is or an ideal inductor, but rom circuit simulations it ollows we better use a realistic 6nH inductor. The inal circuit diagram incl. biasing and simulation results or S, S and NF are shown in Fig. 7, 8, 9 and 0, respectively. The generated layout is depicted in Fig.. From post-layout simulations it ollows that the bandwidth equals 8GHz, S =8.8dB, S <-0dB@0GHz, NF=[.65,3.0], NF min =.0dB and IIP 3 =-8.dBm@5GHz Fig. 8. S o the circuit o Fig. 7. Fig. 9. S o the circuit o Fig. 7. Fig. 0. NF o the circuit o Fig. 7. Fig. 7. Final circuit with biasing F Fig.. Layout o the circuit o Fig

5 . 5 IV. CONCLUSIONS We have demonstrated an ultrawideband LNA with dual-loop negative eedback in TSMC 0.8μm technology. It has a high gain o 8.8dB over a bandwidth up to 8GHz with a minimum noise igure o db. S is below 0dB rom very low requencies up to 0GHz. Since the supply voltage is 3.3 V, and the total current consumption is 5mA, the power consumption equals 50mW. In table, below, a comparison with previous UWB LNA designs is made. We can state that our work is one o the most advanced LNA solutions or UWB applications and that it can also be used or other, e.g., multi-band, applications due to its wide-band eatures. Further there are some advantages and disadvantages over previously published designs. Advantages: We only use two inductors in total compared to solutions that distributed or LC-ladder networks. This means that our chip will be much smaller and cheaper. We use standard technology. We achieve very low noise, high gain and wide band matching at reasonable power consumption. Since the design is based on negative eedback, it beneits rom technology (T) advancements, leading to a larger loop gain and hence a larger bandwidth and a lower power consumption. [3] Li Xiaolong, Wouter A. Serdijn, Bert E.M. Woestenburg and Jan Geralt bij de Vaate: A broadband indirect-eedback power-to-current LNA, proc. IEEE ISCAS, Island o Kos, Greece, pp. 89 9,, May 4 [4] Martins, M.A.; van Hartingsveldt, K.; Verhoeven, C.J.M.; Fernandes, J.R., A wide-band low-noise ampliier with double loop eedback Circuits and Systems, 005. ISCAS 005.IEEE International Symposium, pp Vol. 6, 3-6 May 005 [5] van Zeijl, P.T.M. A new high-dynamic range dual-loop power-tocurrent ampliier Solid-State Circuits, IEEE Journal o Volume 4, Issue 3, pp , Jun 989 [6] Ren-Chieh Liu; Kuo-Liang Deng; Huei Wang, A 0.6--GHz broadband distributed ampliier Radio Frequency Integrated Circuits (RFIC) Symposium, 003 IEEE 8-0, pp.03 06, June 003 [7] Ren-Chieh Liu; Chin-Shen Lin; Kuo-Liang Deng; Huei Wang, A GHz 0.6-dB cascode distributed ampliier VLSI Circuits, 003. Digest o Technical Papers. 003 Symposium, pp.39 40, - 4 June 003 [8] Knapp, H.; Zoschg, D.; Meister, T.; Auinger, K.; Boguth, S.; Treitinger, L., 5 GHz wideband ampliier with.8 db noise igure in SiGe bipolar technology Microwave Symposium Digest, 00 IEEE MTT-S International Volume, pp , 0-5 May 00 [9] C.J.M. Verhoeven et al, Structure Electronic Design Negative Feedback Ampliiers Kluwer Academic Publishers, 003 TABLE : COMPARISON WITH THE STATE-OF-THE ART REPORTED WIDEBAND AMPLIFIERS Technology S S B [GHz] N min Powe r IIP3 [dbm] [mw] [] 0.8 um < [6] 0.8 um < N/A [7] 0.8 um < N/A [8] 0.5 um SiGe < [] 0.8 um SiGe < Our wor k 0.8 um < Disadvantages: We use three CS stages in our circuit, rendering requency compensation more diicult. The voltage-to-current eedback resistor R is so small that it is very sensitive to parasitic capacitance and resistance o wires, so integration with other circuits and packaging must be done very careully. ACKNOWLEDGEMENT The authors would like to thank Arjan van Genderen or his support on Cadence and The Dutch Freeband Knowledge Impulse Program or inancial support. REFERENCES [] Ismail, A.; Abidi, A.A., A 3-0-GHz low-noise ampliier with wideband LC-ladder matching network Solid-State Circuits, IEEE Journal o Volume 39, Issue, pp , Dec. 004 [] A. Bevilacqua and A. Niknejad, An ultra-wideband LNA or 3. to 0.6 GHz wireless receivers in Int. Solid-State Circuis Con. Tech. Dig., 5-9, pp Vol., Feb