ULTRA-WIDEBAND (UWB) radio has become a popular

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1 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 9, SEPTEMBER Design of Wideband LNAs Using Parallel-to-Series Resonant Matching Network Between Common-Gate and Common-Source Stages Yu-Tsung Lo, Student Member, IEEE, and Jean-Fu Kiang, Senior Member, IEEE Abstract A method is proposed to design wideband low-noise amplifiers (LNAs) made of cascaded common-gate (CG) and common-source (CS) stages with a parallel-to-series resonant interstage matching network. The first CG stage has a dual-band response, and the second CS stage has higher gain between these two bands. By applying the proposed interstage matching technique, conjugate matching is achieved at high and low bands, while the midband loss is compensated by the second stage. The output network of the first stage and the input network of the second stage resonate at the same frequency. Two wideband LNAs are designed based on this method and implemented in m RF-mixed signal CMOS process. The first LNA operates at GHz, having db of power gain and db of noise figure (NF) at the power consumption of 13.4 mw. The second LNA operates at GHz, having db of power gain and db of NF at the power consumption of 13.9 mw. Index Terms Common gate (CG), common source (CS), lownoise amplifier (LNA), matching network, parallel series, ultrawideband (UWB). I. INTRODUCTION ULTRA-WIDEBAND (UWB) radio has become a popular subject since the Federal Communications Commission (FCC) released the GHz frequency band for unlicensed operations [1]. UWB applications in other frequency bands have also been studied, including the GHz band for UWB radar and the GHz band for wireless metropolitan area network (WMAN) [2]. Impedance and noise matching over a wide band is the most challenging task to design a wideband low-noise amplifier (LNA), which is crucial to an UWB system. The bandwidth of conventional amplifiers is limited by the parasitics in transistors and impedance-matching techniques [3]. In [4], an ladder filter has been placed at the input of a common-source (CS) amplifier, but the insertion loss of the filter degrades the noise figure (NF). In [5], another inter-stage network is added to increase the power gain, but the NF is 6 db around 10 GHz. The high NF in these designs is attributed to the ladder filter. Manuscript received November 25, 2010; revised April 29, 2011; accepted May 23, Date of publication July 07, 2011; date of current version September 14, This work was supported by the National Science Council (NSC), Taiwan, under Contract NSC E The authors are with the Department of Electrical Engineering and the Graduate Institute of Communication Engineering, National Taiwan University, Taipei 106, Taiwan ( jfkiang@cc.ee.ntu.edu.tw). Digital Object Identifier /TMTT By applying a higher gate voltage to a smaller transistor, the input parasitic capacitance can be reduced while the transconductance is maintained. Hence, a wider bandwidth can be achieved under the same noise level. However, the power consumption is increased and the bandwidth enhancement is still limited [3]. Distributed amplifiers (DAs) have been used to increase the bandwidth. However, they often consume more power, take larger chip size, and usually have higher NF. For example, the DA presented in [6] has a gain of 10 db, NF of , and consumes 7 mw, but the chip size is mm.a smaller chip of mm has been designed by making use of the mutual coupling among inductors, but it consumes 26 mw of dc power [7]. A negative feedback technique can be used to design wideband amplifiers by trading the gain for bandwidth, while preserving the noise and stability performance [8]. In [9], a dual reactive feedback mechanism is adopted to a CS amplifier to achieve a broadband noise and impedance matching. Both a two-stage reactive feedback and current-reuse technique have been applied to design a wideband amplifier with good performance in NF, gain, and impedance matching [10]. In [11], both resistive feedback and inductive peaking technique have been used to achieve db of NF over GHz. The common-gate (CG) configuration is known for its wideband input matching [12]. However, a single-stage CG amplifier may not have enough gain, and cascading additional stages may reduce the bandwidth due to the difficulties of inter-stage matching. In [13], coupled resonators have been used to construct a wideband interstage matching network in a -band cascaded CS amplifier. A wideband LNA operating in GHz has also been proposed [14], in which coupled resonators are used as the load of the common-emitter stage. In this work, an effective inter-stage matching technique is proposed to design wideband LNAs made of cascaded CG and CS stages. Two LNAs in 3 10 and GHz, respectively, have been implemented to verify this method. The CG topology and the inter-stage matching network are discussed in Sections II and III, respectively, two LNA designs in different UWB bands are presented in Section IV, the measurement results are discussed in Section V, and these are followed by conclusions in Section VI. II. CG LNA TOPOLOGIES Although the poor gain response makes the CG topology less popular for narrowband applications, it is often adopted in the /$ IEEE

2 2286 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 9, SEPTEMBER 2011 Fig. 1. (a) Typical CG LNA. (b) CG stage in cascade with CS stage. wideband amplifier design since its input impedance over a wide band is about ( is the effective transconductance, equal to for simple CG stage), which is close to 50, but its noise factor is proportional to. Fig. 1(a) shows a single CG stage, which has good performance over 3 10 GHz [15]. At higher frequencies, cascaded stages may be needed to provide sufficient gain. Fig. 1(b) shows a cascaded CG and CS LNA. In a typical design approach, let the CG amplifier at the first stage have higher gain at lower band, and the gain at higher band is provided by the CS amplifier at the second stage [12], [16]. Since the noise increases rapidly at frequencies higher than the resonant frequency of the CS stage, and the first stage provides little gain at higher frequencies, the CG and CS cascaded amplifier often suffers from worse noise performance at higher frequencies. Besides, the mismatch between the load impedance of the CG stage and the input impedance of the CS stage results in ripples in the passband [11], [17]. Fig. 2 shows the schematic and response of a CG stage, a CS stage, and a cascaded CG-CS LNA with a parallel-to-series matching network, which is proposed to improve the performance of the cascaded CG-CS LNA. In this design approach, dual-band response is achieved at the first stage, which is different from that of a standalone CG stage shown in Fig. 2(a). The response of the second stage in the middle band compensates for that of the first stage. Thus, the cascaded LNA has a wideband performance. Also, the NF at higher frequencies is reduced due to the higher gain response of the first stage. III. PARALLEL-TO-SERIES MATCHING TECHNIQUE Fig. 3(a) shows a typical parallel-to-series network in a bandpass filter design. By selecting the value of inductors and capacitors to make the parallel network and series network resonate at the same frequency, i.e.,, bandpass response can then be achieved as shown in Fig. 3(b). Fig. 3(c) shows the frequency response when the source impedance and load impedance are not equal to 50. In this case, the parallel-to-series matching network exhibits a dual-band response with a dip in the middle. Fig. 4 shows the impedances of an ideal parallel and series networks. Conjugate matching is achieved at the low and high frequencies, while the middle band suffers from impedance mismatch because the output resistance of the parallel tank is much higher than that of the series tank. This Fig. 2. Schematic and frequency response of: (a) CG stage, (b) CS stage, (c) cascaded CG, and CS stages with parallel-series matching network. Fig. 3. Parallel-to-series RLC network. (a) Schematic. (b) Frequency response with R = R =50. (c) Frequency response with R = 250, R = 40, C =0:0835 pf, L =0:6 nh, C =0:06 pf, L =0:834 nh. phenomenon implies that the source and load impedances different from 50 may be explored for inter-stage matching in the two-stage LNA.

3 LO AND KIANG: DESIGN OF WIDEBAND LNAs USING PARALLEL-TO-SERIES RESONANT MATCHING NETWORK BETWEEN CG AND CS STAGES 2287 By substituting the definitions of in (2) and in (4) into (10), we have (11) In case, (1) and (3) are reduced to (12) (13) Fig. 4. Impedances of the parallel and series RLC networks shown in Fig. 3(a). Next, we will prove that two such conjugate matching points always exist if: 1) the parallel and the series tanks resonate at the same frequency and 2) the output resistance of the parallel tank is larger than the input resistance of the series tank. For the parallel network consisting of,, and, as shown in Fig. 3(a), the impedance can be expressed as Let where, the sign applies when while the sign applies when. The impedance of the series matching network, as shown in Fig. 3(a), can be expressed as Let where, the sign applies when while the sign applies when. Note that both the parallel and series networks are designed to resonate at the same frequency,. In case, substitute (2) into (1), and substitute (4) into (3) to obtain By imposing and at,wehave which imply (1) (2) (3) (4) (5) (6) or (7) (8) (9) (10) By imposing and at, we obtain the same equations as (7) and (8). Thus, (11) also applies when. The frequency of conjugate matching,, can be expressed in terms of and by solving (2) and (4), respectively, to have (14) (15) These two expressions are equal if (10) and (11) are satisfied. Similarly, the frequency of conjugate matching,, can be expressed in terms of and by solving (2) and (4), respectively, to have (16) (17) Both expressions are equal if (10) and (11) are satisfied. In summary, we have proven that when the parallel and the series networks resonate at the same frequency, and, conjugate matching can be achieved at and if (11) is satisfied. When applying the proposed parallel-to-series inter-stage matching technique to design wideband LNAs, one should bear in mind that: 1) the response in Fig. 3(c) has dual bands, the input impedance should be designed close to 50 and 2) the gain drop in the middle band should be compensated for. Adopting a CG stage as the first stage resolves the input matching issue due to its low input impedance. Wideband gain response can be obtained by choosing a CS stage as the second stage, and letting it operate at the resonant frequency of the inter-stage matching network. Fig. 5 shows the small-signal circuit model of a CG stage cascaded with a CS stage via the proposed parallel-to-series matching network. The resistance is the equivalent output resistance, including the channel resistance, is the load inductance, and is the gate drain parasitic capacitance. The dip of frequency response of the first stage is expected to be compensated for by the CS stage with inductive degeneration, of which the input impedance can be expressed as [18] (18)

4 2288 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 9, SEPTEMBER 2011 Fig. 5. Small-signal circuit model of a CG stage cascaded with a CS stage via the proposed parallel-to-series matching network. Fig. 7. LNA design in GHz band with parallel-to-series matching technique, the component values are derived at 22 GHz. Fig. 6. LNA design in 3 10-GHz band with parallel-to-series matching technique, the component values are derived at 6 GHz. As a result, the input port toward the CS stage behaves like a series network. Note that the input resistance of this CS stage depends on the reactive components and. IV. CIRCUIT DESIGN AND ANALYSIS Figs. 6 and 7 show two LNA designs in and GHz bands, respectively, using the parallel-to-series matching technique. A. Input Matching The input impedance of a CG stage is approximately equal to [19]. The effect of the source inductance and parasitic capacitance at the gate source junction has been considered in [12] and [15], but the loading effect is neglected. However, input matching becomes more dependent on the loading as the gate length gets narrower [20]. It will be shown later that two frequencies with zero input reactance can be observed with a proper parallel-to-series inter-stage matching technique. Based on the small-signal model shown in Fig. 5, the input impedance of the LNA can be derived as (19) where,, and are the drain source resistance, transconductance, and gate source capacitance, respectively, of, is the inductance at the source of, and is the load impedance looking from the drain of. The transistor is made of transistors and in parallel, each having 47 fingers, and each finger is 1.5- m wide. The dc blocking capacitor plays a minor role in input matching. In the 3 10-GHz LNA, the parallel tank consisting of and resonates around 6 GHz, and provides a wideband response. Its insertion loss is less than 0.9 db from 2.5 to 10.6 GHz. In the GHz LNA, the parallel tank resonates around 22 GHz, and also provides a wideband response with insertion loss less than 1 db from 13 to 30 GHz.

5 LO AND KIANG: DESIGN OF WIDEBAND LNAs USING PARALLEL-TO-SERIES RESONANT MATCHING NETWORK BETWEEN CG AND CS STAGES 2289 Fig. 8. Simulated impedance Z of the parallel RLC tank and Z of the series RLC tank for the 3 10-GHz LNA, - 1 -: R,---:X, :R, 111: X. Fig. 9. Simulated impedance Z of the parallel RLC tank and Z of the series RLC tank for the GHz LNA, - 1 -: R,---:X, :R, 111: X. The noise factor can be modified from [15] and [17] as (20) where is the loss due to the input passive components, is the resistance of signal source, is the available power gain of the CG amplifier, and is the noise factor of the following stage. The parameters associated with transistor include the frequency of unity current gain, the coefficient of channel thermal noise, the ratio of the transconductance, and the channel conductance at zero drain-to-source bias and the gate noise coefficient. The transconductance is selected by tradeoff between the input matching in (19) and the NF in (20), respectively. For the 3 10-GHz LNA, the transistor has the width of 141 m and is biased at V, thus S, higher than S used in [17]. Higher value helps to reduce the NF. The input impedance solely due to is approximately 20, The loading of will contribute part of the input resistance as indicated in (19). For the GHz LNA, the transistor is designed to have S, biased at V, with the total width of 88 m. Fig. 8 shows the simulated inter-stage impedances. The output impedance of the first stage,, resonates at 6.15 GHz. The CS stage forms a series matching network, also resonating at 6.15 GHz. The condition is satisfied at 3.7 and 10 GHz, one below and one above the resonant frequency of 6.15 GHz. At 6.15 GHz, the output resistance of the first stage mismatches with the input resistance of the second stage, making the power gain of the first stage drop and display a dual-band response. However, in the design of the GHz LNA, is not quite constant, as shown in Fig. 9. Since the inductance increases at higher frequencies, which increases the input resistance of the CS stage as in (18). As a consequence, the frequency with is separate from that with in the higher band; hence, the gain is degraded due to imperfect conjugate matching. As shown in Figs. 9 and 10, seen from the drain of is purely resistive at the lower conjugate-matching frequency of 14 GHz, and the input impedance shown in Fig. 11 is purely Fig. 10. Simulated load impedance Z GHz LNA. 111: X, : R. at the drain of the first stage in the Fig. 11. Input impedance of the GHz LNA, 111: simulated X,- 1 -: calculated X, - - -: simulated R, : calculated R. resistive at 12.5 GHz, At the higher band, although exact conjugate matching is not reached, the reactance is still low. A frequency with almost pure input resistance still exists in the higher band. B. Wideband Gain Fig. 12 shows the simulated gains of two separate stages and the cascaded LNA operating in the 3 10-GHz band. The second

6 2290 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 9, SEPTEMBER 2011 Fig. 12. Simulated gains of the 3 10-GHz LNA, 111: first stage, - - -: second stage, : cascaded LNA. Fig. 14. Simulated NF with and without a source-body resistor, : with R, - - -: without R. Fig. 13. Simulated voltage gains of the GHz LNA, - - -: first stage, 111: second stage, : cascaded LNA. stage compensates the low gain of the first stage around 6 GHz so that the overall gain shows a wideband response. Note that when the CG stage stands alone, it exhibits low gain over a wideband. The dual-band gain response appears when the CG stage is connected to the CS stage via the parallel-to-series matching network. Fig. 13 shows the simulated gains of two separate stages and the cascaded LNA operating in the GHz band. The gain in the higher band of the first stage is smaller due to the imperfect conjugate matching, as mentioned in Section IV-A. The lower gain in the midband of the first stage is compensated for by the second stage. C. Noise Reduction The input transconductance and the available power gain of the CG stage have the most profound effect on the overall noise factor. By selecting the value of to be higher than 20 ms, low noise factor can be obtained, as predicted by (20). On the other hand, the CG stage exhibits a dual-band response, and the higher noise factor of the CS stage at frequencies below and above the resonant frequency can be substantially suppressed. As a result, fair noise factor is achieved over the whole wideband due to the proper choice of, as well as the dual-band characteristics of the CG stage. The transistor is implemented as two transistors in parallel. Thus, more fingers are available to reduce the effective gate resistance [21]. Also note that this approach may reduce if the finger width is smaller than 1 m [22]. Both the source and body of each transistor are connected with a resistor of high resistance; hence, the substrate current noise referred to the drain node is reduced [23]. It has also been reported that the NF is reduced by 0.58 db with body floating [23]. Fig. 14 shows that the simulated NF of the proposed LNA with a source-body resistor is lower than that without one by 0.5 db across the frequency band. Since no resistive load is connected to the CG stage, as compared to [12], [15], and [20], the thermal noise from such resistive load is spared. The gate and drain of in both designs are biased at the same voltage, sharing the bypass capacitors. Recall that is part of the output resonant tank of the first stage. This inductive load is critical in wideband matching and noise reduction. D. Summary of Design Procedure Step 1) Adjust the source inductance to resonate with the gate source parasitic capacitance of transistor at the center of the band. Step 2) Select higher transconductance such that is smaller than 50 to reduce the noise. The resistance contributed by the second stage will improve the matching. Step 3) Design a narrowband CS stage with series to resonate with around the center of the frequency band. Step 4) Adjust of the CG amplifier to resonate with the parasitic gate drain capacitance at the resonant frequency. Step 5) Design the second stage with proper gain and input matching at the resonant frequency. Choose proper degeneration inductance to calculate. Smaller leads to a wider band, while larger leads to a narrower band. Substitute into to calculate, Impose the condition to update.

7 LO AND KIANG: DESIGN OF WIDEBAND LNAs USING PARALLEL-TO-SERIES RESONANT MATCHING NETWORK BETWEEN CG AND CS STAGES 2291 Fig. 15. Photograph of the 3 10-GHz LNA chip. Fig. 17. Gain of the 3 10-GHz LNA, : measured, 111: simulated. Fig. 16. Photograph of the GHz LNA chip. Fig. 18. Input reflection coefficient of the 3 10-GHz LNA, : measured, 111: simulated. Since is the parasitic capacitance of, the magnitude of is adjusted by changing the size of, which also affects the magnitude of. The bias voltage may be adjusted to maintain the same. Hence, input matching and proper gain are simultaneously achieved over a wide band. V. RESULTS AND DISCUSSIONS Figs. 15 and 16 show photographs of the 3 10-GHz LNA chip and the GHz LNA chip, respectively. Both are fabricated using the TSMC m RF mixed-signal 1P6M process. The chip size of the former is 0.83 m 0.82 m, and that of the latter is 0.83 m 0.65 m, including testing pads in both cases. When measuring the 3 10-GHz LNA chip, the RF ports are probed, and the dc is fed through bond wires [24]. Fig. 17 shows the measured, which is above 9.6 db from 3.1 to 10.3 GHz. Fig. 18 shows the input reflection coefficient, which is lower than 9 db across the entire band. Fig. 19 shows the NF, which is between db from 3.1 to 10.3 GHz. The parameters are measured with an Agilent PNA N5230A with short-openload-thru (SOLT) calibration. The power consumption is 13.4 mw. The ouput reflection coefficient is lower than 8dB across the band. If the LNA is directly connected to a mixer as in a direct-conversion receiver, the LNA output is not required to match to 50. and are measured at each Fig. 19. NF of the 3 10-GHz LNA, - 1 -: measured, : simulated. subband group of the multiband orthogonal frequency-division multiplexing (MB-OFDM) UWB specification. ranges from 12.5 to 10 dbm from group 1 (center at 3960 MHz) to group 5 (center at MHz). The ranges from 3 to 1 dbm with a two-tone spacing of 4 MHz, considering the channel spacing of MB-OFDM UWB is MHz. Fig. 20 shows that at 3960 MHz is 2 dbm. For the GHz LNA chip, on-wafer measurement is conducted with both dc and RF probes. The -parameters are

8 2292 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 9, SEPTEMBER 2011 Fig. 23. Loci of S in the Smith chart. (a) 3 10-GHz LNA. (b) GHz LNA, black curve: measured, gray curve: simulated. Fig. 20. Measured IIP of the 3 10-GHz LNA at 3960 MHz. Fig. 24. NF of the GHz LNA, - 1 -: measured, : simulated. Fig. 21. Gain of the GHz LNA, : measured, 111: simulated. Fig. 25. Measured IIP of the GHz LNA at 24 GHz. Fig. 22. Input reflection coefficient of the GHz LNA, : measured, 111: simulated. measured with an Agilent PNA E8361A with SOLT calibration. Fig. 21 shows the gain of db. Fig. 22 shows that the input reflection coefficient is below 8.6 db between GHz, and below 10 db between GHz. The loci of are also shown in the Smith chart, as in Fig. 23. Fig. 24 shows that the measured NF between db across the band. The noise is measured with an Agilent N8975A. The calibration is done twice during the measurement, one below 26.5 GHz with the noise meter only, and the other above 26.5 GHz with the noise meter and a K40 down-converter. The measured NF is 4.32 at 26.4 GHz and 4.68 at 26.6 GHz, indicating consistency between these two different calibrations. The total dc power consumption is 13.9 mw, the input is 12 dbm at 24 GHz, and the is 2 dbm at 24 GHz, as shown in Fig. 25. Table I compares the performance of the 3 10-GHz UWB LNA with those in the recent literature. This design shows good noise performace, as well as moderate gain and matching perfomance. Table II compares the GHz LNA with those found in the recent literature. This design also shows excellent

9 LO AND KIANG: DESIGN OF WIDEBAND LNAs USING PARALLEL-TO-SERIES RESONANT MATCHING NETWORK BETWEEN CG AND CS STAGES 2293 TABLE I MEASURED PERFORMANCE OF THE 3 10-GHz LNA AND COMPARISON WITH THE LITERATURE exclude buffer, exclude pad, from 4 to 8 GHz, #: group delay, ##: only the variation is reported, # worse case TABLE II MEASURED PERFORMANCE OF THE GHz LNA AND COMPARISON WITH THE LITERATURE at 24 GHz, voltage gain, active area, at 20 GHz, #: group delay noise performance, as well as moderate gain and matching perfomance at a low dc power consumption. VI. CONCLUSIONS A design technique has been proposed for wideband LNAs using a parallel-to-series resonant matching network between CG and CS stages. Two conjugate-matching frequencies become available by equalizing the resonant frequencies of the two networks. The CG stage behaves as a dual-band amplifier, while the CS stage compensates for the midband gain. The CG stage also provides a wideband input matching, and the inter-stage matching network also contributes to the input resistance. Wideband characteristics can be achieved by properly choosing these two conjugate-matching frequencies. Two LNA chips have been designed and fabricated based on this design technique. The first one operates in GHz, having db of power gain and db of NF, at the power consumption of 13.4 mw. The second one operates

10 2294 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 9, SEPTEMBER 2011 in GHz, having db of power gain and db of NF, at the power consumption of 13.9 mw. ACKNOWLEDGMENT The authors would like to acknowledge fabrication and measurement support provided by the National Chip Implementation Center (CIC), Taiwan. REFERENCES [1] A. Batra et al., Multi-band OFDM physical layer proposal for IEEE Task Group 3a, IEEE P /268r1-TG3a, Sep [Online]. Available: r2P802-15_TG3a-Multi-band-CFP-Document.pdf [2] C. Eklund, R. B. Marks, K. L. Stanwood, and S. Wang, IEEE standard : A technical overview of the wireless MAN air interface for broadband wireless access, IEEE Commun. Mag., pp , Jun [3] F. Ellinger, Radio Frequency Integrated Circuits and Technologies. Berlin, Germany: Springer, 2007, p [4] A. Bevilacqua and A. M. Niknejad, An ultrawideband CMOS low noise amplifier for GHz wireless receivers, IEEE J. Solid- State Circuits, vol. 39, no. 12, pp , Dec [5] Y. J. Lin, S. S. H. Hsu, J. D. Jin, and C. Y. Chan, A GHz ultrawideband CMOS low noise amplifier with current-reused technique, IEEE Microwave Wireless Compon. Lett., vol. 17, no. 3, pp , Mar [6] Y. H. Yu, Y. J. E. Chen, and D. Heo, A 0.6-V low power UWB CMOS LNA, IEEE Microw. Wireless Compon. Lett., vol. 17, no. 3, pp , Mar [7] Y. J. Wang and A. Hajimiri, A compact low noise weighted distributed amplifier in CMOS, in Proc. IEEE Int. Solid-State Conf., Feb. 2009, pp [8] B. G. Perumana, J. H. C. Zhan, S. S. Taylor, B. R. Carlton, and J. Laskar, Resistive-feedback CMOS low-noise amplifiers for multiband applications, IEEE Trans. Microw. Theory Tech., vol. 56, no. 5, pp , May [9] C. T. Fu, C. N. Kuo, and S. S. Taylor, Low-noise amplifier design with dual reactive feedback for broadband simultaneous noise and impedance matching, IEEE Trans. Microw. Theory Tech., vol. 58, no. 4, pp , Apr [10] M. T. Reiha and J. R. Long, A 1.2 V reactive-feedback GHz low-noise amplifier in 0.13 m CMOS, IEEE J. Solid-State Circuits, vol. 42, no. 5, pp , May [11] Y. S. Lin, C. Z. Chen, H. Y. Yang, C. C. Chen, J. H. Lee, G. W. Huang, and S. S. Lu, Analysis and design of a CMOS UWB LNA with dual- RLC-branch wideband input matching network, IEEE Trans. Microw. Theory Tech., vol. 58, no. 2, pp , Feb [12] K. H. Chen, J. H. Lu, B. J. Chen, and S. I. Liu, An ultra-wideband GHz LNA in 0.18 m CMOS, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, pp , Mar [13] F. Vecchi, A wideband mm-wave CMOS receiver for Gb/s communications employing interstage coupled resonator, in Proc. IEEE Int. Solid-State Conf., Feb. 2010, pp [14] M. El-Nozahi, E. Sanchez-Sinencio, and K. Entesari, A millimeterwave (23 32 GHz) wideband BiCMOS low-noise amplifier, IEEE J. Solid-State Circuits, vol. 45, no. 2, pp , Feb [15] H. Zhang, X. Fan, and E. S. Sinencio, A low-power, linearized, ultrawideband LNA design technique, IEEE J. Solid-State Circuits, vol. 44, no. 2, pp , Feb [16] R. M. Weng, C. Y. Liu, and P. C. Lin, A low-power full-band lownoise amplifier for ultra-wideband receivers, IEEE Trans. Microw. Theory Tech., vol. 58, no. 8, pp , Aug [17] Y. Lu, K. S. Yeo, A. Cabuk, J. Ma, M. A. Do, and Z. Lu, A novel CMOS low-noise amplifier design for GHz ultra-wide-band wireless receivers, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 8, pp , Aug [18] D. K. Shaeffer and T. H. Lee, A 1.5-V 1.5-GHz CMOS low noise amplifier, IEEE J. Solid-State Circuits, vol. 32, no. 5, pp , May [19] D. Im, I. Nam, H. T. Kim, and K. Lee, A wideband CMOS low noise amplifier employing noise and IM2 distortion cancellation for a digital TV tuner, IEEE J. Solid-State Circuits, vol. 44, no. 3, pp , Mar [20] Y. Shim, C. W. Kim, J. Lee, and S. G. Lee, Design of full band UWB common-gate LNA, IEEE Microw. Wireless Compon. Lett., vol. 17, no. 10, pp , Oct [21] A. J. Scholten, Noise modeling for RF CMOS cirucit simulation, IEEE Trans. Electron Devices, vol. 50, no. 3, pp , Mar [22] S. P. Voinigescu, M. Tazlauanu, P. C. Ho, and M. T. Yang, Direct extraction methodology for geometry-scalable RF-CMOS models, in Proc. IEEE Int. Microelectron. Test Structures Conf., Mar. 2004, pp [23] H. K. Chen and H. J. Chen, A 5.2-GHz cascade-mos 0.35 m BiCMOS technology ultr-low-power LNA using a novel floating-body method, Microw. Opt. Technol. Lett., pp , Jun [24] Y. T. Lo and J. F. Kiang, A direct-conversion UWB RF front-end for MB-OFDM application, in IEEE Int. Ultra-Wideband Conf, Vancouver, BC, Canada, Sep. 2009, pp [25] H. K. Chen, D. C. Chiang, Y. Z. Juang, and S. S. Lu, A compact wideband CMOS low-noise aplifier using shunt resistive-feedback and series inductive-peaking techniques, IEEE Microw. Wireless Compon. Lett., vol. 17, no. 8, pp , Aug [26] S. Lou and H. C. Luong, A 0.8 GHz 10.6 GHz SDR low-noise amplifier in 0.13 m CMOS, in IEEE Custom Integr. Circuits Conf., Sep. 2008, pp [27] H. Y. Yang, Y. S. Lin, and C. C. Chen, 2.5 db NF GHz CMOS UWB LNA with small group-delay variation, Electron. Lett., vol. 44, no. 8, pp , Apr [28] S. M. R. Hasan, Analysis and design of a multistage CMOS bandpass low-noise preamplifier for ultrawideband RF receiver, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 4, pp , Apr [29] H. Y. Yang, Y. S. Lin, and C. C. Chen, 0.18 m GHz CMOS UWB LNA with db gain and ps group delay, Electron. Lett., vol. 44, no. 17, Aug [30] H. Jacobsson, L. Aspemyr, M. Bao, A. Mercha, and G. Carchon, A 5 25 GHz high linearity, low-noise CMOS amplifier, in Eu. Solid- State Circuits Conf., Sep. 2006, pp [31] H. Zhang, X. Fan, and E. S. Sinencio, A low-power, linearized, ultrawideband LNA design technique, IEEE J. Solid-State Circuits, vol. 44, no. 2, pp , Feb Yu-Tsung Lo (S 09) was born in Taipei, Taiwan, on March 11, He received the B.S. degree in electrical engineering and M.S. degree in communication engineering from National Taiwan University (NTU), Taipei, Taiwan, in 2007 and 2009, respectively, and is currently working toward the Ph.D. degree at NTU. Since 2010, he has been with the National Chip Implementation Center (CIC), Hsinchu, Taiwan, where he is engaged in RF integrated circuit (RFIC) and device measurements. His research interests include CMOS RFICs, microwave systems and measurements, and UWB technology. Jean-Fu Kiang (S 87 M 89 SM 11) was born in Taipei, Taiwan, on February 2, He received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei (NTU), Taiwan, in 1979 and 1981, respectively, and the Ph.D. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1989, respectively. From 1985 to 1986, he was was with Schlumberger-Doll Research, Ridgefield, CT. Frm 1989 to 1990, he was with the IBM T.J. Watson Research Center, Yorktown Heights, NY. From 1990 to 1992, he was with Bellcore, Red Bank, NJ. From 1992 to 1994, he was with Electromedical Systems, Siemens, Danvers, MA. From 1994 to 1999, he was with National Chung-Hsing University, Taichung, Taiwan. Since 1999, he has been a Professor with the Department of Electrical Engineering and the Graduate Institute of Communication Engineering, NTU. His research interests include electromagnetic applications and system issues, including wave propagation in the ionosphere and atmosphere, vehicle and satellite navigation, RF module and transceiver design, antennas, dielectric resonators, and sensor technology.