VLSI Design Considerations of UWB Microwave Receiver and Design of a 20.1 GHz Low Noise Amplifier for on-chip Transceiver

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1 Daffodil International University Institutional Repository Proceedings of NCCI Feruary VLI Design Considerations of UWB Microwave Receiver and Design of a 0. GHz Low Noise Amplifier for on-chip Transceiver Rashid,. M. hahriar Daffodil International University Downloaded from Copyright Daffodil International University Lirary

2 VLI Design Considerations of UWB Microwave Receiver and Design of a 0. GHz Low Noise Amplifier for on-chip Transceiver. M. hahriar Rashid, heikh Nijam Ali, Apratim Roy and A. B. M. H. Rashid Department of Electrical and Electronics Engineering Bangladesh University of Engineering and Technology, Dhaka-000, Bangladesh. shahriar043@yahoo.com, nijam_uet@yahoo.com, apratim_roy_45@yahoo.com Astract: The VLI Design Considerations for the implementation of an UWB Microwave Receiver on silicon chip is presented here. A 0. GHz Low Noise Amplifier (LNA) for on-chip Transceiver is designed in TMC 0.8 µm CMO Process as an example of a Microwave VLI circuit. The LNA achieves a power gain of.7 db with a Bandwidth of 3. GHz. Input and output matching are oth 38 db with Reverse isolation less than -6 db in the entire Bandwidth. The LNA eing driven from a V supply consumes 5.48 mw of power. Keywords: UWB, Microwave, Receiver, 0. GHz, Low Noise Amplifier, LNA.. Introduction: Considerations aout VLI implementation of Communication circuitry are necessary for the communication system to e practically realizale. Communication in higher frequency is always attractive ecause of the higher achievale Bandwidth, higher signal power, lower attenuation, thus, longer communication distance etc. UWB (Ultra Wideand) communication has some additional advantages e.g. larger Bandwidth, Less interference, Higher signal security. Designing VLI circuits for high frequency operation requires special attention to compensate for some effects which are negligile in low frequencies. Parasitic effects in higher frequency complicate the situation even more. In this paper, presenting an on-chip Microwave UWB Receiver architecture, we mention the considerations, which require careful concentration to design the VLI circuitry for the architecture. Then, we design a Low Noise Amplifier (LNA) in TMC 0.8 µm CMO technology, operating at a centre frequency of 0. GHz as an example of microwave VLI circuit. At last, the simulation results of the LNA are presented to reveal its performance.. On-Chip Microwave UWB Receiver Architecture: Figure is an on-chip Microwave UWB Receiver Architecture. Here, the Antenna receives a modulated microwave signal (of centre frequency f O ) and feeds to a microwave Low Noise Amplifier (LNA). LNA amplifies the received signal, which is very week. LNA should e designed with minimum possile Noise Figure ecause it is the first stage of the receiver whose Noise contriution affects the performance of the receiver most. Output of the LNA is transferred to a mixer (for example a Gilert Cell), via BPF (Band Pass Filter ). BPF separates the Modulated Band of frequencies. Mixer takes two inputsone is the Receiver signal of centre frequency, f O and other is a locally generated signal of frequency f LO. Output of the Mixer is the modulated signals of centre frequencies f ±. BPF separates the modulated O f LO signal of Intermediate frequency (IF). Thus, down conversion is completed. Task of the Demodulator is to produce the aseand signal of frequency, demodulating the IF signal. Baseand Amplifier then amplifies the aseand signal and feeds it to the load. Now the Antenna, LNA, BPF and the Mixer together form the Receiver Front end, which operates at high frequency (in microwave range). o, these are the components, which require special considerations during VLI implementation. 3. Microwave VLI Design Consideration: Designing VLI circuits at high frequency is difficult, especially in case of analog circuit. Following are the topics requiring special care for circuits operating in high frequency: 49

3 Fig. A asic Microwave UWB receiver architecture 3. cattering Parameters (-Parameter): Motivation for using -Parameter is to resolve the difficulties of measuring lumped parameters at high frequencies. Transistors are prone to oscillate when they are opened or shorted to measure lumped parameters. Moreover, lumped parameter representation may not e suitale in some cases, for example in the case of transmission line (lumped T or π model are not suitale in microwave frequencies). For these reasons -parameter representation is adopted at high frequencies, whose variale is a travelling wave with associated power with it. The Interpretation of -parameters is presented in figure referring to a two port network. The following four - parameters are necessary for complete characterization. Input matching parameter: Output matching parameter: Power gain parameter: Reverse isolation parameter: = ; when a a = ; when a a = ; when a a = ; when a a In Matrix Form: = Where, network and two port network. a ; a Incident power on the two port Reflected power from the o, should e maximized and,, should e minimized for est performance. For Microwave circuits like figure 3, Input and Output Matching networks should e incorporated, so that and in the operating Band of frequency. It results in =0 and =0. Thus est matching is achieved. 3. Voltage Gain: Like low frequency circuits, we try to maximize voltage gain in Microwave circuits as well, which in turn maximizes and minimizes Noise Figure. For this reason highest possile gain is desirale in Microwave circuits. Fig. A two port network in terms of -parameter. 50

4 Fig. 3 A asic two port Microwave circuit 3.3 Noise Figure (NF): Noise figure is a measure of the noise performance of a microwave circuit, and is defined as, NR N N NF + NR GN GN out out Transistor = = = [] in in Where, and are the output and input NR respectively. G is the voltage gain of the circuit and,, are output, input and transistor noise power respectively. NF of the first stage of the Receiver, which is an LNA, is very important ecause it directly adds to the overall NF of the entire Receiver front end. It is given y, NF Re ceiver = NFLNA + ( NFusequent ) G LNA Where,, and are the NF of the receiver, LNA and susequent stages of the Receiver and is the voltage gain of the LNA. is tried to keep minimum to maximize the Noise Performance of the Receiver. 4. A 0. GHz Low Noise Amplifiers Low Noise Amplifier, eing the first stage of the Microwave Receiver, plays an important role in the performance of the Receiver front end. It s Noise Figure affects the Noise Performance of the Receiver most. A Low Noise Amplifier, operating at 0. GHz is designed here to achieve maximum possile gain and minimum possile Noise Figure, as an example of Microwave VLI CMO circuit on silicon chip. in 4. Process election In our design, TMC 0.8 CMO process technology was selected as the farication process. Though, CMO silicon process is much cheaper than OI (silicon on Insulator) or ige process ut it is difficult to operate in higher frequency (operation aove 30GHz y silicon CMO process is rarely reported). OI and ige process can operate at much higher frequency ut are difficult to faricate and are very costly. o, our motivation was to select a process to design a simple LNA operating at sufficient high frequency, achieving a good noise performance with minimum possile area consumption, so that, it can e easily faricated. 4.3 Circuit Description A simple LNA circuit topology is shown in figure 4(a). We designed a 0. GHz LNA modifying the circuit which is shown in figure 4(). In this circuit, resonates with the drain to gate capacitance of M (C gd ) and exhiits a high Impedance at the resonance frequency,. This is the center frequency of operation of the LNA. o, operating frequency can e changed changing the value of or changing the dimension of M (thus changing ). But other effects prevent us from going eyond 0. GHz. Quality factor of, eing dependent on it's internal resistance, governs the Band Width and Gain of LNA. Input Impedance of the LNA is: Where, = + ; () 5

5 ) a) Fig. 4 A simple LAN (a) and designed 0. GHz LNA () = Gate- source capacitance of M. Equation () shows that is a function of Ls and is to produce a real part for matching with the real part of the source impedance, which is around 50Ω. But Ls reduces Gain ecause a portion of input signal drops here. is added for etter input matching and to otain simultaneous low power consumption with low input noise which is known as power constrained simultaneous Noise Input Matching (PCNIM). is used for matching purpose so that it can cancel out the capacitive imaginary part of the input impedance of the core Amplifier. and are coupling capacitances though, also helps in input matching. prevents the ac signal to go through the dc supply source resistance, thus supply source noise reduces here. is the internal resistance of the signal source. The W/L ratio of M should e large to minimize transistor noise and to increase g m which in turn increases gain at the expense of increased power consumption. o a compromise etween Noise, gain and power dissipation was required. M isolates the output from the input so that input and output impedances are independent of each other. W/L ratio of M is tried to minimize for etter isolation with the penalty of increased Noise. o, again a compromise was required here. Optimizing component values, we could achieve input impedance =50 Ω and output impedance, =.7 KΩ at 0. GHz. Asence of imaginary part in and proves a good input and output matching. Finally is the ias voltage for the M via. is large enough (around 5 KΩ) so that it does not effect much. 4.4 Noise Consideration LNA should e designed with lowest possile noise, which signifies the designation - low noise. That is why we designed the circuit, avoiding any resistor in the DC ias path, which is the primary noisy component in RF circuits. The only resistor in our circuit is, which could e easily replaced y an inductor of value 3nH to 7nH, with the penalty of increased area consumption. As is not carrying any DC current and is large enough for the RF noise current passing through it to e negligile; so, can e safely incorporated for a minimum chip size. Transistor Noise is the major source of noise in our circuit. Larger the aspect ratio of a transistor, lower is its noise contriution. In the designed LNA, M and M have aspect ratios 0µm/.7µm and 45µm/.7µm respectively (aspect ratio of M is not recommended to increase; ecause, it is isolating input and output). o, M is adding little amount of noise, whereas, 5

6 noise contriution from M is expected to e very low. Moreover PCNLM is used to reduce input noise even more. Though, ideal energy storing elements are noiseless, ut capacitors and inductors of our LNA may add some noise ecause of their internal parasitic resistance on silicon chip. Lastly, noise figure of an LNA of this structure can e approximated as, Ls NF = + 3 L and we have used =350 ph, =.6 nh which promises a low NF. o, from noise consideration, we can expect a good Noise Performance, from our designed LNA. g Fig. 5 (a) vs. frequency. 4.5 Area Requirement Transistors, Capacitors and Resistors require low area on silicon chip. The primary area consuming elements are inductors, which is usually an onchip spiral inductor. Larger the value of the inductors, the more numer of turns is necessary, which increases the area requirement. In our design the value of the inductors are L d =.6nH, L s =350pH, L g =.7nH, which are quite small values. o ased on our design, even if a fully integrated on-chip 0.GHz Low Noise amplifier is faricated, we can expect minimum area consumption. 4.6 imulation Results We simulated our circuit in HPICE with TMC 0.8 µm CMO silicon process. A signal source of 50Ω internal resistance was used and a load of.7 KΩ was driven without any output uffer to oserve the performance of our core amplifier (a simple active as well as passive uffer can e incorporated at the output to drive a low resistance load such as 50Ω if required. In that case a source follower may e a good choice). imulation results for -parameters are plotted in db in figure 5(a), (), (c) and (d). Figure 5(a) shows peak forward gain, of.7 d at the center frequency of 0.GHz with a Band Width of 3.GHz. Reverse isolation,, in Figure 5() is less than -6dB in the entire and-width. Input and output matchings ( and ) are oth -38 db, which are shown in Figure 5(c) and 5(d) respectively. Matchings are less than -4dB and Fig. 5 () vs. frequency. Fig. 5 (c) vs. frequency. 53

7 Fig. 5 (d) vs. frequency. -5dB in the entire and-width. Figure 6 is the voltage gain of the circuit, which peaks to 7. db at 0.GHz with a and-width of 3.GHz. The circuit, eing driven y a V power supply, consumes 5.48mW of power. Therefore, the simulation results show that, the designed circuit exhiits good performance, which was expected theoretically. 5. Conclusion In this paper, the VLI design considerations for faricating a Microwave UWB on-chip receiver was discussed together with a Receiver Architecture. Later, a very important component of the Receiver, a Low Noise Amplifier operating at 0. GHz was designed in CMO process as an example of microwave VLI circuit. Circuit configuration and performance was discussed in detail. Lastly, simulation results of the circuit was presented, which exhiited a forward gain of.7 Fig. 6 Voltage gain vs. frequency. db at 0. GHz with and-width of 3.GHz. Input and output matchings were oth -38dB. Reverse isolation was always elow -6dB and the voltage gain was 7.dB at 0.GHz with a and-width of 3.GHz. The circuit consumed 5.48 mw of power when iased y a V power supply. Therefore, performance of the sample circuit was quite satisfactory. References [] Basco Leaung, VLI for Wireless Communication. Prentice Hall Electronics and VLI eries. ereis Editor Charles G. odini. [] C. H. Doan,. Emami, A. M. Niknejad, and R. W. Broadersen, Millimeter-wave CMO design, IEEE J. olid-tate Circuits, vol. 40 no., pp , Jan [3] M. A. Masud, H. Zirath, M. Ferndahl, and H. 0. Vickes, 90-nm CMO amplifier, in IEEE RFIC ymp., 004, pp [4] tar-hspice manual, Release 998., July