Design of a CMOS Distributed Power Amplifier with Gradual Changed Gain Cells

Transcription

1 Chinese Journal of Electronics Vol.27, No.6, Nov Design of a CMOS Distributed Power Amplifier with Gradual Changed Gain Cells ZHANG Ying 1,2,LIZeyou 1,2, YANG Hua 1,2,GENGXiao 1,2 and ZHANG Yi 1,2 (1. College of Electronic and Optical Engineering, College of Microelectronics, Nanjing University of Posts and Telecommunications, Nanjing , China) (2. National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology, Nanjing University of Posts and Telecommunications, Nanjing , China) Abstract A non-uniform Distributed power amplifier (DPA) is designed and implemented in a 0.18µm CMOS technology. The gradual changed gain cells work with the tapered on-chip inductors to construct non-uniform artificial transmission lines, which improves the output power and efficiency in a wide frequency band while maintaining good input and output impedance matching. The proposed DPA achieves 9dB average associated gain from 1 to 17.2GHz, and the input return loss is less than -9dB while the output return loss is less than -8.5dB in the desired frequency band. The output power at 1dB Output compression point (OP 1dB ) is more than 7.8dBm in the frequency band of 2-16GHz, and the peak power-added efficiency is 6.2% with the OP 1dB 12.6dBm at 4GHz. Key words Distributed amplifier, Impedance matching, Power added efficiency, Artificial transmission line. I. Introduction Wide dynamic range microwave front-end components are required for future ultra-wideband agile and software reconfigurable communication links [1]. The high efficiency and broadband Power amplifier (PA) is a key component for the wide dynamic range front-end, and the low cost is expected for the base-station transceivers. Distributed amplifiers (DAs) provide an effective approach for extending the bandwidth and therefore are widely used in the design of ultra-wideband systems. Compared to advanced process technologies such as GaAs PHEMT [2 4] and GaN HEMT [5 8], CMOS technology has the advantages of integration with other Radio frequency (RF) and baseband circuits on the same substrate toward System on chip (SOC). One major deficiency of most reported CMOS DAs [9 13] is their low output power and efficiency due to the low breakdown voltage and the high silicon substrate loss, which impedes them to be integrated as PAs in SOC. This paper presents a non-uniform CMOS Distributed power amplifier (DPA) using a 0.18µm CMOS technology. The cascode structure with series inductor is applied to enhance the forward gain and the reverse isolation. The gradual changed gain cells together with tapered onchip inductors construct non-uniform Artificial transmission lines (ATLs), which improves the power performance in a wide frequency band efficiently while maintaining good input and output impedance matching. The fabricated DPA achieves more than 7.8dBm output power at 1dB Output compression point (OP 1dB )withthepoweradded efficiency (PAE) of % in the frequency band of 2 16GHz. The wide operating frequency band and good power performance enable the designed DPA to be applied in the next generation communication systems such as 5G and WiGig, or some RF test equipments. II. Principle of Distributed Amplifier DAs are realized by absorbing the parasitic capacitances of transistors and on-chip inductors into gate and drain ATLs, and the gain roll off due to the parasitic capacitances of transistors is reduced. The classical circuit of DAs is shown in Fig.1. The signal phase delay of artificial transmission lines in gate and drain should be matched to make the signals in different paths be added positively at the output port. The voltage gain A v and the characteristic impedance Manuscript Received June 24, 2017; Accepted Apr. 20, This work is supported by the National Natural Science Foundation of China (No ), the Natural Science Foundation of the Jiangsu Higher Education Institutions of China (No.15KJB510020), and the Research Fund of Nanjing University of Posts and Telecommunications (No.NY218051). c 2018 Chinese Institute of Electronics. DOI: /cje

2 Design of a CMOS Distributed Power Amplifier with Gradual Changed Gain Cells 1159 Z 0 of DAs (not considering the loss of ATLs) are given as A v = 1 2 ng mz 0 (1) Lg Ld Z 0 = = (2) C in C out where Z 0 is normally set to be 50Ω; C in and C out are the input and output parasitic capacitance of gain cells, respectively; L g and L d are the on-chip inductor of gate and drain ATLs, respectively. The desired inductance can be calculated according to Eq.(2) if the parasitic capacitance of transistors is known. Fig. 1. Classical distributed amplifier The bandwidth of distributed amplifiers is mainly restricted by the cutoff frequency f c of ATLs: 1 f c = 2π 1 = L g C in 2π (3) L d C out According to Eq.(2), L g and L d are proportional to C in and C out when the characteristic impedance is fixed. From Eq.(3), the cutoff frequency f c decreases with the increase of L g (L d )andc in (C out ). So, the contradiction between the gain and the bandwidth still exists in DAs, which is much more serious in conventional amplifiers. III. Circuit Design Fig.2 shows the proposed DPA consisting of four stages of gain cells, which connects in series by on-chip inductors. The power attenuation occurs when the input signal is transmitted along the input ATL for the parasitic resistance and impedance mismatch. The active device size of gain cells increases stage by stage to compensate the reduction of output power and linearity due to the gradual decrease of input signal. The effect of compensation is more significant with the increase of the device scaling, while it is more difficult to obtain good input and output impedance matching. Finally, the optimized size of transistors in gain cells changes from 80 to 160µm gradually. The cascode structure with series inductor [12] is used as the gain cell to enhance the forward gain and the reverse isolation, and the equivalent circuit is presented in Fig.2. The output impedance of gain cell is derived as 1 ω 2 L S C ds1 Z out =g m ω 2 [ω 2 L S C ds1 C gs2 C ds2 (C ds1 + C gs2 )C ds2 ] (4) where g m is the transconductance of transistors; C gs1, C gs2, C ds1 and C ds2 are the parasitic capacitance of transistors; L S is the series inductor in the cascode structure. The series inductor L S introduces a resonant frequency, which improves the output impedance Z out and therefore the forward gain at high frequency. But the change of L S also has an effect on S parameters of the DPA, which is shown in Fig.3. The impact is greater in the frequency band higher than 8GHz. Hence L S is set as 300pH for a compromise between S 11 and S 21. Fig. 2. Designed distributed power amplifier

3 1160 Chinese Journal of Electronics 2018 by 0.9dB and the increasement of OP 1dB is 1.1dB. Fig. 4. Output impedance of gain cells Fig. 3. Impact of the series inductor L S on S parameters. (a) S 21,(b) S 11 The output power of the DPA is the accumulation of output power of each gain cell. In Fig.2, Z LDi and Z RDi are the impedance seen leftwards and rightwards at the output point of each gain cell, which are connected in parallel between the output point of each gain cell and the ground. According to Norton s theorem, more power will flow rightwards and reach the output port if Z LDi is larger than Z RDi for the same parallel impedance consisting of Z LDi and Z RDi. Hence the on-chip inductors L Di reduce from 1200pH to 100pH gradually from the left to the right output port. With the increasing of the output signal for each gain cell, the output power is mainly determined by the output voltage swing. The load impedance Z Di of each gain cell shown in Fig.2 includes the output impedance of the gain cell itself. It is apparent that each gain cell will deliver more power with the smaller load for the same voltage swing. In the process of circuit design, the on-chip tapered inductors should be carefully designed and adjusted according to the requirement of the impedance at the center frequency. Considering the output impedance matching, the optimized Z Di is is around 25Ω as shown in Fig.4, and the frequency at the locations of the triangles is 10GHz. The power gain G p and the linear output power at the frequency of 10GHz are compared between the optimized DPA and the traditional uniform DPA (the on-chip inductor of the drain ATL is set to 700pH), which is shown in Fig.5. It can be observed that the power gain is improved Fig. 5. Comparision between designed DPA and traditional uniform DPA The sizes of the key devices are optimized and listed in Table 1. The on chip inductors are fabricated with the top metal interconnection and verified by electromagnetism simulation. Table 1. Sizes of the key devices Device Value Device Value Device Value L G1 400pH L D1 1200pH L S 300pH L G2 700pH L D2 700pH NM 11,NM 12 80µm/180nm L G3 500pH L D3 600pH NM 21,NM µm/180nm L G4 500pH L D4 400pH NM 31,NM µm/180nm L G5 400pH L D5 100pH NM 41,NM µm/180nm IV. Experimental Results Fig.6 shows the die photograph of the designed DPA with the size of 1.16mm 0.54mm. The circuit is measured via on-wafer test. The measurements were carried out using Agilent E8363B vector network analyzer, E8257D vector signal generator and E4448A spectrum analyzer. The amplifier consumes 55mA current with the supply voltage of 2.6V. The measured S parameters of the DPA are presented in Fig.7. The measured average forward gain

4 Design of a CMOS Distributed Power Amplifier with Gradual Changed Gain Cells 1161 (S 21 ) is 9dB from 1 to 17.2GHz with the gain flatness of ±1.5dB. The input return loss is better than 8.5dB from 2 to 19.6GHz and the output return loss is better than 8dB from 1 to 17.8GHz, which benefits from the non-uniform ATL structure. There is some inconsistency between the measured and simulated results, which is caused partly by the inaccurate device models form the Process design kit (PDK). Another reason is that the modeling of on chip inductors and interconnects may be not so perfect. in Fig.9. In the frequency band of 2 16GHz, the OP 1dB is from 7.8 to 10.5dBm while the corresponding PAE is from 3.6% to 6.2%, and the saturated output power is from 9.5 to 13dBm while the corresponding PAE is from 4.7% to 10.2%. The Output third-order intercept point (OIP3) is further measured with two-tone input, which is from 21.4 to 24.2dBm in the desired frequency band. Finally, Table 2 [9 16] summarizes the comparison between the fabricated DPA and the previously reported CMOS DAs. The proposed DPA exhibits high output OP 1dB and good PAE in a wide frequency band. Fig. 6. Die photograph Fig. 8. Measured OP 1dB, G p and PAE at 10GHz Fig. 7. Measured and simulated S parameters The output power together with the power gain and PAE of the DPA at the frequency of 10GHz is shown in Fig.8. The power gain is 8.5dB, and the OP 1dB is 9.1dBm with a PAE of 4.6%. The power measurements show that the fabricated DPA also has a good power performance in a wide frequency band, which is presented Fig. 9. Measured OP 1dB,OIP3andPAE Table 2. Comparison with previous reports of DAs Refs. CMOS Freq. Gain P DC OP 1dB Area PAE(%) b Technology (GHz) (db) (mw) (dbm) (mm 2 ) [9] 90nm DC @20GHz a 2.5@20GHz a 1.72 [10] 65nm DC @10GHz a 2.7@10GHz a 0.93 [11] 0.18µm @22 30GHz a @22 30GHz a 0.17 [12] 0.18µm @2 30GHz a 1.1 3@2 30GHz a 0.83 [13] 0.18µm @5 35GHz a @5 35GHz a 0.86 [14] 40nm @24 54GHz a @24 54GHz a 0.15 [15] 0.13µm @1 13GHz 9 17@1 13GHz @1 12GHz 9 19@1 12GHz 0.82 [16] 0.18µm @2 22GHz @2 22GHz 1.7 This work 0.18µm @2 16GHz @2 16GHz 0.63 Note: a The data is estimated from their papers for comparison; b PAE is estimated at 1dB gain compression point.

5 1162 Chinese Journal of Electronics 2018 V. Conclusions A GHz broadband DPA with the OP 1dB of more than 7.8dBm is implemented with a 0.18μm CMOStechnology. The non-uniform ATLs constructed by the gradual changed gain cells and tapered on-chip inductors improve the output power and efficiency of DPA while maintaining good input and output impedance matching. The high output power and good PAE enable the DPA to work as a wideband medium-power PA. References [1] F. Kohei, A DC to 22GHz, 2W high power distributed amplifier using stacked FET topology with gate periphery tapering, IEEE Radio Frequency Integrated Circuits Symposium, San Francisco, USA, pp , [2] J.S. Chen and A.M. Niknejad, Design and analysis of a stagescaled distributed power amplifier, IEEE Transactions on Microwave Theory and Techniques, Vol.59, No.5, pp , [3] G. Nikandish and A. Medi, Unilateralization of MMIC distributed amplifiers, IEEE Transactions on Microwave Theory and Techniques, Vol.62, No.12, pp , [4] A. Alizadeh and A. Medi, Distributed class-j power amplifiers, IEEE Transactions on Microwave Theory and Techniques, Vol.65, No.2, pp , [5] X. Zhou, L. Roy and R.E. Amaya, 1W, highly efficient, ultrabroadband non-uniform distributed power amplifier in GaN, IEEE Transactions on Wireless Components Letters, Vol.23, No.4, pp , [6] D.W. Kim, An output matching technique for a GaN distributed power amplifier MMIC using tapered drain shunt capacitors, IEEE Microwave and Wireless Components Letters, Vol.25, No.9, pp , [7] K.W. Kobayashi, D. Denninghoff and D.Miller, A novel 100MHz 45GHz input-termination-less distributed amplifier design with low-frequency low-noise and high linearity implemented with a 6 inch 0.15µm GaN-SiC wafer process technology, IEEE Journal of Solid-State Circuits, Vol.51, No.9, pp , [8] J. Kim, H. Park, S. Lee, et al., 6 18GHz, 26W GaN HEMT compact power-combined non-uniform distributed amplifier, Electronics Letters, Vol.52, No.25, pp , [9] A. Arbabian and A.M. Niknejad, Design of a CMOS tapered cascaded multistage distributed amplifier, IEEE Transactions on Microwave Theory and Techniques, Vol.57, No.4, pp , [10] A. Jahanian and P. Heydari, A CMOS distributed amplifier with distributed active input balun using GBW and linearity enhancing techniques, IEEE Transactions on Microwave Theory and Techniques, Vol.60, No.5, pp , [11] P. Chen, P.C. Huang, J.J. Kuo, et al., A 22 31GHz distributed amplifier based on high-pass transmission lines using 0.18µm CMOS technology, IEEE Microwave and Wireless Components Letters, Vol.21, No.3, pp , [12] J.C. Kao, P. Chen, P.C. Huang, et al., A novel distributed amplifier with high gain, low noise, and high output power in 0.18µm CMOS Technology, IEEE Transactions on Microwave Theory and Techniques, Vol.61, No.4, pp , [13] T.Y. Huang, Y.H. Lin, J.H. Cheng, et al., A high-gain lownoise distributed amplifier with low DC power in 0.18µm CMOS for vital sign detection radar, IEEE MTT-S International Microwave Symposium (IMS), Phoenix, USA, pp.1 3, [14] V. Bhagavatula, M. Taghivand and J.C. Rudell, A compact 77% fractional bandwidth CMOS band-pass distributed amplifier with mirror-symmetric norton transforms, IEEE Journal of Solid-State Circuits, Vol.50, No.5, pp , [15] M.M. Tarar and R. Negra, Design and implementation of wideband stacked distributed power amplifier in 0.13µm CMOSusing uniform distributed topology, IEEE Transactions on Microwave Theory and Techniques, Vol.65, No.12, pp , [16] Y. Zhang and K.X. Ma, A 2 22GHz CMOS distributed power amplifier with combined artificial transmission lines, IEEE Microwave and Wireless Components Letters, Vol.27, No.12, pp , ZHANG Ying was born in Anhui Province, China, in He received the Ph.D. degree in Nanjing University Of Science and Technology. He is an associate professor of Nanjing University of Posts and Telecommunications. His research interests include analog and radio frequency integrated circuits. ( zhangying@njupt.edu.cn) LI Zeyou was born in Jiangsu Province, China, in He is now a M.S. candidate of Nanjing University of Posts and Telecommunications. His present research interests include analog and radio frequency integrated circuits. ( @ njupt.edu.cn)