Analysis and design of a CMOS current reused cascaded distributed amplifier with optimum noise performance

Transcription

1 Journal of Communication Engeerg, Vol. 3, No., Jan.- June 04 Analysis and design of a CMOS current reused cascaded distributed amplifier with optimum noise performance Nahid Pazuki, Mahmoud Mohammad-Taheri, and Mohammad Dosaranian-Moghadam.Department of Electrical, Biomedical and Mechatronics Engeerg, Qazv Branch, Islamic Azad University, Qazv, Iran..School of Electrical and Computer Engeerg, Faculty of Engeerg, University of Tehran. Correspondg author: mtaheri@ut.ac.ir Abstract- In this paper, analysis, simulation and design of a distributed amplifier (DA) with 0.3µm CMOS technology the frequency range of 3-40 GHz is presented. Ga cell is a current reused circuit which is optimum ga, noise figure, bandwidth and also power dissipation. To improve the noise performance the frequency range of terest, a T- matchg low pass filter C network is utilized at the put gate of the designed amplifier. By this means, the proposed cascaded DA shows about 8% improvements noise figure and 0% improvement the ga compared with those of the other well-known configuration. To show the capability of the proposed method we also compared the figure of merit of the proposed amplifier with those obtaed with the other researches and showed that this figure is around 38% higher than that of those achieved by other researchers. The figure of merit cludes ga, bandwidth, power consumption and also noise figure. Index Terms- Distributed amplifier (DA), current reused structure, Conventional distributed amplifier (CDA), Cascaded sgle stage distributed amplifier (CSSDA), Figure of merit (FOM). I. INTODUCTION Broadband amplifiers have been widley used many systems such as, electronic warfare, microwave imagg and also optical tranceivers. In order to realize a broadband amplifier, Conventional Distributed Amplifiers (CDAs) are a good candidate due to thier ultra-wide band properties []. In [], a GaAs hybrid and MMIC technologies have been troduced. Due to low cost and tegration ability of distributed amplifiers (DAs), these amplifiers were also used CMOS technology [3]. However, due to the additive ga mechanism of DA, this amplifier is not suitable applications which high ga is required. This disadvantage of DA (low ga property) is more serios CMOS technology due to the low transconductance and high substrate loss a silicon-based process. In order to take the full advantage of the multiplicative ga mechanism of DA, two-dimensional DAs, Manuscript eceived 3-Dec.-03 and revised 5-Feb.-04, ISSN: Accepted on 4- March-04

2 Analysis and design of a CMOS current reused cascaded V g V dd g d g M F out C g d C s F g M s Fig.. Ga cell with the current reused structure such as cascaded multi-stage distributed amplifier (CMSDA) [4] and matrix DA [5], have been proposed. However, most cascaded DA topologies, the number of cascaded stages is typically smaller than that of the distributed cells, makg the ga primarily determed by the additive mechanism stead of the multiplicative one. Hence, CSSDA has been proposed to take full advantage of the multiplicative ga mechanism [6]. Although the CSSDA has potential of higher ga bandwidth performance than that of other DA topologies, its output power is limited by the device size of the last stage. A larger aspect ratio of transistor results higher output power at the cost of a degraded bandwidth. To improve the performance of the CSSDA, a DA with cascaded ga stages was proposed to achieve higher output power without sacrificg the bandwidth [7]. In addition to the ga-bandwidth performance, power dissipation was another parameter which should be considered. For this purpose, ga cell based on current reuse was proposed [8]. This configuration simply has the power dissipation of one stage but the power ga amplitude of two stages.the prospective of this paper is as follow. In the second section, the current reused circuit is analyzed. Then source degeneration ductance and gate matchg network are added and the analysis and design of the circuit is done. In the third section simulation results of the three stages cascaded distributed amplifier are presented and compared with those of the other reported amplifiers. Fally, the fourth section, the paper is concluded. II. ANAYSIS AND DESIGN OF DISTIBUTED AMPIFIE WITH CUENT EUSED CE Fig. shows the structure of the current reused amplifier. This circuits is fully analyzed [9]. Two of the ma aspects of this configuration are: low power consumption and high power ga. In the first stage of this circuit, a trade-off exists between noise and learity. In order to moderate this compromise, the noise impedance is calculated and optimized by utilizg a proper matchg network

3 Journal of Communication Engeerg, Vol. 3, No., Jan.- June 04 3 s v g g g g m v gs v s C gs v gs r o i d Z Fig.. Small signal model of the common source structure without source degeneration ductance at the put. Small signal model of the first stage of the current reused circuit is showed Fig.. Noise sources are v s 4kT f for source resistance, s v g 4kT f for gate resistance, and g id 4kT f gm for transistor channel. In this analysis, the gate noise is neglected (this assumption is held for the frequencies well below than cutoff frequency). Suppose that s g, therefore noise factor is derived as follows: F g ( )( ) gms s () T The optimum noise impedance is obtaed by equatg the derivation of the noise factor with respect to s given () to zero. This optimum noise impedance is derived as follows: T g s, opt ( ) () ( ) gm Substitutg () to (), the mimum noise factor is: F m ( ) gmg (3) T The followg assumptions are held to calculate a predesign value for s, opt : f 90 GHz, f 35 GHz,.5, g 5 m ms, g 8. Thus, the optimum value of the noise 5g m resistance usg () is s, opt 40 and therefore the mimum noise factor of the first stage of the current reused circuit is NFm. or NFm 0log Fm 0.8 db. Input impedance of the circuit shown Fig. is expressed as: gms Z g j[ ( g s ) ] (4) C C gs gs The first term (4) is the result of source ductance feedback. The source ductance troduces the real part for put impedance and can be used for put impedance or noise matchg. Now the source impedance can be calculated for mimum noise figure as follow: gm s opt g e( Z ) g g T s opt s (5) C gs T T

4 4 Analysis and design of a CMOS current reused cascaded v A v A v v 3 C C 3 C 3 Fig. 3. Two stage of ideal amplifiers with nodal resistance and capacitance Table I. Pole and zero of some of the rlc circuit configurations Z C v C v v C v v C C v - 0 However the gate resonant frequency is obtaed by equatg the imagary part of (4) to the zero. Therefore the gate resonant frequency is: C ( ) gs g s The above method is only valid for narrowband application sce the noise matchg is only achieved at the resonance frequency of gate 0 (4) is a purely real. C ( ) gs g s (6) where the put impedance given by III. DESIGN OF CUENT EUSED CICUIT WITH SOUCE DEGENEATION INDUCTO In order to derive a transfer function for a circuit, the followg method is used this paper. Assumg a two stage amplifier with ideal ga cells, as shown Fig. 3. esistance and capacitance of each node is extracted. The transfer function for this circuit can be expressed as: v v 3 Av Av ; spi s s s ici s s s p p p3 esistance and capacitance of each node generate a pole at that node. A v and A v are the low frequency gas of ga cells. This method is very simple and accurate enough. Other circuit (7)

5 Journal of Communication Engeerg, Vol. 3, No., Jan.- June 04 5 F g C gd d g m v g g o3, z3 g o r g C gs g s r g C gs z4 C gd z g m v g r o p4 out r o o C d C s C d d o C g z d F out o o3 p4 z z g C z3 0 C m gd g s gs C d C g d gs r C z4 o d d C d s g C m gd Fig. 4. Small signal model for the circuit of Fig. configurations are depicted Table I. As an example, parallel C circuit generates two poles at: C p and p simple method and Table I.. Transfer function of the proposed circuit is derived usg the described Small signal model of the two stages cascaded circuit of Fig. is depicted Fig. 4. As can be seen, the poles and zeros are determed term of the circuit elements. These poles and zeros are calculated implementg a proper circuit simplification. esonance frequencies 0 and 03 should be placed at the higher frequency band of 35 GHz. It should be noted that the gate-source capacitance of both transistors M and M are lower than 00 ff. On the other hand, for M with gm 5 ms, Ids 4 ma, and the cutoff frequency of 95 GHz, the source ductance usg Eq. (5) is s 6 ph. The value of C gs and C gs are 44 ff. Therefore, the value of gate ductance of T M, i.e. g, usg (6) with 0 35 GHz is 5 ph. The same procedure can be used to calculate the gate ductance of M, i.e. g, which is obtaed to be 0.6 nh. 0, p4, z, and z4 are higher than the higher end of frequency band while zeros z and z3 are lower than the lower end of the frequency band. Sce there is a conjugate pole near the lower end of the frequency band, zeros z and z3 flatten the slope of the signal band.

6 6 Analysis and design of a CMOS current reused cascaded V g g M s C s F s Z Z = s,opt Fig. 5. Matchg network circuit IV. DESIGN OF T-MATCHING NETWOK AT THE INPUT IN ODE TO IMPOVE CICUIT PEFOMANCE Circuit of Fig. needs a matchg network at the put to match 40 Ω optimum noise resistance to 50 Ω source resistance. The proposed matchg network is presented with series and parallel C as Fig. 5. In this figure, impedances Z is expressed as follows: s Z s s sc sc s s s s C.. s s C At the resonance frequency of C the last expression is simplified as follow: Z s C sc (9) For a complete put impedance matchg, Z should be matched to s. Therefore, we have: s s C sc. (8) Similarly, it could be stated that at the resonance frequency of C, Z can be expressed as: Z s C s sc (0) Z should be matched to s, and: C s sc. () Proposed matchg network is a low pass filter and two resonance frequencies are C and C. If both resonance frequencies are equal to 35 Grad s and, then the

7 Journal of Communication Engeerg, Vol. 3, No., Jan.- June 04 7 Structure Table II. Simulation results of common source, simple current reused, and improved current reused distributed amplifiers BW (GHz) P DC (mw) S, avg (db) S, avg (db) S, avg (db) NF (db) Common source Simple current reused Improved (proposed) current reused FOM value of capacitance and ductance of matchg network are 0 ff and 03 ph respectively. V. THE SIMUATION OF THE CASCADED DISTIBUTED AMPIFIE WITH IMPOVED CUENT EUSED GAIN CE The fal structures of the proposed distributed amplifier with improved current reused ga cell are showed Fig. 6 through Fig. 8. Simulations are done with Advanced Design System (ADS) from Agilent and circuit element models are from TSMC foundry. Circuit elements are from 30 nm F CMOS general purpose technology. The number of the cascaded stages of three gives the best results. esults of common source, simple current reused, and improved current reused (Fig. 6) ga cells distributed amplifiers are depicted Fig. 0 and Fig. 0 for comparison. In this figure, curves with no symbol, square symbol, and circle symbols are related to common source, simple current reused, and improved current reused circuits respectively. S of improved circuit is more flat than two other circuits. Bandwidth of improved circuit is about 0.5 GHz wider than simple circuit. S which represents the put matchg, improved circuit is better than simple circuit the high corner of the bandwidth. It is maly because of usg matchg circuit of Fig. 5 at the put of the amplifier. The matchg circuit Fig. 5 is designed to work at higher frequencies near 40 GHz. As a result better ga and put matchg is achieved at these high frequencies. It is also worth to mention that noise figure of proposed amplifier high frequencies near 40 GHz is improved respect to the simple current reused circuit. This is also due to proper noise matchg at the put stage. Noise figure of the common source amplifier is better than simple current reused and improved current reused circuit. This is due to the numerous number of on-chip ductors used current reused circuit. This ductors are usually made with low quality and therefore produce high noise at high frequencies. Noise figure of the current reused circuit at low frequencies (frequencies lower than GHz) is very high sce current reused circuit blocks signals with low frequency; hence no power ga is achievable low frequencies. Figure of merit given by (0) is used for comparison. S ( ). ( ) db BW GHz FOM P ( ). ( ) () DC mw NF db

8 8 Analysis and design of a CMOS current reused cascaded g V g g Port M V g C g d C s g DC Block g M s Port C Fig. 6. Fal structure of the improved current reused ga cell Fig. 7. Fal structure of the distributed amplifier with three improved current reused ga cell stages As can be seen Table II, the noise performance of the proposed circuit is 8% lower than that of common source circuit and its mimum is 5.6 db. Bandwidth of the proposed circuit is about 6% wider than that of common source and is 37 GHz. The ga of the proposed amplifier is also 0% higher than that of simple current reused amplifier. The amplifier has also FOM of.7 which is about 38% higher than those of two other circuits. Fally, Table III the comparison is made with the results reported by other references.

9 S() (db) NF(dB) S() (db) S() (db) Journal of Communication Engeerg, Vol. 3, No., Jan.- June 04 9 Fig. 8. Fal structure of the proposed cascaded distributed amplifier three stages Eqn Pdc_=-3*.*X.Vdd.i freq Hz Eqn Pdc_=-3*.*MDA_..X.Vdd.i Eqn Pdc_3=-3*.*MDA_3..X.Vdd.i Pdc_ Pdc_ Pdc_ E8 E9 E0 E -30 E8 E9 E0 E Frequency (Hz) Frequency (Hz) (a) E8 E9 E0 E 0 E8 E9 E0 E Frequency (Hz) Frequency (Hz) (b) Fig. 9. (a) Power ga (S ) and (b) put return loss (S ) of the three stage cascaded distributed amplifiers with common source (no symbol and black color), simple current reused (with square symbol and blue color), and improved current reused (with circle symbols and red color) core circuits. Ht: power consumption of the three blocks of each cascaded DA with. V power supply is reported above the figure (a); Pdc_, Pdc_, and Pdc_3 are for common source, simple current reused, and improved (proposed) current reused DAs respectively.

10 0 Analysis and design of a CMOS current reused cascaded (a) (b) Fig. 0. (a) Output return loss (S ) and (b) noise figure (NF) of the three stage cascaded distributed amplifiers with common source (no symbol and black color), simple current reused (with square symbol and blue color), and improved current reused (with circle symbols and red color) core circuits VI. CONCUSION In this paper, a common source ga cell was first vestigated. Then a method was implemented to simultaneously optimize the noise and impedance performances. Consequently, the improved ga cell with source degeneration, current reused and put matchg network were proposed to design a CCSDA. Fal results showed that the method proposed this paper successfully improve amplifier performances cludg power dissipation, noise, ga and the figure of merit.

11 Journal of Communication Engeerg, Vol. 3, No., Jan.- June 04 Table III. esults of some reported das and the proposed da for comparison Voltage- ef. Year Tech. BW (GHz) S avg Power [0] nm CMOS DC [4] nm CMOS DC [] 0 65 nm CMOS DC-65 na [] nm CMOS na [3] nm CMOS DC [4] nm CMOS DC This work nm CMOS NF m FOM EFEENCES [] J.-C. Chien and.-h. u, "40-Gb/s high-ga distributed amplifiers with cascaded ga stages 0.8-μm CMOS," IEEE Journal of Solid-State Circuits, vol. 4, pp , 007. [] H.-Y. Chang, Y.-C. iu, S.-H. Weng, C.-H., Y.-. Yeh, and Y.-C. Wang, "Design and analysis of a DC GHz fully tegrated distributed amplifier usg GaAs HEMT HBT cascode ga stage," IEEE Transactions on Microwave Theory and Techniques, vol. 59, pp , 0. [3] J.-C. Kao, P. Chen, P.-C. Huang, and H. Wang, "A Novel Distributed Amplifier With High Ga, ow Noise, and High Output Power CMOS Technology," IEEE Transactions on Microwave Theory and Techniques, vol. 6, pp , 03. [4] A. Arbabian and A. M. Niknejad, "Design of a CMOS tapered cascaded multistage distributed amplifier," IEEE Transactions on Microwave Theory and Techniques, vol. 57, pp , 009. [5] T.-Y. Chen, J.-C. Chien, and.-h. u, "A 45.6-GHz matrix distributed amplifier 0.8-µm CMOS," Proceedgs of the IEEE Custom Integrated Circuits Conference, 005, pp. 9-. [6] P. Chen, J.-C. Kao, P.-C. Huang, and H. Wang, "A novel distributed amplifier with high ga, low noise and high output power 0.8-µm CMOS technology," IEEE MTT-S International Microwave Symposium Digest, 0, pp. -4. [7] Y.-S., J.-F. Chang, and S.-S. u, "Analysis and design of CMOS distributed amplifier usg ductively peakg cascaded ga cell for UWB systems," IEEE Transactions on Microwave Theory and Techniques, vol. 59, pp , 0. [8] H.-. Huang, M.-F. Chou, W.-S. Wuen, K.-A. Wen, and C.-Y. Chang, "A low power CMOS distributed amplifier," IEEE Annual Conference Wireless and Microwave Technology, 005, pp [9].-M. Weng, C.-Y. iu, and P.-C., "A low-power full-band low-noise amplifier for ultra-wideband receivers," IEEE Transactions on Microwave Theory and Techniques, vol. 58, pp , 00. [0].-C. iu, C.-S., K.-. Deng, and H. Wang, "Design and analysis of DC-to-4-GHz and -GHz CMOS cascode," IEEE Journal of Solid-State Circuits, vol. 39, pp , 004. [] A. Jahanian and P. Heydari, "A CMOS distributed amplifier with distributed active put balun usg GBW and learity enhancg techniques," IEEE Transactions on Microwave Theory and Techniques, vol. 60, pp , 0. [] C. Feng, X. P. Yu, W. M. im, and K. S. Yeo, "A compact. 39 GHz self-biased low-noise amplifier 65 nm CMOS technology," IEEE Microwave and Wireless Components etters, vol. 3, pp , 03.

12 Analysis and design of a CMOS current reused cascaded [3] C.-Y. Hsiao, T.-Y. Su, and S. S. Hsu, "CMOS distributed amplifiers usg gate dra transformer feedback technique," IEEE Transactions on Microwave Theory and Techniques, vol. 6, pp , 03. [4] J.-C. Kao, P. Chen, P.-C. Huang, and H. Wang, "A novel distributed amplifier with high ga, low noise, and high output power 0.8-µm CMOS technology," IEEE Transactions on Microwave Theory and Techniques, vol. 6, pp , 03.