ARTIFICAL INDUCTOR EFFECT ON MOS TRANSISTORS

Transcription

1 ATFCAL NDUCTO EFFECT ON MOS TANSSTOS V.V. Buniatyan, G.M. Travajyan, and A.H. Asatryan State Engeerg University of Armenia, Yerevan, ntroduction and state-of- the-art ecently the terest to the radio-fruency tegrated circuits is sharply creased, connected with the rapid development of mobile communication. The modern tegrated technology for F applications (800 МHz-.5G Hz) rather easily provides creation of active devices. However, the presence of high-quality passive components represents a serious problem for tegrated realization [, ]. The high-quality ductor monolithic performance is the most difficult to realize by methods, which would be compatible to modern planar manufacturg techniques of micro- and nanoscale tegrated circuits. At present a significant progress tegration of monolithic spiral ductors has been achieved [, 3]. However, for the F spiral ductors the quality factor, Q, at high fruencies sharply decreases caused by losses of energy a silicon substrate and metal traces of a spiral. Some approaches have been proposed to address the substrate issues. The crease the thickness of metal (up to 4 μm) and dielectric (up to 7 μm) layers of ductor design allows one to improve the quality factor till 0-, and also to weaken the fluence of sk effect. Noise couplg via the semiconductor substrate at gigahertz fruency range has been reported [4, 5]. Usg of the substrates with high (above 5-0 Ohm cm) specific resistance partially decreases the level of noise couplg. n many publications [3, 4, 5] it is shown that etchg of pits the silicon substrate under the spiral ductors or usg the patterned ground shields between ductor and substrate allow reducg impact of substrate on circuit parameters. However, offered approaches addition complicate technological process, crease the cost price too, and hence, from the pot of view of technology, are not acceptable variants. Thus, new approaches and decisions of a substrate problem are necessary to overcome the creased complexity of process: particular, for cheap tegration monolithic ductors structure of the chip. Except for constructive-technological methods of improvement of spiral ductor parameters on chip, the other alternative opportunities of ductive effects are considered. They can be based on different physical prciples and schematic solutions [6]. The terestg demonstration of ductive effect is observed schemes with a feedback. The theoretical analysis [7] for the hightemperature superconductg th films shows that application the operational amplifier of a feedback on C chas can become an effective way of creatg synthetic ductance solidstate circuits. 57

2 n the present report a new circuit is offered which can exhibit synthetic ductive effect and the possibilities of realization of the suggested scheme are discussed. Distctive feature of the offered scheme is based on the opportunity of universality of the MOS transistor to use as a typical circuit element (as an active device, resistor, and capacitor). Moreover, it is very important that the offered variant of tegrated synthetic ductance both technological and schematic aspects is compatible with modern planar MOS technology.. Description of the circuit The electric scheme of realization of synthetic ductive effect and the correspondg uivalent scheme for calculations are shown Figs. and. OA OA M C M 4 U UG M M5 Uout U C 3 Uout M 3 Fig. Fig. As resistors and capacitors a C feedback cha the MOS transistors are used. They are cluded the circuit of realization of passive components the parameters of which can be varied a wide range. The operational amplifier is also collected on MOS transistors under the scheme of emitter-follower with voltage ga close to unit. Considerg that the put resistance of amplifier is real and also approaches fity, we can write down the uations for fdg the put impedance of the scheme + ( + ( + + = U jωc ) ( K 3 ) + ( U ), = U jωc + + ( K 3 U ) = U ),. () 58

3 At put susoidal signal U and voltage ga K u = for an impedance of a circuit we obta the expression Z( jω ) = + jx = + jωl, () where and L are, accordgly, uivalent to resistance and ductance of a circuit. They are expressed as = ( 3 ω C ), L 4C. (3) For the circuit s uivalent quality factor the followg expression is obtaed: 4ωC Q =. (4) 3 ω C From uation () it is seen that for the offered circuit the uivalent reactive component of impedance has an ductive character. The put impedance, as a first approximation, can be presented the form of consistently connected uivalent resistance and uivalent ductance. Both components of the impedance and the quality factor, as follows from expressions (3) and (4), depend on the resistance and capacitance C of the MOS structure. 3. Discussion of results For a qualitative and quantitative substantiation of presence of ductive effect the offered scheme the circuit fruency characteristics one analyzed by means of program SPCE. Modelg is led for the circuit, which all MOS structures are realized on modern submicron (90 nm and probably below) technological level. The geometrical sizes of structures will correspond to the micron and submicron range. The analysis of circuit ductive nature was vestigated by means of resonant characteristics. The amplitude-fruency (Fig. 3a) and phase-fruency characteristics (Fig. 3b), as well as the current resonant characteristic (Fig.3c) of the realized scheme are simulated. The resistance and capacitance parameters of C feedback cha for the simulated circuits correspond to =5 Ω and C=00 pf. Obtaed dependences are herent to a parallel resonance circuit with correspondg uivalent C, L and parameters. At certa fruencies ( our case ~. GHz) the circuit shows self-resonance and at the resonance pot the reactive part of the admittance is ual to zero ( Fig. 3b the phase angle is ual to zero). At lower fruencies the ductive character of the circuit is observed. Beyond the self-resonance fruencies uivalent capacitance will domate and circuit has a capacitive behavior. Thus, the ductive effect has a fite bandwidth. For the practical applications it is necessary to stay well below the self-resonance fruencies. However, the ductive effect, consuently self-resonant fruency of the circuit, will be 59

4 controlled and adjusted, as evident from (3), by changg the and C parameters of MOS structures C feedback circuit. One can use the obtaed dependences and results for the design of monolithic tegrated circuits with synthetic ductance. a) b) c) Fig. 3 EFEENCES. B.azavi. F microelectronics, Prentice Hall PT, J. ogers and C. Plett. adio fruency tegrated circuit design. Artech House, Q. Huang, F. Plazza, P.Ozsatti, and T. Ohguro. J.of Solid-State Circuits, v. 33, 7 (998). 4. C.P. Yue and S.S. Wong. EEE Journal of Solid-State Circuits, v. 33, 5 (998). 5. C.Su, L. Chen, and S.Chang. Solid- State Electronics, 46 (00). 6. V.M. Harutyunyan and F.V. Gasparyan. Phys. Stat. Sol. (a), 49, 797 (978). 60

5 7. В.М. Арутюнян, В.В. Буниатян, А.В. Саркисян, Р.А. Аветисян. Радиотехника и электроника, т. 47, (00). 6