Small Signal Amplifiers - BJT. Definitions Small Signal Amplifiers Dimensioning of capacitors

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1 Small Signal mplifiers BJT Defitions Small Signal mplifiers Dimensiong of capacitors 1

2 Defitions (1) Small signal condition When the put signal (v and, i ) is small so that output signal (v out and, i out ) is confed the active region of the output characteristics of the device, the device is operatg a condition of small signal. More specifically, the condition of small signal are verified when the variations output are so small that the parameter values of the device can be regarded as constant. n these conditions, the amplifiers can be analyzed usg the smallsignal models of the BJT. The small signal conditions occur, general, for the first stages constitutg an amplification system. earity n conditions of the small signal, the amplifier can be considered lear. The output signal is proportional to the put signal. This property derives from the fact that the components of the circuit are described by lear equations. f the system is lear applies the prciple of superposition. mplitude and phase distortion So that a waveform is not altered across the amplifier is necessary that each of its susoidal component is equally modified amplitude and phase. 2

3 Defitions (2) Transfer function or network function Complex function that describes the relationship between the output signal and the put signal. t is defed the aplace doma (s) or the frequency doma (s = jw) mplitude and phase response eal functions obtaed by specifyg amplitude and phase of the transfer function with s = jw. Describe the variation of modulus and phase when the frequency changes. Ga and phase shift of an amplifier n the case of an amplifier transfer function is also called amplification (or ga) and can be expressed magnitude and phase. elatively to the various electrical quantities considered for entry and exit there are various defitions of ga s S oltage amplification Current amplification Transconductance amplification v i G ; ; ; Transresistance amplification ; 3

4 Defitions (3) nput impedance t is the impedance viewed by the source of the put signal. Z ; Output mpedance t is the impedance viewed from the output port. This impedance can be terpreted as the Theven impedance at the output port. Z out out out ; S S out s out Z Z out 4

5 Defitions (4) Three configurations can be considered CC CC CC C1 1 2 C BJT E C2 C3 s s s s C1 1 2 C E BJT C2 s s C1 1 2 E BJT C2 Common Base Conf.. Common Emitter Conf. Common Collecttor Conf. P // v i out 1 2 CBC CEC CCC h hfe C // C // fe 1 h fe E // C // h hie 1h fe E E 1 ie h C fe v v v C 1 h fe hie // P // hie 1 hfe E P 1 E 1 hfe // C C hie h fe E // 1 P // hie h fe E // P E hie P // S 1 h fe Electronics: a systems approach by N. Storey 5

6 Defitions (5) i b h fe i b h ie Common Base C. v E C // v out i b h fe i b Common Emitter C. v 1 // 2 h ie E C // v out i b h fe i b Common Collecttor C. h ie v v out 1 // 2 E // C 6

7 Common Emitter C. The voltage supply ( CC ) for the signal is equivalent to a short circuit v 1 v be 2 equivalent i circuit b h fe i b h ie v ce C v out v 1 // 2 i b h ie E h fe i b C // v out E Capacitors the midband are equivalent to a short circuit 1 1 // // h h // 1 2 ie fe E 1 2 P v i h // v i h h v out b fe C b ie fe E v h // // out v h 1h fe C C ie fe E i vout 1 i v i // v // C C E 7

8 Common Collettor C. The voltage supply ( CC ) for the signal is equivalent to a short circuit v 1 v be 2 equivalent i circuit b h fe i b h ie v ce C i b h fe i b h ie v v out 1 // 2 E // C E v out Capacitors the midband are equivalent to a short circuit // // h h // // 1 2 ie fe E 1 2 P v i h // v i h h // out b fe C b ie fe C v 1 h out fe E // v 1 v hie 1 h fe E // i vout 1 i v i // v // // C C C 8

9 Defitions (6) Couplg capacitor The amplifier is used to provide voltage and current levels adequate to drive the load connected to the output. The use of a sgle BJT is sometimes not sufficient to achieve this result. This limitation can be overcome by connectg cascade several amplifiers, so that the signal emitted by the source is creased by each amplifier constitutg the cascade. Each dividual amplifier is called stage. Capacitors are used to connect one stage to another, they are referred couplg capacitors. The couplg capacitors have the function of providg sulation DC so that the bias of one stage does not affect that of the next stage. These capacitors have to pass the C signal from one stage to another with mimum distortion. S s Z Z out 9

10 Defitions (7) Bypass capacitors These capacitors are connected parallel to a resistor, so C signals on the resistor are short circuited. n this way the C and DC circuits are different. For example, the case of CEC, a bypass capacitor on E allows to obta a higher voltage ga. h fe C // h 1h ie fe E h // fe C h ie For the capacitor bypass the followg configurations can be used : BJ T C3 E BJT E C3 BJ T C3 e 3 3 Ga variation with frequency Because of the troduced reactive elements and the parasitic reactive elements the response of the amplifier is function of frequency. 10

11 Defitions (8) Midband To simplify the study, it is useful to assume that there is a range of frequencies (bandwidth) which all the reactive effects are negligible. Therefore this range, ga ( 0 ), put and output impedances are real quantities ( out ). Three different frequency ranges (low, medium and high frequencies) can be considered. Three different frequency ranges correspond to three different dynamic circuits. Cutoff frequencies The midband is delimited by two frequencies, the lower cutoff frequency f l (determed by couplg and bypass capacitors) and the upper cutoff frequency f u (determed by the junction capacitance and the parasitic effects). Freq. The cutoff frequencies are defed by: 0 u 2 f f l f f 3dB l db u db 0 db Electronics: a systems approach by N. Storey (13.7) Freq. 11

12 Defitions (9) s S Z Z out j( ) j v e e 0 ; v v ; ; Common Emitter C. Common Collector C. Midband 12

13 Defitions (10) Observation When the small signal conditions are verified the bias conditions are not fluenced by signals present, and the full analysis can be divided to two subanalysis: DC and C. The C analysis is often made by assumg the existence of the termediate band and analyzg the circuit this band, where the reactive effects can be neglected. Therefore, it is important to know the cutoff frequencies that defe the midband. Syntesis of a small signal stage n general, a synthesis process, without the computer aid is carried out takg to account the behavior of the circuit DC and C and estimatg the effect of the capacitors on the cutoff frequencies. t last, the synthesis, of a stage which works at small signal, can be realized the followg steps: 1. Synthesis of the bias network. 2. Change of the bias network to meet the design specifications. 3. Choice of the capacitors to obta the request lower cutoff frequency. 13

14 Small signal amplifiers 14

15 To design an amplifier, that by means of a suitable value, ensure a specific current ga and voltage amplification equal to one. The circuit solution is the: CC common collector stage 1 BJT C2 S s C1 2 E Synthesis steps 1. Synthesize the bias network ( 1, 2, E ). 2. Select the value which ensures the desired current ga. 3. Choose the appropriate values for C1 and C2 which ensure the lower cutoff frequency given the project specifications. 15

16 Synthesis steps: 1 Synthesis of bias network for the CCC Bias network for the CCC 3 resistors 3 relations 1) ( ) CC CE E CQ BQ 1 B 2 base BJT CC E 2) CQ 2 BQ 2 10 BQ 10 h h 2 FE 1 base BEQ E BQ BQ 1 BEQ 1 hfe E 10 BQ 2 1 hfe 10 E CQ FE 2 E 3) 2 CC 1// 2 BQ ( BEQ E ) ( BEQ E ) 1 2 CC BEQ E 1 2 BEQ E 16

17 Synthesis steps: 1 Synthesis steps of bias network: 1) Choose the supply voltage CC and the transistor workg pot: C, CE. 2) From the datasheet BEon and h FE values can be obtaed. BEon =0.66 h FE =210 3) E is obtaed by: E CC C CEQ m 1k 4) 2 is obtaed by: Or: k 2 hfe E 21k 2 15k BE E BE E 2 hfe 10 2 C 5) 1 is obtaed by: CC BEQ E 1 2 BEQ E k 13 k 1 12 k

18 Synthesis steps: 2 is obtaed by the circuit analysis. P // P // hie 1 hfe E // h // P fe E h fe 1 1 E P E f h fe E >> P or h fe E > 10 P h E h 1 fe fe P 1 E h fe 1 h P fe f h fe E > 10 P and h fe >10 P k 6. 8k

19 To perform the and measurements : Mount the circuit troducg a test resistor T //.k T CC Measure T (usg two probes) T 1 BJT C2 Calculate and T T ; S s T C1 2 E Calculate Calculate 20

20 To design a stage which ensures, the passband, the desired voltage amplification. f the load can be selected a possible solution is the: common emitter stage Synthesis steps 1. Synthesize the bias network ( 1, 2, C, E ). 2. Select the value which ensures the voltage ga desired. 3. Choose the appropriate values for C1, C2 and C3 (C3 >> C1 and C2) which ensure the lower cutoff frequency given the project specifications s s C1 1 2 C E BJT CC C2 C3 21

21 Synthesis steps: 1 Synthesis of bias network for the CEC (and CBC) CC 4 resistors 4 relations 1) ( ) CC C C CEQ E CQ BQ 1 CQ c 2) CC E B 2 base 2 BJT E E 3) CQ 2 BQ 2 10 BQ 10 h h 2 FE 1 base BEQ 1 hfe E BQ 2 1 hfe 10 E CQ FE 4) 2 CC 1// 2 BQ ( BEQ E ) ( BEQ E ) 1 2 CC BEQ E 1 2 BEQ E 22

22 Synthesis steps: 1 Synthesis steps of bias network: 1) Choose the supply voltage CC and the transistor workg pot: C, CE. 2) From the datasheet BEon and h FE values can be obtaed. BEon =0.66 h FE =210 3) E is obtaed by: E E CQ CC 20 CQ 1 10m 100 4) C is obtaed by: C CC CEQ E CQ C m 4) 2 is obtaed by: Or: 1 2 hfe E 2. 1k k BE E BE E 2 hfe 10 2 C 5) 1 is obtaed by: CC BEQ E 1 2 BEQ E k 20 k 1 22 k

23 Synthesis steps: 2 is obtaed by circuit analysis. s s C1 1 2 C BJT E CC C2 C3 S s i i i b h ie 1 // 2 i b h fe 1 1 hfe C // hfe h h ie ie C 25

24 To design a stage to ensure, the passband, a voltage amplification f the load is fixed a possible solution is the: common emitter stage with emitter degeneration s C1 1 C BJT CC C2 C3 The emitter resistor is replaced with E //Series (C 3 3 ) to obta different impedance values DC and C. s 2 E 3 Synthesis steps 1. Synthesize the bias network ( 1, 2, C, E ). Same approach of the CEC. 2. Select the 3 value. 3. Choose the appropriate values for C1, C2 and C3 (C3 >> C1 and C2) which ensure the lower cutoff frequency given the project specifications. 26

25 Synthesis steps: 2 CC s C1 1 C BJT C2 C3 S i i i b h ie i b h fe s 2 E 3 s 1 // 2 E // 3 3 hfe C // C // 1 E h 1h // // // // ie fe E 1 1 // 3 C E E 3 C E 3 E

Microelectronics Circuit Analysis and Design

Neamen Microelectronics Chapter 6-1 Microelectronics Circuit Analysis and Design Donald A. Neamen Chapter 6 Basic BJT Amplifiers Neamen Microelectronics Chapter 6-2 In this chapter, we will: Understand