5.25Chapter V Problem Set

Transcription

1 5.25Chapter V Problem Set P5.1 Analyze the circuits in Fig. P5.1 and determine the base, collector, and emitter currents of the BJTs as well as the voltages at the base, collector, and emitter terminals. = 4.7kΩ = 4.7kΩ + R E = 2kΩ 6V β = 50 β = 50 β = 100 R E = 3.3kΩ R E = 3.3kΩ = - a) b) c) Fig. P5.1. BJT circuits for DC analysis. P5.2 Suppose that an inverter in Fig. P5.2 has = 2kΩ, V CC =, and β = 50. During the DC analysis, assume that V BE = 0.7V in the active and saturation regions, and that V CE = 0.2V in the saturation region. a) If it is desired for the transistor to be in saturation whenever V in is greater than 1.5V (when no load is connected at V o), what is the largest allowed value for the base resistor? b) Now assume that = 5kΩ. Sketch the input-output characteristic (V o vs. V in). Label the voltages at which the transistor transitions between the regions of operation. c) With = 5kΩ, what is the output voltage when V in = 1V? d) Suppose that the inverter (with = 5kΩ) is specified for a maximum load current of 0.2mA when the input voltage is V in = V IL = 0.9V. What is the corresponding value of V o = V OH? V cc = 2kΩ V o V in β = 50 Fig. P5.2. Inverter with a BJT. P5.3 Assume that the BJT in the amplifier below has a β value of 20, that the amplifier s frequency response is ideal (i.e., gain-bandwidth product = ), and that the boundary between the reverse and forward bias regions of the base-emitter junction is at 0.7V. Perform large signal analysis with r π = 0 in this problem. a. Plot the input-output transfer characteristics (V o vs. V in). Label the minimum and maximum values as well as the points at which its slope changes. 1

2 b. What is the gain of the amplifier based on the transfer function in the linear range? c. Sketch the output voltage to scale versus time when the input is 1.9V + 0.5V sin(2π 1kHz t). Label the DC value of the output signal, its peak values, and its period. d. Sketch the output voltage to scale versus time when the input is 1.9V + 2V sin(2π 1kHz t). Label the DC value of the output signal, its peak values, and its period. 10kΩ i C C 2kΩ V o V in i B B E Fig. P5.3. DC and transient analysis of a common-emitter amplifier. P5.4 A PNP transistor is operating at room temperature under the conditions annotated in Fig. P5.4. Calculate the value of V B that would result in I DC = 10mA. V B = 9.2V I DC = 1A Fig. P5.4. DC analysis of a PNP bipolar transistor. P5.5 Calculate the DC voltages V 1-V 5 in the circuit of Fig. P5.5 under the assumption that β = 100 for the NPN and PNP BJTs. 9. V 1 Q 1 V 2 5. V 5 100kΩ V 3 Q 2-9. V 4 4.3kΩ - Fig. P5.5. Circuit with an NPN transistor and a PNP transistor. 2

3 P5.6 Calculate the DC voltages V 1-V 6 in the circuit of Fig. P5.6 under the assumption that β = 100 for the NPN and PNP BJTs. 4.7kΩ 5. V 2 V3 2kΩ Q 2 V 4 V 6 Q 1 Q 3 V 1 3kΩ 4.7kΩ kΩ - Fig. P5.6. Circuit with 2 NPN transistors and one PNP transistor. V 5 P5.7 Find the current I x and the voltage V x that are labeled in Fig. P5.7. Assume β = 300 and V BE = 0.7V in this DC analysis. Also show that your assumptions for the operating regions of the BJTs are correct by evaluating the appropriate conditions. 15MΩ Q 2 Q 1 V x I x Fig. P5.7. DC analysis of a circuit with an NPN transistor and a PNP transistor. 3

4 P5.8 Find the small-signal voltage gain A vs = / v s for the amplifier in Fig. P5.8. Assume β = 125, V th = 26mV, r ce =, V BE = 0.7V if the transistor is in active mode, and (V BE = 0.7 V, V CE = 0.2V) if the transistor is in saturation mode. Note: You will have to perform DC analysis and AC analysis to solve this problem. C = 4kΩ C = v s 10kΩ 25.6kΩ 10.4kΩ 18V = 4kΩ Fig. P5.8. BJT amplifier with DC biasing network. P5.9 Assume that β = 100 for the BJT in the amplifier in Fig. P5.9, and that its output resistance (r ce) is high enough to be ignored. a) Draw a small-signal equivalent circuit and derive an expression for the voltage gain (A vs = / v s). Calculate the relevant small-signal parameters to numerically evaluate the expression for the voltage gain. You can assume I EQ I CQ I DC in the parameter calculations. What is the value of A vs? b) Derive the input resistance, and calculate its value. c) Draw a new small-signal equivalent circuit that allows you to obtain an expression for the output resistance. Calculate its value. V CC 0.5mA I DC v O 100kΩ C = C = R S R o 50Ω v S R i Fig. P5.9. Analysis of a common-base amplifier. 4

5 P5.10 From a DC analysis at room temperature (V th = 26mV), the operating point currents in the shown amplifier circuit are: I BQ = 39.27µA I CQ = 3.93mA I EQ = 3.97mA a) Calculate the values of the small-signal parameters r π, g m, and r e. b) Draw the small-signal equivalent circuit. c) Use small-signal analysis to determine the value of the input resistance (R i) at midband frequencies. V CC = C = V DC 4.8V 3.2kΩ I BQ I CQ β = 100 r ce = v i I EQ R i C = R E Fig. P5.10. Small-signal analysis of a BJT amplifier. P5.11 Consider the common-emitter amplifier with an emitter degeneration resistor in Fig. P5.11. a. Draw the small-signal equivalent circuit for the amplifier and derive expressions for the voltage gain A v = /v in and the input impedance (Z in) in terms of r π, β, and resistors. Also write an equation for the voltage gain A vs = /v s in terms of Z in, r π, β, and resistors. Assume that the coupling capacitors (C c) are short circuits for the signal. b. Find the values of I CQ, r π, A v, and Z in at room temperature with V CC =, β = 100, V BEQ = 0.7V, = 270kΩ, =, R E = 100Ω, and =. Repeat the calculations with R E = 0 and prepare a table to compare the results. c. Derive an equation for the output impedance (Z out) of the amplifier. V CC = R S C C C C v s v in R E Z out Z in Fig. P5.11. Analysis of a common-emitter amplifier with an emitter degeneration. 5

6 P5.12 Assume that the coupling capacitors (C c) are short circuits for the signal in the two-stage amplifier in Fig. P5.12. Transistor Q 1 has a β of 50, transistor Q 2 has a β of 100. You can assume for both transistors that V BE = 0.7V and that their collector-emitter resistances (r ce) are high enough to be neglected in the smallsignal analysis. a. Find the DC emitter currents of Q 1 and Q 2 as well as the DC voltages V B1 and V B2 at their bases. b. With a load resistance of connected, determine an expression for the voltage gain from the base to the emitter of Q 2: /v b2 = /v e1. Also find an equation for the input resistance R ib2 looking into the base of Q 2. Evaluate /v b2 and R ib2 numerically. (Hint: Draw the small-signal equivalent circuit and consider Q 2 as an emitter-follower amplifier fed by an input voltage v b2 at the base.) c. Replace Q 2 with its input resistance R ib2 in the small-signal equivalent circuit, where R ib2 is the resistance calculated in part b). Analyze the circuit to determine the resistance (R ib1) looking into the base of Q 1, the input resistance (R in), and the gain (v e1/v b1 = v b2/v b1) from the base of Q 1 to its emitter. d. For the case in which the amplifier is fed by a source (v s) with a series resistance of 100kΩ, find an equation and the numerical value for the gain from the source to the base of Q 1: v b1/v s. e. Calculate the overall voltage gain (/v s). v s 100kΩ R S R in C C R 1 R 2 1MΩ 9V 1MΩ R ib1 50μA 9V -9V Fig. P5.12. Amplifier with two cascaded emitter-follower stages. P5.13 For the emitter-follower in Fig. P5.13, the BJT has a specified range for β of at room temperature. Assuming that the BJT s collector-emitter resistance is large enough to be ignored, find the following quantities and parameters for the two extreme cases (β = 50, β = 300): a. The DC values of I EQ, V EQ, and V BQ. b. The AC input resistance R i at midband frequencies. c. The small-signal voltage gain /v s. Q 1 R ib2 9V -9V Q 2 C C 5mA RL 50kΩ 5kΩ R S v S C C = R i V BQ I EQ V EQ 0.5kΩ R E C C = v O 3kΩ Fig. P5.13. DC and AC analysis of an emitter-follower. 6

7 P5.14 The signal source v s in Fig. P5.14 is a sinusoid with a small amplitude below 10mV and zero average. Assume that β of the transistor is 100, that the coupling capacitors (C c) are large enough to be approximated as short-circuits, and that the amplifier operates at room temperature. a. Find the value of R E to establish a DC emitter current of about 0.5mA. b. Find to establish a DC collector voltage of about +5V. c. For = 10kΩ and r ce = 200kΩ, draw the small-signal equivalent circuit of the amplifier and determine its overall voltage gain (/v s). C c R S = 2.5kΩ C c v s R E - Fig. P5.14. Common-emitter amplifier. P5.15 The BJT in the emitter-follower amplifier in Fig. P5.15 has a β of 100. Assume that a DC analysis has been completed to obtain the following small-signal parameter values: r π = 405.6Ω, r e = 4.02Ω, g m = A/V. You can assume that the collector-emitter resistance is large enough to be ignored (r ce = ). a) Draw the small-signal equivalent circuit, derive the equation for the voltage gain from the input to the output (A v = /v i), and calculate the value of A v. b) Derive an equation for the input impedance (Z i) seen at the node labeled v i in the figure. Find the value of the input impedance. c) Draw a new small-signal equivalent circuit to obtain an expression for the output impedance (Z o) of the amplifier, and calculate its value. 10kΩ R 1 v i C C = C C = Z i 10kΩ R 2 R E Z o 500Ω Fig. P5.15. Small-signal analysis of an emitter-follower. 7

8 P5.16 Setup the test circuit below in PSPICE. Notice that one of the BJT models is Qbreakn and the other one is Q2N2222. a. Setup a DC bias point analysis and place a check mark next to Include detailed bias point information in the output file options of the simulation settings (analysis) window. Run a simulation to determine the values of I C and I B for the Q2N2222 transistor. Calculate the value of β DC based on the DC simulation result. b. Select the Qbreakn transistor in the schematic and choose edit PSPICE model in the menu on the top. To specify a β value of 200, change the statement in the first line to:.model Qbreakn NPN BF=200 Save the model entry and rerun the DC bias point simulation. Make sure that all voltages and currents are labeled before printing out the schematic for submission. Calculate β DC for the Qbreakn transistor based on the DC simulation result. c. Switch to the simulation output window (in which you usually plot results). Choose View output file in the menu on the top. Scroll down to the BJT model parameters and verify that BF is 200 for the Qbreakn device. What is BF in the Q2N2222 model? Scroll down further to find the operating point information, which will be saved when the option is selected as described in part a). Notice that you can find a lot of relevant information in this list, such as V BE, g m, f t, RO (= r ce), RPI (= r π). You can use these DC operating point and small-signal parameters when you want to perform accurate hand calculations. There are two parameters for β in the list: BETADC represents the DC current gain, and BETAAC represents the AC current gain. What are these two parameters for the 2N2222 BJT under the simulated DC bias conditions? Print out the output file and highlight BF, BETAAC, and BETADC for the Q2N2222 transistor. d. Find a datasheet on the internet for a 2N2222 transistor from any manufacturer. Print out the page that that reports the DC current gain (β) for the BJT. Highlight the case (value of β) that is the most appropriate estimate under the given DC bias conditions in the example circuit. Is your simulation result close to this value? Fig. P5.16. Test circuit for DC simulations and operating point inspection with PSPICE. 8

9 P5.17 Analyze the circuit in Fig. P5.17 under the assumption that β = 100 for both BJTs. a. Use hand calculations to find I x and V o. b. Verify the hand calculation result with PSPICE by using the QbreakN and QbreakP models with BF = 100. (See problem P5.16 for details how to specify BF in the device model.) Print out the schematic that shows the voltage and currents from the DC bias point simulation. Note that the small difference between the hand calculation and simulation results in this case is mainly caused by the V BE difference of the PNP device. (You can look up the V BE values of the transistors in the DC operating point information of the output file as described in problem P5.16.) c. If the base current of the NPN transistor is increased (by reducing the 15MΩ resistor), then the NPN transistor will remain in active mode because its collector voltage changes negligibly due to the almost constant emitter-base voltage drop of the PNP transistor. However, the voltage at the collector of the PNP transistor will increase as a result of the corresponding increase of I x. (The PNP collector current is an amplified version of the NPN base current). The PNP collector voltage increase will move the operating point of the PNP device closer to the saturation region. Calculate the minimum value for that ensures that the PNP transistor is still in active region (at the edge of saturation region). Check your result in PSPICE, and print the schematic that shows the currents/voltages with this calculated minimum resistance value. 15MΩ V o I x Fig. P5.17. DC analysis and simulation of a circuit with an NPN transistor and a PNP transistor. P5.18 Consider the circuit in Fig. P5.18. a. DC analysis and design: Assume that a DC operating point (Q-point) value for the collector current (I C) between 4mA and 5mA is required to ensure proper ranges for small-signal parameter values, and that β can vary between 100 and 300. (This means that I C should be 4mA when β = 100, and equal to 5mA when β = 300 to guarantee: 4mA I C 5mA). Find values for and R E that satisfy the requirements. b. Small-signal parameter calculation: Calculate the small-signal parameters g m, r π, and r ce at room temperature (300K), assuming that the Early voltage (V early = V A) is 100V. Use the maximum I C and minimum I C cases from part a) in the calculations to determine the expected ranges of the smallsignal parameter values. c. Draw the small-signal equivalent circuit using the hybrid-π model that includes the parameters from part b). FYI: This is the circuit that you would use for AC analysis at mid-band frequencies (gain, input/output impedance, etc.). d. Set up the circuit with your calculated values in PSPICE, and simulate it to verify your results. Use the procedure described in homework 5 to model the BJT with the Qbreakn device model and a specified value of β. Submit the schematics that show the collector current values for the minimum and maximum cases in part a). Next, sweep the DC bias voltage at the base (V BB) of the BJT from 0 to using the Q2N2222 transistor model for the BJT. Plot the DC transfer characteristic curve at 9

10 the collector (V C vs. V BB), and label the voltages at which an output signal at the collector would begin to clip. Submit the labeled plot. What is the maximum peak-peak output voltage swing that can be achieved when the Q-point is in the middle of the linear range? v i C c = V C C c = L BB = V BB 5V R E Fig. P5.18. Example amplifier for DC analysis, operating point design, and PSPICE simulations. P5.19 Setup the circuit in Fig. P5.19 in PSPICE using the Q2N2222 BJT model and the following component parameters: R 1 = 700kΩ, R 2 = 300kΩ, = 3kΩ, R E = 200Ω, = 10kΩ, C C1 = C C2 = C C3 = 5µF a. Run a DC simulation to verify that the BJT is operating in active mode. Inspect the DC operating point information of the BJT (as described in problem P5.16), and record the transconductance parameter (GM). Notice that the expected AC gain for this amplifier configuration is: A v - g m ( ) because R 1 R 2 >> r π. Submit a print out of the schematic in which the DC voltages and currents are displayed. Also print the DC operating point information of the BJT. b. Run an AC simulation from 1Hz to 100MHz using a logarithmic sweep with 20 points per decade. Plot the AC voltage gain (/ vs) in db-scale vs. frequency. Label the midband frequency gain (in db) and the 3-dB frequencies (low corner frequency and high corner frequency) in the plot before printing it out for submission. What is the midband voltage gain as a ratio (not in db)? c. Setup a transient simulation with a sinusoidal input at 100kHz that has a 2mV amplitude. Use a 0.1µs maximum time step and a simulation time of 50µs. Plot the input and output signals vs. time, and mark the peak amplitudes in the plots. What is the gain based on the transient simulation? Does it agree with the AC gain in part b)? d. Increase the input signal amplitude to 20mV and repeat the transient simulation. Plot the output signal. Can you notice the distortion? Which condition is not satisfied? (i.e., What causes the distortion)? e. Remove the capacitor C C3 from the schematic and repeat the AC simulation with the same range as in part b). Label the midband frequency gain (in db) and the 3-dB frequencies (low corner frequency and high corner frequency) in the plot before printing it out for submission. What is the midband voltage gain as a ratio (not in db)? Repeat the transient simulation with 20mV input amplitude at 100kHz [as in part d)] without C C3, and submit a plot of the output voltage vs. time in which the peak amplitude is labeled. What is the gain based on the transient simulation? 10

11 V CC = C C1 R 1 C C2 v s R 2 C 3 E Fig. P5.19. Common-emitter amplifier for DC, AC, and transient simulation with PSPICE. P5.20 Analyze the circuit in Fig. P5.20 under the assumption that β = 100 for both BJTs. a. Calculate the DC voltages V 1-V 5 using DC analysis with a V BE voltage drop of 0.7V when a transistor is forward-biased. b. Verify the result with PSPICE by using the QbreakN and QbreakP models with BF = 100. (See problem P5.16.) Print out the schematic that shows the voltage and currents from the DC bias point simulation. Note that the small differences between the hand calculation and simulation results in this case are mainly caused by the V BE differences of the transistors in comparison to the assumed 0.7V for the forward-biased case in hand calculations. (You can look up the V BE values of the transistors in the DC operating point information of the output file as described in P5.16.) V 1 100kΩ 9. V 3 - Q 1 V V 5 Q 2 V 4 4.3kΩ - Fig. P5.20. DC analysis and simulation of a circuit with a PNP transistor and an NPN transistor. 11

12 P5.21 Consider the circuit in Fig. P5.21, and assume that V BE = 0.7V and β = 100. a. DC analysis: Find the values of R 1 and such that the bias point is with V CE = 5V and I C = 2mA. b. Set up the circuit with your calculated values in PSPICE, and simulate it to verify your results. Use the procedure described in prob. P5.16 to model the BJT with the Qbreakn device model and a specified value of β. To avoid error messages related to the floating terminals of the capacitors at the input and output, you can connect 10GΩ resistors from v i and to ground. Alternatively, you can simulate the circuit without the capacitors to obtain the DC operating point information. Submit the schematics that show the DC collector current value. c. Small-signal parameter calculation: Calculate the small-signal parameters g m, r π, and r ce at room temperature (300K) based on the results from part a), assuming that the Early voltage (V early = V A) is 100V. d. Draw the small-signal equivalent circuit using the hybrid-π model that includes the parameters from part c). e. Replace the Qbreakn BJT model with the Q2N2222 model. Simulate the circuit again and submit a schematic that shows the DC current of the new operating point. Sweep the DC bias voltage at the base (V BB) from to 20V using the Q2N2222 transistor model for the BJT. Plot V C vs. V BB, and label the V BB value at which V C is equal to 5V. Submit the labeled plot. I R v i C c = 500μF R 1 V C I C C c = 500μF V CE 100kΩ R 2 V BB Fig. P5.21. Common-emitter amplifier. 12

13 P5.22 1) Consider the dual supply bias arrangement shown in Fig. P5.22 using ±3V for +V CC and -V EE. Assume that it is required to design the circuit so that I C = 3mA while V C = 0V (placed midway between +V CC and -V EE). a. With β =, what values are required for R E and? b. If the BJT is specified to have a minimum β of 90, find the largest value for which still ensures that the voltage drop across is one-tenth of the voltage drop across R E. c. What standard 5%-resistor values would you use for, R E, and? Make your selection such that the resistance values are somewhat lower than the calculated values to allow for the effects from low β. d. For the values you selected in part c), find I C, V B, V E, and V C for β = and for β = 90. e. Simulate your design in PSPICE to check it with the values from part c). Use the procedure described in problem P5.16 to model the BJT with the Qbreakn device model and a specified value of β. Run one simulation with β = 90 and another one with β = 400, and submit the print outs of the schematics with displayed DC voltages and currents. +V CC V C R E -V EE Fig. P5.22. A BJT biased with two supply voltages. P5.23 Set up the circuit in Fig. P5.23 in PSPICE using the Q2N2222 BJT model and the following component parameters: R 1 = 175kΩ, R 2 = 125kΩ, = 1.2kΩ, R E = 200Ω, = 8kΩ, C C1 = C C2 = C C3 = 5µF a. Run a DC simulation to verify that the BJT is operating in active mode. Inspect the DC operating point information of the BJT (as in problem P5.16), and record the transconductance parameter (GM). Notice that the expected AC gain for this amplifier configuration is: A v -g m ( ) because R 1 R 2 >> r π. Submit a print out of the schematic in which the DC voltages and currents are displayed. Also print the DC operating point information of the BJT in the output file (.out). b. Run an AC simulation from 1Hz to 100MHz using a logarithmic sweep with 20 points per decade. Plot the AC voltage gain (/ vs) in db-scale vs. frequency. Label the midband frequency gain (in db) and the 3-dB frequencies (low corner frequency and high corner frequency) in the plot before printing it out for submission. What is the midband voltage gain as a ratio (not in db)? c. Set up a transient simulation with a sinusoidal input at 300kHz that has a 0.5mV amplitude. Use a 0.1µs max. time step and a simulation time of 20µs. Plot the input and output signals vs. time, and mark the peak amplitudes in the plots. What is the gain based on the transient simulation? Does it agree with the AC gain in part b)? d. Increase the input signal amplitude to 10mV and repeat the transient simulation. Plot the voltages at the collector terminal of the BJT and at the output (across ). Can you notice the distortion? Which condition is not satisfied? (i.e., What causes the distortion?) e. Remove the capacitor C C3 from the schematic and repeat the AC simulation with the same range as 13

14 in part b). Label the midband frequency gain (in db) and the 3-dB frequencies (low corner frequency and high corner frequency) in the plot before printing it out for submission. What is the midband voltage gain as a ratio (not in db)? Repeat the transient simulation with 10mV input amplitude at 300kHz [as in part d)] without C C3, and submit a plot of the output voltage vs. time in which the peak amplitude is labeled. What is the gain based on the transient simulation? V CC = 20V C C1 R 1 C C2 v s R 2 C 3 E Fig. P5.23. Common-emitter amplifier for DC, AC, and transient simulation with PSPICE. P5.24 Consider the circuit in Fig. P5.24 at room temperature, in which the common-base amplifier is coupled to a 20kΩ load resistor () through a large capacitor. The voltage signal source has a resistance of R S = 100Ω. Assume that β is large (α 1). a. Design the circuit so that the amplifier input impedance (Z i) is matched (identical) to that of the source. Ensure that the BJT operates in active mode when the AC voltage v be (across the base and emitter terminals) is limited to 10mV (peak amplitude) to guarantee linear operation according to the small-signal approximation requirement. Assuming that the maximum input voltage amplitude specification guarantees that v in(max) = v be(max) = 10mV, select the value of as large as possible while avoiding that the output signal is clipped due to voltage swing limitations. Such a choice for will maximize the voltage gain. In your particular design, what are the minimum and maximum instantaneous voltages (DC + AC) at the collector (V C) of the BJT that correspond to the maximum input condition ( v be(max) = 10mV)? Clearly identify these voltages as well as the values of and I DC in your design. b. What is the voltage gain (A v = / v in) of the amplifier that you designed? What is the gain from the source to the output (A vs = / v s)? c. Setup the circuit in PSPICE using the Q2N2222 model for the BJT. Verify with an AC simulation that your voltage gain A vs = / v s agrees with your hand calculation with reasonable error. Submit the plot of the voltage gain (as a ratio, not in db) vs. frequency. d. Verify that your simulated input impedance is close to 100Ω by inserting an ideal AC voltage source (without R S, but with the coupling capacitor C c) directly at the amplifier input (v in). After running an AC simulation with a frequency sweep, you can plot the absolute value of the ratio of the test voltage source and its AC current at the terminal vs. frequency in order to obtain the plot of Z in = v test/i test vs. frequency. Submit this plot with a label that should show an input impedance magnitude close to 100Ω for midband frequencies. e. Reinsert resistor R S to revert to the same configuration as in part c), and select the input voltage amplitude of v s (a 100kHz sinusoidal signal) that results in a peak v be amplitude of 10mV. Verify 14

15 with a transient simulation that your output voltage is undistorted. Also compare your minimum and maximum voltages at the collector terminal with those calculated in part a). Submit the plots of the source voltage (v s), input voltage (v in), collector voltage (V c), and output voltage () across the load resistor (all vs. time). Calculate the voltage gain A vs from the transient simulation to check that it agrees with the gain from the AC simulation. +3V V C v O R S C C =200µF C C (200µF) v in v S I DC Z i -3V Fig. P5.24. Common-base amplifier: design for a particular input impedance and simulation with PSPICE. 15