[Mojlish, 3(2): February, 2014] ISSN: Impact Factor: 1.852

Transcription

1 JESRT NTERNATONAL JOURNAL OF ENGNEERNG SENES & RESEARH TEHNOLOGY Design of a Photovoltaic Grid-Tied nverter Employg a Dual-Stage Boost onverter and a Transformer-Less Step-Down ircuit Sameer Ahmed Khan Mojlish Lecturer, Department of Electrical & Electronic Engeerg, ndependent University, Bangladesh sameer_buet@yahoo.com Abstract This paper proposes a topology for a transformer-less, pure se wave grid-tie verter (GT) for photovoltaic (P) application. The proposed GT employs a dual-stage boost converter, a transformer-less step down circuit, an H-bridge verter and a T-LL mmittance conversion circuit. The switchg technique of the proposed verter consists of a combation of susoidal pulse width modulation (SPWM) and a square wave along with grid synchronizg conditions. As the suggested method is entirely transformer-less, it significantly reduces the total harmonic distortion (THD) of the put voltage (less than.%), mimizes its size and swells the verter efficiency up to 97%. The T-LL mmittance conversion circuit not only reduces the harmonics of the verter put but also provides a nearly constant put current thereby stabilizg the system rapidly. The overall performance of the proposed verter is simulated usg PSM usg the designed values of circuit components. The simulation results show that the proposed verter is capable of not only elimatg harmonics but is also highly efficient, compact and cost effective. Keywords: Boost onverter, Step- down ircuit,t-ll mmittance onverter, Grid-Tie nverter (GT) ntroduction The changg world climate is a serious for frequency synchronization. But transformers are threat to our planet. The global warmg bulky, costly equipment contributg significantly to phenomenon, driven by the emission of carbon dioxide (O2) from the use of fossil fuels is slowly killg our planet. Moreover, the cost of fossil fuel is also creasg day by day and its sources are gradually becomg exhausted. Therefore the use of fossil fuel is not a long-term solution to the prevalent power crisis Bangladesh. As Bangladesh receives a lot of sunlight, therefore implementg a highly efficient and cost effective solar module can be an effective means to combat power crisis by producg large amounts of power at low cost. n photovoltaic (P) system, solar energy is converted to electrical energy through P arrays. There are two mandatory tasks a P system () utilizg maximum energy from P arrays. (2) Usg the most reliable, highly efficient and cost effective Total Harmonic Distortion (THD) of the put voltage [3]. n this paper, a transformer-less voltage divider circuit is employed to step down the grid voltage for frequency synchronization purposes. Further, unlike the conventional low pass L filter, a T-LL mmittance onverter is used at the put of the proposed verter, which besides suppressg the harmonics also helps to mata a constant put current. [4] The proposed verter consists of five ma parts () A P array for solar energy to electrical energy conversion. (2)A dual stage D-D boost converter to step-up P array voltage to grid level. (3)An H-bridge D-A converter to obta A voltage. (4) A T-LL mmitance converter to deliver a nearly constant and filtered current. (5) A configuration for the power converter to supply only transformer-less step-down A-D conversion pure susoidal current to the grid []. n circuit which is used to produce gate pulses for conventional verters, boost converters are used to step up the voltage at the put of the P array to the grid voltage. Sce a sgle-stage boost converter requires a high duty cycle which is convenient for verter switchg by combg SPWM and square wave signals. The block diagram of the proposed verter configuration is shown below. MOSFET s switchg; therefore a dual stage boost converter is used to get a duty cycle suitable for MOSFET switchg. Also conventional verters, transformers are used to step down the grid voltage

2 Desired put voltage.35 ripple(.% of put voltage) Maximum put current.4a -: Block diagram of verter configuration Design of Dual-Stage Boost onverter n this section, the design of a dual stage D-D boost converter is presented which steps up the P array voltage to a fixed high level grid voltage (32 peak or 22 rms Bangladesh). n this paper, the dual stage (N2) boost converter is proposed sce the duty cycle of a sgle stage would be large (above 9%) which is not suitable for MOSFET s switchg [6].The dual stage converter provides a more symmetrical duty cycle and reduces the voltage stra on the MOSFETs. Here the conversion is done based on the conversion ratio, x 2 32/24 which converts 24 to 86 the first stage and 86 to 32 the second stage the design parameters of the first and second stages are listed Table- and Table- respectively. Table-: Design of first stage boost converter Symbol Actual meang alue Given put voltage 24 Desired average put 86 voltage f s Switchg frequency of converter 2KHz L,max Maximum ductor 26A current i L Estimated ductor ripple 4.55A current(.75% of L,max ) Desired put voltage 44m ripple(.5% of put voltage) Maximum put current 4.3A Table-2: Design of second stage boost converter Symbol Actual meang alue Given put voltage 86 Desired average put 32 voltage f s Switchg frequency of converter 2KHz L,max Maximum ductor 23A current i L Estimated ductor ripple current(26% of L,max ) 6A Duty ycle Maximum duty cycle of first stage is, D Maximum duty cycle of second stage is, D nductor Selection The ductor values are selected usg the followg equation [7] So, ( ) L L f s 24 ( 86 24) L 9µH ( 32 86) L2 5µH and apacitor Selection The capacitor values are selected usg the followg equation [7] and So, D f s mf mF The designed D-D Boost onverter The puts of the first and second stages of the boost converter usg PSM simulation are shown Fig2 and Fig3 respectively. The figures show that 24 has been boosted up to 32.

3 [Mojlish, 3(2): February, 24] SSN: Fig-6: 7.7 peak (5 rms) put voltage Fig-2: Boost converter put of the first stage Fig-3: Boost converter put of the second stage Design of the Transformer-Lesss Step down ircuit The step down operation is performed usg a voltage divider. Settg Fig-4: oltage divider circuit Usg voltage divider equation, [7] v R2 v R+ R2 v 32 ; v 7.7;R kω solvg for R2, we get R22.32KΩ. The put voltage (32peak; 22 rms) and the put voltage (7.7peak; 5 rms) are shown Fig 5 and Fig 6 respectively. The figures show that 32 has been stepped down to 7.7. Fig-5: 32 peak (22 rms) put voltage and Fig-7: Proposed transformer-less grid-tie verter Proposed Grid-Tie nverter Design Grid Synchronization The put voltage of a grid-tied verter should mata some fixed requirements so that it may provide power to grid [2]. The requirements are given below: i. The amplitude of the put voltage should be equal to the amplitude of the grid voltage. ii. The frequency of the verter should be equal to the grid frequency (5Hz Bangladesh). n the proposed design, these conditions are achieved by samplg the grid frequency and usg it to generate the switchg signal. The GT is connected to the power grid where the load is much higher as compared to the GT. This means that the GT has to force the power from the P array to the grid. The real power is given by [2] v grid Real Power P si φ, where t t Lkg le impedance v Output voltage of verter grid Grid voltage ϕ Angle between v and grid. From the above equation, it is clear that maximum real power can be transmitted to the grid for ϕ9 degrees. f sϕ is positive, then real power flows from the GT to the grid; if sϕ is negative, then real power follows the reverse direction. Power ircuits The schematic circuit diagram of the proposed verter is shown Fig7. The D-D dual-stage boost converter steps up P array voltage from 24 to 32. The H-Bridge D-A verter has two parallel MOSFET gates. A combation of analog and digital circuits is used to produce the gatg pulses of the MOSFETs.

4 [Mojlish, 3(2): February, 24] Switchg/ontrol ircuit n conventional verters only one type of switchg technique is used. But this proposed design stead uses a combation of SPWM and square wave to reduce the switchg loss by reducg the switchg frequency. Fig 8 shows the proposed switchg circuit of the GT. The se wave is sampled from the grid by usg a transformer-less voltage divider circuit which steps down the voltage from 22 (rms) to 5(rms).The se wave sampled is used to generate the SPWM signal thus ensurg that the put voltage from the GT will have the same frequency as the grid [5]. After samplg, the se wave is rectified with a precision rectifier, the put of which is shown Fig 9. Fig-8: ontrol circuit of proposed GT SSN: Fig-: Square wave signals The verter requires four switchg signals sce it has four MOSFETs. To produce the four signals, an AND operation is performed between two sets of square wave signals and the SPWM signal. The four sets of switchg signals can be categorized two groups. The first group contas MOSFETs Q and Q4 while the second group contas MOSFETs Q2 and Q3. The gate pulses for switchg of MOSFETs are illustrated Figs 2 and 3 respectively. When Q4 is ON, Q is switched ON with the SPWM signal and both Q2 and Q3 are OFF. This produces a positive voltage at the verter put. When Q3 is ON, Q2 is switched ON with the SPWM signal and Q and Q4 are both OFF. This produces a negative voltage at the verter put. Fig-9: Rectified se wave n addition, a high frequency triangle wave of KHz is used. Then the two signals are passed through a comparator to produce the SPWM signal as shown Fig. A square wave signal is used as the le frequency (5 Hz for Bangladesh) and is phase with the SPWM as shown Fig.The square wave is passed through a NOT gate to produce a signal that is 8 degree of phase with the origal signal. Fig-2: Switchg signal from control circuit for MOSFETs (Q and Q4) Fig-3: Switchg signal from control circuit for MOSFETs (Q2 and Q3) Filter ircuit To elimate harmonics from the verter put, a filter circuit is employed. n conventional Fig-: SPWM signal verters, L filter is used but this design employs a T-LL mmitance onverter. The filter circuit consists of two ductors L and L 2 and a capacitor

5 the shape of a T as shown Fig 7. From the derivation of the equation of the put current of the filter, 2 is found as [4]: 2 2 [ Q ]...() Where is the put voltage, 2 is the load impedance and Q is the quality factor, Q ωl... r ( 2) With ω2π f as the angular frequency, r is the ternal resistance of the ductor and is the characteristic impedance determed by L and, L. (3) When r is negligible or zero, the quality factor becomes fity. Under this condition, 2...( 4) From eq. (4), it is observed that the put of the T- LL filter is dependent of load. Therefore this filter is capable of not only reducg harmonics but is also helpful providg a constant current to the load. The values of L and of T-LL filter (considerg Butterworth type) is calculated usg the cut-off frequency condition of low pass filters, i.e. 2πf c...( 5) where is the characteristic impedance given by Eq. (3). Assumg as 2Ω and choosg f c 5Hz, we get the values of L and usg Eqs. (3) and (5), 2 π mF And L mH Power Transmittg oltage angle of GT must lead grid voltage angle to transmit power to grid. To achieve this, the sampled se wave from the grid is passed through a phase shifter circuit to make the leadg adjustments. As mentioned earlier, to send maximum power to the grid, the leadg angle must be 9 degrees. But practice, due to stability reasons the angle is kept somewhat less than 9 degrees. [5] elimate these harmonics, a low pass T-LL filter is employed at the put of the verter which produces a pure, susoidal voltage. After filterg, we obtaed a pure susoidal voltage of frequency 5Hz and of rms value 22 as shown Fig 5. Fig-4: Output voltage with filterg PSM. Fig-5: Output voltage after filterg PSM nverter Output urrent The peak value of the verter put current is an important factor designg the verter stack size. The verter current ratg is normally determed by the filter impedance and the rated load impedance a steady-state. Fig. 6 shows the put current. Fig-6: Output current waveform PSM n order to test the performance of the verter, the load current was measured for both R and RL load with and with usg the filter circuit. The load impedance was varied from 5Ω toω for both R and RL load by considerg the characteristic impedance as 2Ω. t was observed that the load current with filter varies a large range than the current with the filter circuit employed as shown Fig 7. t is also observed that the load current for both resistive and ductive load remas almost constant which confirms that the put current is nearly dependent of load for a T-LL filter. Simulation Results nverter Output oltage Fig. 4 shows the put voltage waveform the absence of any filter. The waveform is nonsusoidal and contas lots of harmonics. To

6 Fig-7: Output current vs. load impedance nverter Efficiency The verter efficiency is calculated usg the followg formula: P η P %. (6) where P and P are the put and put powers of the verter respectively. By varyg the load impedance, the verter efficiency was measured for the T-LL filter as shown Fig 9. The graph shows that the verter efficiency is over 9% for the entire load range with a peak value of nearly 97%. Fig-8: Efficiency vs. load impedance References [] H.N.audd and S.Mekhilef, omparison study of maximum power pot tracker techniques for P systems, Proc. 4 th nternational Middle East Power Systems onference, airo University, Egypt, December, 2 [2] T.K.Kwang and S. Masri, Sgle phase grid tie verter for photovoltaic application, Proc. EEE Sustaable Utilization and Development Engeerg and Technology onf, November 2 [3] N.Kasa and T.ida, A transformer-less sgle phase verter usg a buck-boost type chopper circuit for photovoltaic power system, Proc. PE 98, Seoul, Korea, 998 [4] S.B. Afzal, M.M. Shabab and M.A.Razzak, A combed Π- and T-type immitance converter for constant current applications, Proc. EEE nternational onference on nformatics, electronics and vision (E), May 23, Dhaka, Bangladesh [5] A.S.Kamal howdhury and M.A.Razzak, sgle phase grid connected photovoltaic verter for residential application with maximum power pot trackg, Proc. EEE nternational onference on nformatics, Electronics and ision (E), May 23, Dhaka, Bangladesh [6] ed on July 23 [7] M.H.Rashid, PowerElectronics, ircuits, Devices and Applications, 3 rd ed, New Delhi: Prentice-Hall of ndia private limited, 27 onclusions This paper presents a transformer-less P grid-tie verter for residential application, the put of which is 22 rms at a frequency of 5Hz. The PSM simulation results confirm these. The power loss the transformer-less circuit is only 473mW which is much less than the loss curred with a transformer. The total harmonic distortion of the put voltage is.% which is much lower than the EEE 59 standard and the efficiency of the verter swells up to 97%. Therefore the proposed verter design is highly efficient, cost-effective and compact due to beg transformer-less and provides a near constant current which ensures stability.