Single-Stage High-Power-Factor Electronic Ballast with a Symmetrical Class-DE Resonant Rectifier

Transcription

1 Sgle-Stage High-Power-Factor Electronic Ballast with 49 JPE Sgle-Stage High-Power-Factor Electronic Ballast with a Symmetrical Class-DE Resonant Rectifier Chaar Ekkaravarodome and Kamon Jirasereeamornkul * Dept. of Instrumentation and Electronics Engeerg, Kg Mongkut s University of Technology North Bangkok, Bangkok, Thailand * Dept. of Electronic and Telecommunication Engeerg, Kg Mongkut s University of Technology Thonburi, Bangkok, Thailand Abstract This paper presents the use of a novel, sgle-stage high-power-factor electronic ballast with a symmetrical class-de low-dυ/dt resonant rectifier as a power-factor corrector for fluorescent lamps. The power-factor correction is achieved by usg a bridge rectifier to utilize the function of a symmetrical class-de resonant rectifier. By employg this topology, the peak and ripple values of the put current are reduced, allowg for a reduced filter ductor volume of the EMI filter. Sce the conduction angle of the bridge rectifier diode current was creased, a low-le current harmonic and a power factor near unity can be obtaed. A prototype ballast, operatg at an 84-kHz fixed frequency and a -V rms, 5-Hz le put voltage, was utilized to drive a T8-36W fluorescent lamp. Experimental results are presented which verify the theoretical analysis. Key words: Class-DE resonant rectifier, Electronic ballast, Power-factor correction, Sgle-stage I. INTRODUCTION High-frequency resonant verters have played a very important role the development of gas-discharge lamps, especially fluorescent lamps, sce they can improve the light quality and prolong the lamp lifetime [1]. Most electronic ballasts use class-d resonant verters because they can provide a high strikg voltage durg startup. In addition, they provide current-limitg control to allow for steady-state operation with a low crest factor for fluorescent lamps. However, this type of circuit causes a large and sharp put current when the put ac source voltage reaches its peak. The distorted current waveform affects the power quality and results a lower total power factor. In order to alleviate this drawback, a power-factor correction (PFC) circuit must be attached to the electronic ballast, thus reducg the harmonics the utility le current and satisfyg the IEC class-c standard for lightg equipment. The high-power-factor, electronic ballast is developed usg a two-stage circuit, which has been presented previous Manuscript received Jun. 14, 11; revised Apr. 9, 1 Recommended for publication by Associate Editor Yong-Chae Jung. Correspondg Author: chaare@kmutnb.ac.th Tel: , Fax: , KMUTNB * Dept. of Electronic and Telecommunication Engeerg, Kg Mongkut s University of Technology Thonburi, Thailand studies []-[5]. The ma problem associated with a two-stage electronic ballast is the creasg number of components it requires, which results higher costs. Recently, many researchers have focused on a sgle-stage approach which the power-factor-corrector stage and the dc/ac resonant verter stage are tegrated to sgle-stage electronic ballasts (SSEBs) [6]-[17]. However, most sgle-stage electronic ballasts use a large electromagnetic terference (EMI) filter due to the high levels of harmonic distortion from le put current, makg this ballast unattractive for commercial applications. The objective of this paper is to troduce a new SSEB topology which a symmetrical class-de rectifier is used as a power-factor corrector while the volume of the ductor the EMI filter is reduced. This paper is organized as follows. In Section II, the circuit description is presented. In Section III, the prciple of operation is described. The design procedure for the components is presented Section IV. Simulation and experimental results to support the theoretical analysis are presented Section V. In Section VI, a simplified circuit is presented. Some conclusions are given Section VII. II. CIRCUIT DESCRIPTION Figure 1 shows the circuit of the proposed sgle-stage electronic ballast. The circuit consists of a filter ductor, L f,

2 43 Journal of Power Electronics, Vol. 1, No. 3, May 1 i L D1 D f i CDE 1 CDE1 i d i CDE CDE D3 C D DE1 4 C DE C d1 i C d d Ld M 1 M i M 1 DS1 Lr i M DS ir C r CC i L R L L C B Small EMI Filter Class-DE Rectifier Matchg Network Class-DInverter Fig. 1. Proposed electronic ballast with symmetrical class-de resonant rectifier as a PFC stage. a bridge rectifier, D 1 D D 3 D 4, and two high-frequency capacitors, C DE1 and C DE, which are connected parallel with the two diodes, D 3 and D 4, of the bridge rectifier order to form a symmetrical class-de resonant rectifier. Additionally, an ductor,, and two capacitors, C d1 and C d, serve the function of high-frequency current shapg, while couplg capacitors and a bulk-filter capacitor, C B, supply the class-d parallel resonant verter. The voltage,, across this capacitor is nearly constant, which results constant lamp current and voltage amplitudes, and a class-d parallel resonant verter, L r C r C C R L. All power switches are operated under the zero-voltage switchg (ZVS) condition. The matchg network, C d1 C d, is fed by a square-wave output voltage from the class-d resonant verter and is converted to a high-frequency current source to drive the symmetrical class-de rectifier. III. PRINCIPLE OF OPERATION The prciple of operation of the symmetrical class-de resonant rectifier the PFC stage is demonstrated by the equivalent circuit shown Fig. (a). The diodes, D 1 and D 4, of the bridge rectifier operate durg the positive half-cycle of the le voltage, which is represented as V s Lt, where L is the le angular frequency and the diodes, D and D 3, operate durg the negative half-cycle. The model of the le-voltage rectifier output is a full-wave rectified susoidal voltage source (i.e., V s t ). Because the dc voltage L source,, appears as a short circuit to the ac component, the capacitor, C DE1, and the high-frequency current source,, can be connected parallel with D 1, as shown Fig. (b). In addition, the parallel connection of D 1, C DE1, and the high-frequency current source,, is connected series with the voltage source,. The order of these elements is terchangeable, as shown Fig. (c). In this circuit, the D1 D i CDE1 D D 3 4 CDE C DE1 C DE i i d1 CDE1 i CDE1 C DE1 D 1 D 4 (a) (c) voltage sources and are connected series and can be combed to an output voltage, O = VB, of the class-de rectifier, as can be seen Fig. (d). The output characteristics of the symmetrical class-de low-dυ/dt rectifier with a varyg resistive load roughly match the conceptual waveforms of the proposed PFC shown Fig. 3. Fig. 3(a) shows the susoidal le-voltage waveform. Fig. 3(b) and (c) show the rectified le voltage,, and the combed voltage waveform, VB, respectively. If the stantaneous value of is positive and low, the voltage of the class-de lowdυ/dt rectifier, V, is high, and the duty ratio, D d, of the B i CDE CDE C DE i d i d C DE1 V O B D1 D i D3 D4 i O D 1 D 4 (b) i D4 (d) C DE i CDE1 CDE1 C DE1 i CDE CDE C DE Fig.. Circuit derivation of the PFC with a symmetrical class-de rectifier durg the positive half-cycle of the le voltage: (a) equivalent circuit; (b) equivalent circuit when movg the capacitor (C DE1 ) and the current source ( ); (c) equivalent circuit when movg D 1, C DE1,, and ; (d) equivalent, symmetrical circuit with a combed voltage source, VB. i d i d

3 Sgle-Stage High-Power-Factor Electronic Ballast with 431 rectifier diode current is low. Therefore, the average value of the rectifier diode current over one switchg cycle is low. Conversely, if the stantaneous value of is positive and high the voltage of the class - DE rectifier,, is low, and the duty ratio, D d, of the rectifier diode is high. Thus, the average value of the diode current over one switchg cycle is high. For a half-cycle with a negative le voltage, the bridge rectifier rectifies the negative values of to positive values and rectifies those of the diode duty ratio as a half-cycle with a position le voltage. The conduction angle modulation of the rectifier diode over the le frequency, f L, and the le-put current, i, are shown Fig. 3(d). The idealized current and voltage waveforms a class-de low-dυ/dt rectifier are shown Fig. 4. Current flows through diodes D 1 and D 4 when each diode is ON and it passes through capacitors C DE1 and C DE when the diodes are OFF. The diodes beg to turn off when their current reaches zero. The current passg through the capacitors, C DE1 and C DE, shapes the voltage across the diodes accordance with the equation icde CDEd ( CDE )/ dt. Because icde1 and i CDE are zero at turn-off, each diode turns off at dυ/dt =. The diodes turn on at a low dυ/dt to reduce the turn-on switchg loss and noise. The prciples of operation of the class-d parallel resonant verter the proposed circuit are explaed by the equivalent circuit Fig. 5(a). The put impedance of the class-de rectifier is represented by a series combation of the put resistor, R i, and the put capacitor, C i, as shown Fig. 5(b). The capacitor, C r, and the lamp resistance, R L, are converted to a series R s C rs circuit, as shown Fig. 5(c). The C d C i circuit is replaced by an equivalent capacitor, which is represented as C di = C d C i / (C d +C i ). The MOSFETs are modeled by switches with the on-resistances, r DS1 and r DS. The resistances, r Ld and r Lr, represent the equivalent resistances of the ductors, and L r, respectively. The equivalent circuits of the class - D parallel resonant verter are modeled by a square-wave voltage source, S, with an equivalent resistor, rs rds1rds / rds, and are loaded by two sub-circuits, r Ld R i C di and r Lr R s L r C rs. The proposed electronic ballast can be divided to two parts: a PFC semi-stage and an verter semi-stage. Fig. 6(a) shows an equivalent circuit of the PFC semi-stage. Fig. 6(b) depicts a simplified circuit of the PFC symmetrical class-de low-dυ/dt rectifier. Fig. 6(c) shows an equivalent circuit of the verter semi-stage. From Fig. 6(a), the mimum value of the load resistance, R DEm, occurs at the mimum output voltage, Om, as does the maximum output current, i Omax, of the symmetrical class-de low-dυ/dt rectifier. The mimum load resistance, R DEm, is defed as [16]: Om V B V R DEm. iomax I The ratio of the dc bus voltage and the amplitude of the put le voltage, /V, is obtaed as (). Figure 7 illustrates the voltage ratio ( /V ), which is a function of the maximum duty ratio of the class-de rectifier diode, D dmax, accordg to (). The mimum conduction angle, m, which is a function of the duty ratio of the maximum class-de rectifier, is shown Fig. 8. The normalized effective put impedance [18] of the class-de resonant rectifier is Z i s C DE Z i R i jx Ci. The normalized put resistance, and the reactance, X are plotted R i _ fl, Ci _ fl, versus D dmax and shown Figs. 9 and 1, respectively. The numerical values of the class-de rectifier parameters at selected maximum duty ratio values, D dmax, are given Table I. (1) Ddmax V B 1 cos Ddmax P s D dmax 1. V 1 cos D dmax 16 fc s DEV () m s C DE R DEm TABLE I PARAMETERS OF CLASS-DE RECTIFIER FOR PFC scder i _ fl scde XCi _ fl /V

4 43 Journal of Power Electronics, Vol. 1, No. 3, May 1, V i B VB / T S D1, D4 Operate (a) (b) (c) (d) V I D, D3 Operate IV. DESIGN PROCEDURE I Omax The design of the proposed SSEB can be divided to two parts: the PFC semi-stage and the ballast semi-stage. The ballast semi-stage can be designed as detailed [16]. The design procedure for the PFC semi-stage, usg a symmetrical class-de low-dυ/dt rectifier, is given as follows: 1. To design the PFC symmetrical class-de rectifier, the no-load condition, at the duty ratio D d = D dm =, and the full-load condition, at the duty ratio D d = D dmax, were considered. In addition, a near-susoidal put le current was assumed, and an expected efficiency was estimated. The put power, P, and amplitude of the put le current, I, which is the maximum output current, I Omax, of the class-de resonant rectifier, was obtaed for a given output power, P out, and rms value of the put le voltage, V irms.. Choose a maximum duty ratio, D dmax, takg to consideration the tradeoffs regardg the ratio of the dc bus voltage and the amplitude of the put le voltage, L t L t L t L t Fig. 3. Conceptual waveforms of the symmetrical class-de resonant rectifier as a PFC: (a) le voltage waveform, ; (b) the rectified le voltage, ; (c) the combed voltage, VB ; (d) the put current waveform, i, is the filtered average diode current and follows the shape of the le voltage,. /V. If a low value of D dmax is used, then the ma switches have high voltage stresses. If a high value of D dmax is chosen, then the ma switches have low voltage stresses. 3. Fd the m value from the same le as the selected D dmax value Table I. 4. Determe the dc bus voltage,, from the specified put le voltage, V, and add it to the calculated I, thus obtag the class-de resonant rectifier s full load resistance, R DEm. 5. Fd f s with a desired C d, which is obtaed by s C DE R DEm from the same le as the selected D dmax value Table I. 6. Fd the normalized full load puts, R and X _, i_ fl from the same le as the selected D dmax value Table I. 7. To simplify the design procedure, we assume that the capacitance C d C i. Therefore, the total capacitance, C di, is approximately equal to capacitor C i. Under the full load condition, the amplitude of the drivg current, I d_fl, can be determed. 8. Fd the amplitude of 1 under the full load condition. 9. Calculate the amplitude of the drivg current, I d_nl, under no load. 1. Fd the amplitude of 1 with no load. 11. Fd the value of ductor from the results of procedures 8 and Add an additional ductance, L e, to to cancel the reactance of C d. A. The PFC Semi-Stage Design To mimic the design criteria of the proposed ballast, the electronic ballast was designed to handle a le rms voltage, V rms, of V and a le frequency, f L, of 5 Hz. It was assumed that the total ballast efficiency,, was equal to.9. The ballast drew a se-wave put current. The put power is given by: P Pout 4 W. (3) The amplitude of the ballast put current is calculated from: I IOmax = P V irms Ci =.57 A. (4) With D dmax equal to.4, the diode conduction angle is: m = Ddmax =.68 rad/s. (5) From Table I, the followg are obtaed: /V = 1.51; fl

5 Sgle-Stage High-Power-Factor Electronic Ballast with 433 i d The switchg frequency, f s, is given by: VB VB D1 D4 I d s t s t s t f s =.661 4CDERDEm 84 khz. (7) Under a full load, the normalized effective put impedance of the class-de resonant rectifier is: = R jx (8) Z i_ fl = s CDEZi _ fl i_ fl Ci_ fl, i D4 Dd s t where s R i_ fl = m =.19, (9) i CDE1 Dd s t and s cos XCi _ fl = m m m =.48. (1) i CDE i M 1 s t s t The put impedance value of the class-de rectifier is obtaed by solvg (7) (1). The resultg value is = 1.9 j4.8 Ω. The magnitude of i d = + i d, under a Z i _ fl full load, is determed by: I m s t I d _ fl = IOmax( VB V Ri_ fl ) =.868 A. (11) i M I m t s The bus voltage,, is equal to 37 V; therefore, I d_fl =.868 A. The magnitude of the equivalent voltage source,, is: 1 DS1 V 1 = d_ fl i_ fl I Z (1) s t DS V m 1 s t where the magnitude of the impedance of Z i_ fl = Z i _ fl 1 Ri _ fl sld. sci_ fl is given by: (13) Fig. 4. Idealized current and voltage waveforms of the proposed circuit. V (i.e., the amplitude of the le voltage) = V irms 311 V; and the dc bus voltage,, is approximately 37 V. From these values, the full-load resistance is calculated as: = R DEm ( VB V ) = 6.56 Ω. (6) I Omax High-frequency, stored-charge capacitors were selected to have the followg configuration: C DE = C DE1 = C DE = 1 nf. Under the no-load condition, the magnitude of the drivg current, i d, is determed by: I d _ nl V / = B j / C s DE = A. (14) Therefore, I d_nl = A, and the magnitude of the equivalent voltage source, 1, is determed by: j V 1 = Id_ nl jsld. s CDE (15) The values of V 1 and are obtaed by solvg (1), (13),

6 434 Journal of Power Electronics, Vol. 1, No. 3, May 1 CDE1 M 1 i M 1 C DE1 i CDE1 i O O C i CDE1 C d DE1 i D1 i CDE O D 4 CDE C DE i d M DS1 L r i M i r DS C r CC i L R L L 1 i d C d1 CDE1 i d D 1 i CDE O (a) 1 C d CDE C DE D 4 i D4 R i C i C di C d id i M 1 r DS1 r Ld i M r DS DS1 r Lr DS L r ir C rs R s 1 i d C d Cdi C i Ri (a) 1 Lr i r C r CC i L R L L Z i R i C di id rld i S S (b) rlr r S L r ir Crs R s Z i (b) (c) Fig. 6. Equivalent circuits of the electronic ballast: (a) PFC symmetrical class-de rectifier with an equivalent se-wave voltage source, 1 ; (b) simplified equivalent circuit of (a); (c) equivalent circuit of the verter semi-stage. (c) Fig. 5. Circuit of the symmetrical class-de rectifier semi-stage and the class-d parallel resonant verter: (a) circuit with a symmetrical class-de rectifier and a parallel-resonant circuit; (b) the symmetrical class-de rectifier is replaced by the equivalent circuit, C i R i, and the R L C r circuit is transformed to an R s C rs circuit; (c) equivalent circuit of the verter. and (15). The resultg value of equals μh. For a fite value of the capacitance (C d ), an additional L e can be added to to compensate for the reactance of C d = C d1 = C d = 1 nf. The value of the additional ductance is: B. Ballast Semi-Stage Design A class-d parallel resonant verter is shown Fig. 6(c), the design of which can be found []. The class-d parallel resonant verter is easy to design. C. Conduction Loss Analysis The calculated conduction loss of the electronic ballast, as a function of the load resistance, R L, is depicted Fig. 5. Therefore, the maximum value of the dra current (i.e., I M = I S = I d + I r ) is shown Fig. 5(c). Thus the power loss each MOSFET s forward resistance, r DS, is given by: 1 L e = C s d = μh. (16) P rds = IM rds 4 = 67 mw. (19) The total ductance (total) is: (total) = + L e = μh. (17) The converter employs (STMicroelectronics IRF74) MOSFETs, each with an on-resistance, r DS, of.48 Ω. The power loss the diodes, D 1 D 4, due to the forward voltage, V D, is obtaed as: To achieve a ripple voltage of less than 1%, the value of the bulk filter capacitor is determed by: V P DB = DID = 156 mw. () CB P VBVripple L = μf. (18) Therefore, the standard value of 68 μf is selected for C B. The bridge rectifier was built usg a (Philips BYM36C) fast-recovery diode with a pn junction diode (V D = 1. V). The ESR of the filter ductor is r Lf = Ω. Thus, the conduction loss the filter ductor, L f, can be obtaed as:

7 Sgle-Stage High-Power-Factor Electronic Ballast with 435 TABLE II CIRCUIT PARAMETERS OF THE PROTOTYPE Fig. 7. /V as a function of D dmax. Parameter M 1 and M D 1 D 4 L f L r C d1 and C d C DE1 and C DE C r C C C B Value and Part Number N-Channel MOSFETs IRF74 Fast Recovery Diodes BYM36C 1 mh (DRWW1x16 N-series-YTE) 43 μh (EE3/15/7 N7-EPCOS) 775 μh (EE5/13/7 N7-EPCOS) 1 nf (polypropylene) 1 nf (polypropylene) 4.7 nf (polypropylene) 1 μf (polypropylene) 68 μf (electrolytic) P rlf = IrLf = mw. (1) The parasitic resistance of the series ductor, r Ld, is.119 Ω. Thus the conduction loss the ductor,, is obtaed from: Fig. 8. Conduction angle m versus D dmax. P rld d Ld I r = = 159 mw. () The parasitic resistance of the ductor, r Lr, is.371 Ω, and the maximum value of the resonant current, I r, is given by (3). Therefore, the conduction loss the ductor, L r, is given by: I r = V B Q L Z O 1 = 615 ma. (3) Fig. 9. s C DE R i _ fl as a function of D dmax. = P rlr IrrLr = 7 mw. (4) Conduction losses due to the parasitic resistance the overall capacitors are very small. Therefore, their affects were neglected. Fig. 1. s C DE X Ci _ fl as a function of D dmax. V. SIMULATION AND EXPERIMENTAL RESULTS A. Simulation Results Figure 11 shows the simulated put le-current waveforms of the asymmetrical and symmetrical class-de resonant rectifiers without a filter ductor, L f. These waveforms show that the put le current the symmetrical class-de resonant rectifier has half the peak value and double the frequency when compared to the asymmetrical rectifier. The higher value for the peak le put current is the ma drawback of the asymmetrical topology.

8 436 Journal of Power Electronics, Vol. 1, No. 3, May 1 Ch i Fig. 1. Input le voltage and the current waveforms. Fig. 11. Comparison of the simulated waveforms of the put le-current of the asymmetrical and symmetrical circuits, with the bottom two waveforms as zoomed- views of the top two waveforms. B. Experimental Results A prototype ballast was constructed usg the component values obtaed from the design procedure given above. The details of these calculations are given design procedures A and B. The circuit parameters are presented Table II. The switchg frequency was fixed at about 84 khz. The le voltage was set to V rms, and the le frequency, f L, was 5 Hz. The measured put le power was approximately 39.9 W, while the put power-factor was approximately.99 (as shown Fig. 1). The THD of the put current, THDi, was about 1%, as shown Fig. 13. The proposed electronic ballast can be operated with a le voltage of V rms %. The measured THDi and PF are shown Fig. 14. Otherwise, the electronic ballast will suffer from a wide range of lamp power variations. Near the zero crossg, the le current can not reach zero if the le voltage is too high. On the other side, the le current shows a dead band near the zero crossg when the le voltage is too low. In such cases, a near-susoidal le put current can be obtaed by usg switchg frequency modulation over a wide range of le put voltages. Figure 15 illustrates the experimental waveforms of the diode current,, and the capacitor voltage, CDE1, of the symmetrical class-de low-dυ/dt rectifier near the peak and zero-crossg of the le voltage, respectively. As expected, the duty ratio of the diode current decreased as the stantaneous le voltage decreased. The switch voltage and the switch current waveforms of D 1 of the class-de resonant rectifier are shown Fig. 16. The waveforms of the switch voltage and the switch current of M are shown Fig. 17. Fig. 13. Measured THD of i from the power analyzer. THDof the put current i (%) PF THDi Le voltage (V ) Fig. 14. THDi and PF versus le voltage. Ch Ch (vertical : V / div, Ch : A / div) (horizontal(top) : ms/ div,(bottom) : 5S/ div) rms CDE1 D1 CDE1 D1 Fig. 15. Measured waveforms of and CDE1 ; the top two waveforms are near the zero-crossg of the le voltage, while the bottom two waveforms are near the le-voltage peak. Power factor

9 Sgle-Stage High-Power-Factor Electronic Ballast with 437 Ch D1 i D1 D L f D 3 D 4 i d C d1 C d CDE C DE i CDE C s C t R s i d R t V cc V b R t H o IR153 C t D 5 Com V s L o C b R G1 R G M 1 M i M 1 DS1 Lr i M i r DS Fig.. Simplified electronic ballast usg a sgle, high-frequency capacitor. C r CC i L R L C B L (vertical : V / div, Ch : A / div) (horizontal : S/ div) Fig. 16. Measured diode voltage and current waveforms of D 1 at 4 degrees of the le voltage. Ch DS i M The proposed scheme provides a more systematic and feasible solution. Because the previous ballasts had an teraction between the current the PFC semi-stage and the current the verter semi-stage, they had a high lamp-current crest factor when tryg to achieve a low THD the le-put current. Fig. 18 illustrates the measured waveform of the lamp current. The crest factor of the lamp current was 1.4, which meets the general lamp manufacturer recommendation of a value below 1.7. Fig. 19 shows the measured waveforms of the lamp voltage and the lamp current. The lamp power, P L, was W. The measured efficiency of the ballast was approximately 9%. (vertical : V / div, Ch : A / div) (horizontal : S/ div) Fig. 17. Measured switch voltage and current waveforms of M. A B VI. SIMPLIFIED CIRCUIT The circuit for the proposed electronic ballast can be simplified by combg the two high-frequency capacitors, C DE1 and C DE, to one, as shown Fig.. The number of capacitor components is reduced. An (IR153) IC, which is a high-side low-side driver, was used to drive a pair of MOSFETs, which were connected to form the half-bridge verter. A (vertical : 5mA / div) (horizontal(top) : ms/ div,(bottom) : 5S/ div) Fig. 18. Experimental envelope waveform of the lamp current; the lower waveform is a zoomed- view of the top waveform. Math Ch L P L i L (vertical :1V / div, Ch :.5A / div, Math : 4W / div) (horizontal:5s/div) Fig. 19. Measured voltage, power, and lamp-current waveforms. B VII. CONCLUSION A novel, sgle-stage, high-power-factor, electronic ballast with a symmetrical class-de low-dυ/dt rectifier as a PFC is proposed this paper. The proposed PFC was achieved by usg a bridge rectifier that serves as a symmetrical class-de resonant rectifier. The two active power switches were operated under the ZVS condition. By usg this topology, the conduction angle of the bridge rectifier diode current was creased, resultg a low-le current harmonic, a power factor near unity, and reductions the size and weight of the EMI filter. The prototype ballast was implemented to drive a T8-36W fluorescent lamp. The switchg frequency was fixed to approximately 84 khz. Experimental results verified the theoretical analysis. The designed electronic ballast had a power factor of.99, a 1% THD i (which satisfies the lightg equipment IEC class-c standard), a 1.4 lamp-current crest factor (which meets the lamp manufacturer recommendations), and an efficiency of 9%.

10 438 Journal of Power Electronics, Vol. 1, No. 3, May 1 ACKNOWLEDGMENT This research was fancially supported by the Faculty of Engeerg, Kg Mongkut s University of Technology North Bangkok. REFERENCES [1] C. S. Moo, H. C. Yen, Y. C. Hsieh, and C. R. Lee, A fluorescent lamp model for high-frequency electronic ballasts, Conf. Rec. IEEE IAS Annu. Meetg, Vol. 5, pp ,. [] M. K. Kazimierczuk and W. Szaraniec, Electronic ballast for fluorescent lamps, IEEE Trans. Power Electron., Vol. 8, No. 4, pp , Oct [3] E. Santi, Z. Zhang, and S. Cuk, High frequency electronic ballast provides le frequency lamp current, IEEE Trans. Power Electron., Vol. 16, No. 5, pp , Sep. 1. [4] M. Dehghani, S. M. Saghaiannejad, and H. R. Karshenas, Electronic ballast for HPS lamps with trsic power Regulation over Lamp Life, Journal of Power Electronics, Vol. 9, No. 4, pp , Jul. 9. [5] Y. Wang, X. Zhang, W. Wang, and D. Xu, Digital control methods of two-stage electronic ballast for metal halide lamps with a ZVS-QSW converter, Journal of Power Electronics, Vol. 1, No. 5, pp , Sep. 1. [6] J. Qian and F. C. Lee, Charge pump power-factor-correction technologies Part II: Ballast applications, IEEE Trans. Power Electron., Vol. 15, No. 1, pp , Jan.. [7] H. S. Chon, D. Y. Lee, and D. S. Hyun, A new control scheme of class-e electronic ballast with low crest factor, Journal of Power Electronics, Vol. 3, No. 3, pp , Jul. 3. [8] K. Jirasereeamornkul, M. K. Kazimierczuk, I. Boonyaroonate, and K. Chamnongthai, Sgle-stage electronic ballast with class-e rectifier as power-factor corrector, IEEE Trans. Circuits Syst. I, Vol. 53, No. 1, pp , Jan. 6. [9] H. M. Suryawanshi, V. B. Borghate, M. R. Ramteke, and K. L. Thakre, Electronic ballast usg a symmetrical half-bridge verter operatg at unity-power-factor and high efficiency Journal of Power Electronics, Vol. 6, No. 4, pp , Oct. 6. [1] W. Huang, D. Chen, E. M. Baker, J. Zhou, H.-I Hsieh, and F. C. Lee, Design of a power piezoelectric transformer for a PFC electronic ballast, IEEE Trans. Ind. Electron., Vol. 54, No. 6, pp , Dec. 7. [11] C.-M. Wang, A novel sgle-stage high-power-factor electronic ballast with symmetrical half-bridge topology, IEEE Trans. Ind. Electron., Vol. 55, No., pp , Feb. 8. [1] C. B. Nascimento and A. J. Per, High power factor electronic ballast for fluorescent lamps with reduced put filter and low cost of implementation, IEEE Trans. Ind. Electron., Vol. 55, No., pp , Feb. 8. [13] J. M. Alonso, M. A. Dalla Costa, M. Rico-Secades, J. Cardesín, and J. García, Investigation of a new control strategy for electronic ballasts based on variable ductor, IEEE Trans. Ind. Electron., Vol. 55, No. 1, pp. 3-1, Jan. 8. [14] Y.-C. Chuang, C.-S. Moo, H.-W. Chen, and T.-F. L, A novel sgle-stage high-power-factor electronic ballast with boost topology for multiple fluorescent lamps, IEEE Trans. Ind. Appl., Vol. 45, No. 1, pp , Jan./Feb. 9. [15] C. S. Moo, K. H. Lee, H. L. Cheng, and W.M. Chen, A sgle-stage high-power-factor electronic ballast with ZVS buck-boost conversion, IEEE Trans. Ind. Electron., Vol. 56, No. 4, pp , Apr. 9. [16] C. Ekkaravarodome, A. Nathakaranakule, and I. Boonyaroonate, Sgle-stage electronic ballast usg class-de low-dυ/dt current-source driven rectifier for power-factor correction, IEEE Trans. Ind. Electron., Vol. 57, No. 1, pp , Oct. 1. [17] J. C. W. Lam and P. K. Ja, A high-power-factor sgle-stage sgle-switch electronic ballast for compact fluorescent lamps, IEEE Trans. Power Electron., Vol. 5, No. 8, pp. 45-1, Aug. 1. [18] D. C. Hamill, Class-DE verters and rectifiers for dc-dc conversion, Proc. 7th Annu. IEEE Power Electron. Spec. Conf. Rec., Vol. 1, pp , Chaar Ekkaravarodome was born Songkhla, Thailand, He received his B.Ind.Tech Industrial Electrical Technology from the Kg Mongkut s Institute of Technology North Bangkok (KMITNB), Bangkok, Thailand, 3, and his M.E. and Ph.D. Electrical Engeerg and Energy Technology from the Kg Mongkut s University of Technology Thonburi (KMUTT), Bangkok, Thailand, 5 and 9, respectively. He is currently a Lecturer with the Department of Instrumentation and Electronic Engeerg, Faculty of Engeerg, Kg Mongkut s University of Technology North Bangkok (KMUTNB). His current research terests clude electronic ballasts, power-factor-correction circuits, resonant rectifiers, and soft-switchg power converters. Kamon Jirasereeamornkul was born Phuket, Thailand, He received his B.E. and M.E. Electrical Engeerg, and his Ph.D. Electrical and Computer Engeerg from the Kg Mongkut s University of Technology Thonburi (KMUTT), Bangkok, Thailand, 1997, 1, and 6, respectively. He is currently a Lecturer with the Department of Electronics and Telecommunication Engeerg, Faculty of Engeerg, KMUTT. His current research terests clude electronic ballasts, high-frequency power converters, and power-factor-correction circuits.