Module 3. DC to DC Converters. Version 2 EE IIT, Kharagpur 1

Transcription

1 Module 3 DC to DC Converters ersion EE IIT, Kharagpur

2 Lesson 4 C uk and Sepic Converter ersion EE IIT, Kharagpur

3 Instructional objective On completion the student will be able to Compare the advantages and disadvantages of CuK and Sepic converters with those of three basic converters. Draw the circuit diagrams and identify the operatg modes of CuK and Sepic converters. Draw the waveforms of the circuit variables associated with CuK and Sepic converters. Calculate the capacitor voltage ripples and ductor current ripples CuK converter. ersion EE IIT, Kharagpur 3

4 4. Introduction Switch Mode Power Supply topologies follow a set of rules. A very large number of converters have been proposed, which however can be seen to be mor variations of a group of basic DC- DC converters built on a set of rules. Many consider the basic group to consist of the three: BUCK, BOOST and BUCK-BOOST converters. The CUK, essentially a BOOST-BUCK converter, may not be considered as basic converter along with its variations: the SEPIC and the zeta converters. The Canonical Cell forms the basis of analyzg switchg circuits, but the energy transport mechanism forms the foundation of the buildg blocks of such converters. The Buck converter may consequently be seen as a oltage to Current converter, the Boost as a Current to oltage converter, the Buck-Boost as a oltage-current-oltage and the CUK as a Current- oltage-current converter. All other switchg converter MUST fall to one of these configurations if it does not crease the switchg stages further for example to a -I--I converter which is difficult to realize through a sgle controlled switch. It does not require an explanation that a current source must be made to deliver its energy to a voltage sk and viceversa. A voltage source cannot discharge to a voltage sk and neither can a current source discharge to a current sk. The first would cause current stresses while the latter results voltage surges. This rule is analogous to the energy exchange between a source of Potential Energy (oltage of a Capacitor) and a sk of Ketic Energy (Current an Inductor) and viceversa. Both can however discharge to a dissipative load, without causg any voltage or current amplification. The resonant converters also have to agree to some of these basic rules. 4. Analysis of C uk converter The advantages and disadvantages of three basic non-isolated converters can be summerised as given below. (i) Buck converter S L C i B Fig. 4.: Circuit schematic of a buck converter Features of a buck converter are Pulsed put current, requires put filter. Contuous output current results lower output voltage ripple. Output voltage is always less than put voltage. ersion EE IIT, Kharagpur 4

5 (ii) Boost converter L S C Fig. 4.: Circuit schematic of a boost converter Features of a boost converter are Contuous put current, elimates put filter. Pulsed output current creases output voltage ripple. Output voltage is always greater than put voltage. (iii) Buck - Boost converter S L C Fig. 4.3: Circuit schematic of a buck boost converter Features of a buck - boost converter are Pulsed put current, requires put filter. Pulsed output current creases output voltage ripple Output voltage can be either greater or smaller than put voltage. It will be desirable to combe the advantages of these basic converters to one converter. CuK converter is one such converter. It has the followg advantages. Contuous put current. Contuous output current. Output voltage can be either greater or less than put voltage. CuK converter is actually the cascade combation of a boost and a buck converter. L L S C - S ' ' Fig. 4.4: Circuit schematic of a boost-buck converter ersion EE IIT, Kharagpur 5 C -

6 S and S operate synchronously with same duty ratio. Therefore there are only two switchg states. (i) 0 < t DT S to () & S to (') The circuit configuration is given below L L L C C C C (a) (ii) DT < t < T; S to () & S to (') L L L C C (b) Fig. 4.5: Circuit topology of a boost-buck converter durg different switchg tervals (a) 0 t < DT, (b) DT t < T These two topologies can also be obtaed from the followg circuit which is the so called CuK converter. ersion EE IIT, Kharagpur 6

7 L C L S C L (a) v c C - L il il i B C i c i 0-0 (b) Fig. 4.6: Schematic and Circuit representation of ĈuK converter. (a) Schematic diagram, (b) Circuit diagram 4.. Expression for average output voltage and ductor currents L i c i c i 0 il il - 0 C - L i c C (a) Fig. 4.7: Equivalent Circuit of a ĈuK converter durg different conduction modes. (a) 0 < t DT (b) DT < t T L L il il i c i 0 C 0 - C - C L 0 < t DT (b) DT < t T - - ersion EE IIT, Kharagpur 7

8 Applyg olt-sec balance across L ( )( ) DT D T =0 (4.) C D = 0 ( ) C or C = (4.) D Applyg olt-sec balance across L ( ) ( ) DT D T = 0 (4.3) 0 C 0 or 0 D C = 0 (4.4) or 0 C D = D = (4.5) D Expression for average ductor current can be obtaed from charge balance of C I L I0 0 = (4.6) I D D = 0 L I = = (4.7) 0 From power balance v 0 L = D 0I0 = = I I = D ( D) L ( D) (4.8) (4.9) 4.. Current ripple and voltage ripple calculations The waveforms of different circuit variables of Fig. 4.7 are given Fig ersion EE IIT, Kharagpur 8

9 i B DT T t I L MAX I L i L I L MIN t I L MAX I L i L I L MIN t t t i c I L MAX I L MIN v c - I L MAX - I L MIN C MAX C C MIN t t i c / I ˆL p-p t t t c -/ I ˆL p-p t c Fig. 4.8: Waveforms of circuit variables a ĈuK converter. ersion EE IIT, Kharagpur 9

10 From the waveforms of Fig. 4.8 I D T LMAX = ILMIN (4.0) L ˆ DT IL = ILMAX ILMIN = (4.) p p L From equation 4.9 I I = I = D ( D) LMAX LMIN L (4.) ILMAX I D T D = ( D) L (4.3) D T D = ( D) L (4.4) LMIN I = I ( D) T = I DT 0 LMAX LMIN LMIN L L (4.5) ˆ DT IL = IL MAX IL MIN = (4.6) p p L From equation 4.7 ILMAX ILMIN= I D 0 = (4.7) D ILMAX T D = D L (4.8) I LMIN T D = D L (4.9) For calculatg voltage ripples it is noted that v c DT = i c 0 c dt (4.0) but for 0 < t DT i c = i L (4.) DT DT i 0 c dt i dt c = c 0 L (4.) ersion EE IIT, Kharagpur 0

11 or vˆ c DT I I T DTI = C L = c LMAX LMIN L 0 I DT = (4.3) c or vˆ c = DT C( D) (4.4) vˆ c = t i t c c dt which is the hatched area under ic waveform Fig. 4.8 vˆ c = T DT DT c L = 8L C (4.5) Equations 4., 4.6, 4.4 and 4.5 can be utilized to design a CuK converter of given specification ersion EE IIT, Kharagpur

12 The SEPIC Converter The previous chapter discussed the sgle stage conversion Buck and Boost converters along with the two-stage Buck-Boost converter. This chapter offers a few additional topologies. Fig. 4.9(a): A basic converter: BUCK converter Fig. 4.9(a) is that of a basic Buck converter. From the voltage source C, the converter charges the current sk constituted by the ductor-diode (L-D). The current is further converted to voltage without a switchg stage (amplification) at C. The canonical switchg cell is approached if the capacitors C and C are combed to be represented by a sgle capacitor C. The cell cludes T-C-L-D, the basic buildg block of DC-DC converters. The Boost converter is realized if the positions of D and T are terchanged Fig.4.9 (a). Now power flows from the right. Here, the energy stored the ductor durg each ON period of switch T is transferred to the Capacitor durg its OFF period. The CUK converter as the dual of the Buck-Boost converter has current put and current output stages. The basic SEPIC is a modification of the basic Boost and the CuK topologies. Consider the Boost converter Fig 4.9(b). At steady state, the average voltage across the put ductor is zero. Equatg the ductor voltages for the period when the switch T is ON with that when it is OFF,.T ON = ( out ).TOFF (4.6) or, out = ( ). where, is the duty ratio of the switch. Fig. 4.9(b): BOOST converter Fig. 4.0 Modified Boost with load across Diode for Boost-Buck Operation. (left) without output filter, (right) with filter. In the path, -L-D- out, Fig. 4.9(b), the average voltages across all the elements are known. Thus, that appearg across the diode D is out. This voltage from Eqn is: ersion EE IIT, Kharagpur

13 D = [( ) ]. = ( ) A Boost-Buck converter is thus realized. This is the voltage that would appear an unfiltered form at the load Fig. 4.0 (left). Now, sce the source is a current source, the output stage must be capacitive (voltage sk) which is taken care of by C -D. The voltage across D has high ripples, which can be filtered much like the Buck converter with an L (and a C 3 ). The CUK converter is thus realized. It is a I--I converter. A glarg drawback of this derived converter topology is that the polarity of the output is reversed. This is not acceptable for various reasons. Now it is the turn of the Diode to be terchanged with the filter ductor. The ductor is thus converted to be part of the switchg circuit and it not just a filter. The SEPIC results not an entirely different one - but easily derivable from the previous topologies. The SEPIC officially stands for Sgle-Ended Primary Inductance Converter. However, the unofficial terpretation is more descriptive: Secondary Polarity Inverted Cuk. Fig. 4.(a): The basic SEPIC topology Aga, the basic put output relation can be derived by considerg the two ductors to have average null voltage across themselves. If the lk capacitor has a voltage c across itself (consider it to be reasonably constant), then for the put ductor, the volt-secs durg the ON and OFF periods of the switch are:.t ON = (C out )T OFF (4.7) or, C = out (. ) TOFF For the output ductor,.t =.T (4.8) C ON out OFF Elimatg, c and writg T ON =. T, out = ( ) (4.9) Thus the SEPIC is also basically a BOOST-BUCK converter ak to the CUK converter. (The Boost stage comes first followed by the Buck stage and it is also I--I converter) In the practical SEPIC converter, the two ductors are coupled with the polarities as dicated by dots Fig. 4.(a). The turns ratio is and the couplg is very tight. For such a coupled-transformer SEPIC, equatg the positive and negative volt-secs for the two ductors, (. K. C ). TON = ( out C K. out ). T OFF (4.30) for the put ductor, and ersion EE IIT, Kharagpur 3

14 K T K T (4.3) ' ' ( C. ). ON = [ out ( out C )]. OFF Equations (4.8) and (4.9) can be obtaed from the above two by substitutg both K and K to zero to have no couplg between the two coils. Fig. 4.(b) The practical SEPIC topology with coupled ductors The above two equations result an identity to dicate that such a system cannot work. This can be explaed by examg the operation of the circuit. Initially when the transistor is OFF, the capacitor C charges to the supply voltage. When the transistor is switched ON, the resultg active circuit is shown Fig 4.. Fig. 4.: Active part of the circuit when transistor is switched with C charged to The circuits to the left and right of the transistor are identical and both the wdgs are duced with the supply voltages, resultg null emfs on either side, which explas why the ideal circuit will not work. However, neither the couplg between the ductors nor the effective turns ratio can be unity. This results a circuit with the features of the uncoupled circuit and the circuit performs. The second voltage source, C, duces N. C to the primary, where N is the turns ratio. For the terestg case, = C =, if the turns ratio, n, is creased slightly from unity, by /k (where k < is the couplg coefficient between wdgs), then the voltage duced by will crease the voltage at the Dra of the transistor to N., thereby "bootstrappg" the leakage ductance of the put ductor. Because the voltage at each end of this leakage ductance is the same, its ductance is effectively fite. Consequently, all variations magnetizg current, (through M) due to a varyg is supplied from the secondary wdg source. By symmetry, settg n = k causes the secondary-wdg current to become constant while the primary source supplies the magnetizg-current variations. This effect can be desirable because, for n = /k, it results constant (DC) primary current. Noisy switchg current does not appear at the converter put but is diverted stead to the secondary wdg. However, typical values of k are slightly less than one, and turns ratios of nearly : may not be easy to wd. One simplification is to use a : transformer, such as a lowcost, commodity, common-mode power-le put-filter choke, and add a small additional ductance series with the primary wdg. This effectively creases the leakage ductance so that the same secondary-wdg domance of magnetizg current is obtaed with n =. ersion EE IIT, Kharagpur 4

15 The circuit is an alternative to the Boost converter and outputs an range which cludes the put range also beg a Boost-Buck converter. It is superior to the other converters both terms of the put current purity and efficiency. Fig. 4.3: Dra voltages of FLYBACK and SEPIC converters The waveforms Fig. 4.3 show the voltage at the transistor Dra present on the fly back (Boost) and SEPIC circuits. The fly back transformer leakage ductance produces a voltage spike that adds an additional level to the "flat-top" voltage. This level is about.5 times the supply voltage for puts around 0. In comparison, the SEPIC FET switchg waveform is clamped, and shows very little overshoot, or rgg. This clampg results less switchgloss, output voltage noise and a power stage that can be operated at a much higher frequency than that of the fly back. Aga, the fly back transformer leakage ductance also produces a significant voltage spike relative to the SEPIC at the output diode. A relatively high voltage (~00) output diode is required for the fly back to handle the large negative rgg compared to the SEPIC s 60 Schottky diode. The 0.5 volt forward drop of the SEPIC s Schottky diode relative to the one volt forward drop of the flyback's ultra-fast diode, results significant power savgs for the SEPIC. ersion EE IIT, Kharagpur 5