Modified Bridgeless Rectifier for PFC with Minimized Stress

Transcription

1 Modified Bridgeless Rectifier for PFC with Mimized Stress *1 aya Sagar Kommukuri, 2 Kanungo Barada Mohanty, 3 Kishor Thakre, 4 Aditi Chatterjee, 5 Ashwi Kumar Nayak Department of Electrical Engeerg National Institute of Technology Rourkela, Rourkela, Odisha 7698, India Abstract. A high performance sgle phase modified bridgeless ac-dc converter with an automatic power factor correction is troduced. The proposed converter is based on a sgle ended primary ductance converter (SEPIC) topology and operated contuous conduction mode (CCM) to meet the demands of power factor correction (PFC) to unity and output voltage regulation. It offers many advantages, such as fewer semiconductor devices, low stress on each component, improved efficiency, high power factor compared to classical converter.detailed analysis of the converter is presented. Simulation and experimental results are discussed for a 3W prototype to verify the performance of the converter. Keywords: Power factor correction (PFC); contuous conduction mode (CCM); sgle ended primary ductance converter (SEPIC). 1. Introduction Many applications like computers, telecom equipment, biomedical dustries and LED lightg uses AC-DC conversion which volves conventional bridge rectifier with large capacitor at output end is unavoidable, results low power factor of about.5-.7[1]. As per the Strgent ternational standards like International Electronic Commission (IEC) , harmonics produced by the electronic equipment like rectifiers should be limited [2].Therefore, the power factor improvement is mandatory for sgle phase power supplies to meet the demands like reduction of current harmonics and power factor correction (PFC).The most conventional PFC converter is a bridge rectifier followed by a DC-DC converter. Boost converter is widely used as the DC-DC converter PFC circuits because of its simplicity, low cost and high performance though it is havg output voltage greater than the peak put voltage. In large no of applications, it is preferred to have the PFC output voltage lower than the put ac voltage, a buck type converter is recommended. The put current of buck converter is discontuous and to shape it like susoidal another passive filter must be used at the put side of the buck converter. This is the characteristics of all converters which a buck converter is at its put, such as buck-boost, nonvertg buck-boost, flyback etc.,[ 3-5]. On the other side, a SEPIC converter can provide a high power actor regardless of its output voltage due to its step up/down function. However, all the above addressed conventional PFC rectifiers cludes a front end bridge rectifier which leads to high conduction losses, resultg additional thermal management and decrease the efficiency of the PFC converter. In order to enhance the efficiency of the conventional PFC 72

2 converters bridgeless PFC converters have been proposed such as buck, buck-boost, boost, sepic [6-17].Sce Bridgeless PFC rectifiers has lower no of semiconductor devices the current path,results lower conduction losses,higher efficiency and cost savg. The bridgeless PFC boost rectifier is predomant because of its simplicity but it has same major practical drawbacks like difficulty providg put-output isolation, high startup rush current and lack of current limitg durg overload conditions as conventional boost PFC converter. Therefore research has been focused on bridgeless sepic PFC sce it is a solution for many applications. Recently many bridgeless SEPIC PFC converters have been proposed the literature. Bridgeless SEPIC PFC circuits that are proposed the literature [18-23], operates under DCM mode suffers with high voltage and current stress that highly degrades the performance of the converter and limits its application range. To overcome aforementioned defects, a modified bridgeless SEPIC PFC with contuous conduction mode (CCM) with reduced stress is presented. This meets the challenges of near unity power factor and output voltage regulation. The remag sections of the paper is organized as follows. Prciple of operation is discussed section 2. In section 3 theoretical analysis are design procedure and experimental considerations are given. Efficiency improvement is explaed section 4. The simulation results are presented section 5. Experimental results and conclusion are given section 6 and 7, respectively. 2. Operation of Bridgeless SEPIC converter CCM mode The circuit diagram of conventional SEPIC PFC rectifier and modified Bridgeless SEPIC are shown Fig.1 and Fig.2. Bridgeless SEPIC is combation of both bridge rectifier and classical SEPIC converter, so it is known as Bridgeless SEPIC converter. It is havg fewer semiconductor components. Operation of the circuit is similar to classical sepic converter and is symmetrical two half le cycles of put voltage. Thus, the operation of the converter is considered durg one switchg period the positive half le cycle of the put voltage. The converter is operated CCM mode i.e., output diode turns off when the switch is turned on. The capacitance of the output capacitor Co is adequately high enough to make it ideal dc voltage source as shown Fig.2.Also, the supply voltage is assumed constant and equal to a switchg period T s. To simplify the analysis, it is assumed that the converter is operatg at steady state and all components are ideal. The circuit operation a switchg cycle is divided to two modes.fig.3 and Fig.4 shows the schematic diagram of mode I and mode II the positive half cycle. The theoretical waveforms of the converter are shown Fig.5. L1 Cc D S1 L2 C Fig 1. Conventional SEPIC PFC rectifier 73

3 D1 S1 C c D L 1 D3 L 2 C D2 S2 C m Fig 2. Modified Bridgeless SEPIC PFC rectifier Mode I (t -t 1 ): At t, both switches S1, S2 and diode D1 are ON state and output diode D is OFF state. Capacitors C C and C m follows the put voltage. The load current is provided by the output capacitor as the output diode is reverse biased. Here the switch current is combation of currents flowg through ductors L 1 and L 2.Input ductor current i L1 starts to crease learly by a slope of (t )/ L 1 and output ductor current i L2 starts decreasg learly by the slope of ( Cc Cm )t / L 2.This mode ends by turng off the switches S1 and S2.Switch current is given by the equation (1). I S1 t i L1 i L2 ( t ) ( t ) t L L 1 2 (1) where i ( t t L ) 1 L (2) 1 i Cc Cm ( t ) L = (3) ( t t ) 2 L 2 L2 t (4) Cc Cm D1 S1 C c D L 1 D3 L 2 C D2 S2 C m Fig 3. Mode I 74

4 Mode II (t 1 -t 2 ): At t 1, switches S1 and S2 are turned off and diodes D3 and D starts conductg. The voltage across switches begs to crease. Energy stored the put ductor is transferred to the output through the couplg capacitor C c1 and output diode D and also to the C c2 through diode D 3 at the same time.energy stored ductor L2 is transferred to the output through diode D.This mode ends by startg the next switchg cycle at t2. i Cc Cm t t (5) L1 il 1 1 t1 L1 i Cc t t (6) L2 il2 1 t1 L2 Cc Cm (7) D1 S1 C c D L 1 D3 L 2 C D2 S2 C m Fig 4. Mode II 75

5 Pulses S 1,S 2 I S1 S1 (+ )/2 I D, I D3 IS 1 /2 D (+ )/2 I L1 DI L I L2 t t 1 t 2 Fig 5. Theoretical waveforms of the Converter 3. Theoretical Analysis 3.1 Static ga: The average ductor voltage at steady state is considered to be zero. By applyg volt-second balance to the ductor L is given by equation (8) 1 76

6 t on T t (8) cm on From equation (4) & (7) we get cm (9) 2 From equation (8) & (9) we get t D T Now, static ga is given by equation (11) on (1) 1 D 1 D (11) 3.2 Inductors L 1 and L 2 : Inductors L 1 and L 2 are calculated as a specification of maximum put current ripple D i L.The peak put current is calculated by equation (12) assumg the current ripple given by equation (13).The ductors L 1 and L 2 are given by equation (14) I 2P s( ) (12) ( peak) t ( rms) D D il (13) Lfs D L 1 L 2 (15) Di f L s 3.3 Capacitors C C and C m It has a considerable impact the put current waveform sce the capacitors C and c C m follows the put le voltage with le period and is constant one switchg period. Resonant frequency f r plays a vital role the design of capacitor C and c C. The resonant frequency f r of couplg capacitor C andc, ductor (L 1 ) and ductor (L 2 ) should be greater than le frequency c m f to avoid the put current oscillations at each half le cycle, likewise resonant frequency l should be lower than the switchg frequency f s to make sure that the capacitor voltage is constant a switchg time T s.accordgly C and c C can be obtaed from the followg equation. m m f r 77

7 C m C C 4f 2 r 1 L L 1 2 (16) Where f l f r f s f value is chosen as 5 khz to meet the requirement. r 3 Output voltage of the converter ( ) 25 o Cc Cm 2 Switch voltage of the converter 15 Cm 1 Cc ωt Fig 6. Theoretical waveforms of the Capacitor voltages The voltage across the capacitors Fig.6. C and c C are given by the equation (17) and (18) and are shown m Cc Cm 1 1 D D 1 D (17) (18) 3.4 Output Capacitor C Sce output voltage ripple is two times the put le frequency, output capacitor must be large enough to reduce the output voltage ripple D.Therefore, output capacitor voltage is obtaed from the followg equation C P (19) 4 fld 78

8 where f is put le frequency and D is output voltage ripple. l 3.5 Maximum voltage and current ratg of switchg devices The maximum switch voltage and current of the converter is obtaed from the followg equation. (m) S1,2(m) (2) 2 S1,2(max) (max) (21) 2 I m I(m) DI L (22) S1 I I max I(max) DI L (23) S1 I 3.6 Controller Design The average current mode control is used to generate the current reference for the bridgeless SEPIC converter. The design of the converter is done based on CCM mode. The converter uses UC3854 as a controller, which gives current shape and frequency that follows le current usg synchronous feedback loop [ 25]. To get near unity power factor, the controller needs voltage and current feedback signals are sensed from the converter. In the given circuit put voltage is sensed from capacitors C and c sce they follows the put voltage, Input ductor current signal is sensed from diode currents (I D1 and I D2 ) as shown Fig.7. Then the reference current is computed by a multiplier of the synchronous feedback loop, output voltage feedback loop, and put voltage feed forward loop. The control circuit of the converter is shown Fig.7. The voltage feedback loop should have a very low bandwidth, well below the le frequency, order to mimize put current distortion [26,27]. C m I D1 I D2 Adder Current error Amplifier + _ S 1,S 2 f s =1 Khz Cc + Cm 1/k Ref oltage error Amplifier Multiplier Fig 7. Block diagram for Controller 79

9 4. Efficiency improvement Based on the number of components present the converter, the efficiency enhancement of the converter is analyzed. From the operation of the converter, it is seen that a diode the rectifier is removed and the other diode is substituted by a switch. Assumg the forward voltage drop of the diodes the converter is 1 and the voltage drop of the power MOSFET is negligible sce R DS(on) is small. The theoretical calculations of the power dissipation of the reduced components is given by (24). Where T= π, D = 1, I D =4.991s (ω) and T 1 PD, avg DI Ddt 3. 15W T (24) P D, avg is average power loss one diode of the put rectifier. The efficiency improvement of 3W converter is calculated by (25). improvement 2 PD, avg 2.11% 3 (25) In general the efficiency enhancement is less than 2.11% due to the assumption of the zero voltage drop of switch. 5. Simulation results The proposed converter is simulated LT Spice I. Specifications and parameters of the converter are as follows: = 85 Rms, = 25 dc, i L1 = 2% of i L1, f = 1 khz and P = 3 W. Accordg to the design considerations, the circuit elements are obtaed as L 1 =L 2 = 2mH, C c =.62µF, and C = 12µF. To achieve PFC and regulated output voltage average current mode control is used. It cludes an ner current loop and outer voltage loop. Here capacitor voltages are sensed sce they follows put voltage which is given to one of the multiplier put. The output voltage is sensed and processed through voltage error amplifier which feeds the other put port of the multiplier. The output of the multiplier generates current reference which is compared with put current that is sensed from sum of the diode current. The output of the current error signal is compared with ramp signal to generate gate pulses. The put voltage and current waveforms simulation are shown Fig. 8 (a). It is observed that both are phase which depicts the property of power factor correction of the converter. Fig.8 (b) illustrates the output voltage and output current waveforms respectively. The capacitor voltage waveforms and ductor currents are shown Fig. 9 (a) and Fig.9 (b) and it can be observed that current waveforms of the ductors L 1 and L 2 are contuous which assure converter is operated CCM mode. Switch current and output diode current waveforms are shown Fig.9 (c). s 8

10 (a) (b) Fig 8. (a) Input voltage and current waveforms (b) Output voltage and current waveforms (a) 81

11 (b) (c) Fig 9. (a).capacitor voltage waveforms (b). Inductor current waveforms (c).switch and Diode current waveforms 6. Experimental results The theoretical analysis of the proposed converter is validated by experimental prototype with the same specifications of the modified bridgeless SEPIC PFC converter. Fig. 1(a) presents the experimental results of the put current and put voltage. It is noticed that the measured power factor is near to unity, sce voltage and current waveforms are phase. Output voltage and output current of the converter are shown Fig. 1(b). Capacitor voltage and ductor current (I L1 ) and (I L2 ) are shown Fig 1(c). Switch current (I S1 ) and output diode current (I D ) are presented Fig. 1(d).From the figure it is clearly witnessed, the output diode current is nearly half to the switch current. Fig. 11 (a) and Fig. 11 (b) illustrate put voltage, put current and output voltage, output current with change 7% load. The output voltage of the proposed converter is regulated usg compensator the output voltage feedback loop irrespective of the load change. Fig. 12 (a) shows the formation about experimental THD, Fig. 12 (b) presents put current harmonics frequency doma, which is the plot between put harmonic current and harmonic order. Here put current harmonics compared with the IEC standards and also conventional CCM converter Ref.24 to show the superiority of the proposed converter. It is evident that the proposed converter put harmonic current is lower than the conventional CCM converter and 82

12 follows the IEC standards. Fig.12 (c) shows the efficiency of the proposed converter as a function of output power comparison with conventional and contemporary topology Ref.24. It depicts that the proposed converter shows the superior performance than the other converters at various output power. [5/div] I [4A/div].1s/div (a) [1/div] I [1A/div].1s/div (b) 83

13 Cm [1/div] Cc [1/div].5s/div I L1 [2A/div] I L2 [1A/div].25us/div (c) 84

14 I S1 [2A/div] I D [2A/div].25us/div (d) Fig 1. (a) Input oltage and Current waveforms (b) Output voltage and Current waveforms (c) Capacitor voltage and Inductor Currents waveforms (d) Switch current and output diode current waveforms [5/div] I [5A/div].2s/div (a) 85

15 [1/div] I [1A/div].2s/div (b) Fig 11. With load variation (a) Input voltage and current (b) Output oltage and Output Current (a) 86

16 (b) (c) Fig 12. (a) Experimental THD of source current (b) Current harmonics compared with IEC and conventional converter (c) Efficiency as a function of output power 7. Conclusion In this study, modified bridgeless SEPIC under Contuous Conduction Mode for power factor correction is presented. The efficiency of the converter is improved and free from voltage and current stress. In addition, switch voltage is less than the output voltage and output diode current is reduced by nearly half of the switch current compared to conventional bridgeless sepic converter. It offers high static ga, lower conduction losses and suitable for high power applications. Also the switchg signal applied to the switches the circuit is same that simplifies the control. Theoretical and experimental results are provided of the proposed converter. 87

17 References [1]. C.M. Wang, A novel zero-voltage-switchg PWM boost rectifier with high power factor and low conduction losses, IEEE Transactions. Ind. Electron, 52 (25) [2]. IEC , International Electro technical Commission Genève, Switzerland, 1998 [3]. R. Itoh et. al., Sgle-phase buck rectifier employg voltage reversal circuit for susoidal put current wave shapg, IEE Proc. Electr. Power Appl., 146 (1999) [4]. R. Oruganti et. al., Inductor voltage control of buck-type sgle-phase ac-dc converter, IEEE Trans. Power Electron, 15 (2) [5]. M. A. Al-Saffar et. al., Integrated buck boost quadratic buck PFC rectifier for universal put applications, IEEE Trans. Power Electronics, 24 (29) [6]. W. Wei et. al., A novel bridgeless buck-boost PFC converter, IEEE power electronics specialists conference, (PESC) 28, pp [7]. K. Mok et. al., A sgle-stage bridgeless power factor correction rectifier based on fly back topology, IEEE ternational telecommunications energy conference, (INTELEC) 211, pp [8]. Y. Jang et. al., Bridgeless high-power-factor buck converter state-of-the-art, IEEE Trans Ind. Electron, 26 (211) [9]. L. Huber et. al., Performance evaluation of bridgeless PFC boost rectifiers, IEEE Trans Power Electron, 23 (28) [1]. W-Y. Choi et. al., Bridgeless boost rectifier with low conduction losses and reduced diode reverse-recovery problems, IEEE Trans Ind. Electron., 54 (27) [11]. E. H. Ismail, Bridgeless SEPIC rectifier with unity power factor and reduced conduction losses, IEEE Trans Ind. Electron, 56 (29) [12]. K.S. Muhammad et. al., ZCS Bridgeless Boost PFC Rectifier Usg Only Two Active Switches, IEEE Trans. Ind. Electron, 62 (215) [13]. A.A. Fardoun et. al., Bridgeless resonant pseudo boost PFC rectifier, IEEE Trans. Power Electron, 29 (214) [14]. A. Bouafassa et. al., Design and real time implementation of sgle phase boost power factor correction converter, ISA Transactions, 55 (215) [15]. M. Mahdavi et. al., Zero-current-transition bridgeless PFC without extra voltage and current stress, IEEE Trans. Ind. Electron, 56 (29) [16]. M. Mahdavi et. al., A new zero voltage transition bridgeless PFC with reduced conduction losses, Jour. of Power Electron, 9 (29) [17]. M. Mahdavi et. al., A new soft switchg bridgeless PFC without any extra switch, Int. Review. Electr. Engg, 3 (28) [18]. A. Sabzali et. al., New bridgeless PFC Sepic and Cuk rectifiers with low conduction and switchg losses, IEEE PEDS, pp , 29. [19]. M.R. Sahid et. al., A New AC-DC converter usg bridgeless SEPIC, IEEE Annual Conf. Industrial Electronics Society (IECON 21), pp , November 21. [2]. A. J. Sabzali et. al., New bridgeless DCM SEPIC and Cuk PFC rectifiers with low conduction and switchg losses, IEEE Trans. Ind. Appl., 47 (211) [21]. M. Mahdavi et. al., Bridgeless SEPIC PFC rectifier with reduced components and conduction losses, IEEE Trans Ind. Electron, 58 (211)

18 [22]. Jae-won Yang et. al., Bridgeless SEPIC Converter with a Ripple Free Input Current, IEEE Trans. Power Electron, 28 (213) [23]. C. G. Bianch et. al., High-Power-Factor Rectifier Usg the Modified SEPIC Converter Operatg Discontuous Conduction Mode, IEEE Transactions on Power Electronics, 3 (215) [24]. J.M. Kwon et. al., Contuous-conduction-mode SEPIC converter with low reverse-recovery loss for power factor correction, IEE Proc. Electr. Power Appl, 153 (26) [25]. C.S. Silva, Power factor correction with the UC3854, Unitrode Product and Applications Handbook. ( ). [26]. L. Dixon, High. Power factor pre-regulator usg the SEPIC converter, Unitrode Product and Applications Handbook. ( ). [27]. L.H.Dixon, Control loop design, SEPIC preregulator Example, Unitrode Product and Applications Handbook. (1993). 89